JPH05129598A - Overheat detector for power device - Google Patents

Overheat detector for power device

Info

Publication number
JPH05129598A
JPH05129598A JP3292581A JP29258191A JPH05129598A JP H05129598 A JPH05129598 A JP H05129598A JP 3292581 A JP3292581 A JP 3292581A JP 29258191 A JP29258191 A JP 29258191A JP H05129598 A JPH05129598 A JP H05129598A
Authority
JP
Japan
Prior art keywords
circuit
temperature
power device
detection
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3292581A
Other languages
Japanese (ja)
Other versions
JP3132587B2 (en
Inventor
Shinji Nishiura
真治 西浦
Tatsuhiko Fujihira
龍彦 藤平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP03292581A priority Critical patent/JP3132587B2/en
Priority to US07/796,266 priority patent/US5355123A/en
Publication of JPH05129598A publication Critical patent/JPH05129598A/en
Priority to US08/156,700 priority patent/US5349336A/en
Application granted granted Critical
Publication of JP3132587B2 publication Critical patent/JP3132587B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To form a temperature detector in a simple structure by connecting a diode in series with a MOSFET, applying a reverse bias to the diode, and connecting the other end of the diode to the GND. CONSTITUTION:A diode 1 and a depression type MOSFET(MOSFET) 2 having a source, a drain and a gate 22 are connected in series. The diode 1 is connected to a buffer 5 in which an FET is used at a midpoint of the MOSFET 2. The buffer 5 has a predetermined threshold voltage. The reverse leakage current of the diode 1 is varied depending upon the square root of temperature, and increased as the temperature rises. When an intermediate voltage Vc of the MOSFET 2 exceeds the threshold value of the buffer 5, it is set to output a signal. Thus, the detection signal of an abnormal temperature can be output, and damage of a power IC can be prevented by controlling it by using the detection signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、制御用パワーIC等の
半導体基板に形成され、そのパワーICに含まれるパワ
ーデバイスの異常温度を検出するパワーデバイスの過熱
検出回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power device overheat detection circuit which is formed on a semiconductor substrate such as a control power IC and detects an abnormal temperature of a power device included in the power IC.

【0002】[0002]

【従来の技術】制御用パワーICは、制御部とパワー部
を一つの半導体チップに構成したもので、制御ICとパ
ワー段の相互干渉を防ぐ必要がある。そのためには、絶
縁膜で分離する誘電体分離、PN接合で分離する接合分
離およびデバイスが基板と絶縁されるゲートによって制
御され、各デバイス自身のPN接合で分離される自己分
離の各種の方法がある。前2者はコスト高であるので、
自己分離法を採用できることが望ましい。
2. Description of the Related Art In a control power IC, a control section and a power section are formed on one semiconductor chip, and it is necessary to prevent mutual interference between the control IC and the power stage. For that purpose, various methods of dielectric isolation separated by an insulating film, junction separation separated by a PN junction, and self-separation separated by a PN junction of each device controlled by a gate insulated from a substrate are used. is there. The former two are costly, so
It is desirable to be able to adopt the self-separation method.

【0003】パワーデバイスは高電圧,大電流の用途に
使われるために、例えば負荷の急増や短絡などによって
定格電流を超える大電流が流れると、発熱によってパワ
ーデバイスが熱破壊する危険性がある。したがって、パ
ワーデバイスの温度を常時監視して所定温度を超える温
度異常すなわち過熱があった場合には、負荷回路を遮断
するなどの保護操作を行うことによって、パワーデバイ
スの熱破壊事故を防止することが求められる。
Since the power device is used for high voltage and large current, when a large current exceeding the rated current flows due to, for example, a sudden increase in load or a short circuit, there is a risk that the power device will be thermally destroyed due to heat generation. Therefore, the temperature of the power device is constantly monitored, and if there is a temperature abnormality that exceeds a predetermined temperature, that is, if there is overheating, a protective operation such as disconnecting the load circuit is performed to prevent a thermal breakdown accident of the power device. Is required.

【0004】パワーICの温度監視を行おうとする場
合、温度センサを含む過熱検出回路をパワーICと共通
の半導体基板上に作り込むことが温度の検出感度を高め
回路の構成を簡素化する上で有利であることはいうまで
もない。しかし、パワーICに自己分離法で形成した従
来の過熱検出回路は、基板に電源を接続し、その電位を
最高電位または最低電位とした例しかなく、パワーデバ
イスのように基板を出力端子とするものは発表されてい
ない。
When the temperature of the power IC is to be monitored, it is necessary to build an overheat detection circuit including a temperature sensor on the same semiconductor substrate as the power IC in order to increase the temperature detection sensitivity and simplify the circuit structure. It goes without saying that it is advantageous. However, in the conventional overheat detection circuit formed in the power IC by the self-separation method, there is only an example in which a power source is connected to the substrate and the potential thereof is set to the maximum potential or the minimum potential, and the substrate serves as an output terminal like a power device. Things have not been announced.

【0005】[0005]

【発明が解決しようとする課題】そのような過熱検出回
路は、負荷と高電位電源との間にスイッチング用のパワ
ーデバイスが接続されるハイサイド形には使用できる
が、負荷とGND電位との間にスイッチング用のパワー
デバイスが接続されるローサイド形には使用できない。
Such an overheat detecting circuit can be used for a high side type in which a power device for switching is connected between a load and a high potential power source, but the overheat detecting circuit is not connected to the load and the GND potential. It cannot be used for the low side type in which a power device for switching is connected.

【0006】本発明の目的は、半導体基板を出力端子と
して用いるパワーデバイスの温度検出を行う検出回路部
を簡素な構成で同一基板に自己分離型で形成でき、かつ
温度依存性を利用して検出温度領域で大きな信号を取り
出せるパワーデバイスの過熱検出回路を提供することに
ある。
An object of the present invention is that a detection circuit portion for detecting the temperature of a power device using a semiconductor substrate as an output terminal can be formed on the same substrate by a self-separation type with a simple structure, and the temperature dependence is used for detection. An object is to provide an overheat detection circuit for a power device that can extract a large signal in the temperature range.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、パワーデバイスと共通の半導体基板に
形成されてパワーデバイスの過熱を検出する回路であっ
て、デプレッション型MOSFETを用いた定電流電源
と、逆バイアスされ一側が低電位に、他側が前記定電流
電源に接続されたPN接合と、その定電流電源とPN接
合の中間点の電位が所定の値に達したことを判断して信
号を発する判断回路とを備えてなるものとする。
In order to achieve the above-mentioned object, the present invention is a circuit formed on a semiconductor substrate common to a power device to detect overheating of the power device, which uses a depletion type MOSFET. The constant current power source, the reverse biased one side to a low potential, the other side to the PN junction connected to the constant current power source, and the potential at the intermediate point between the constant current power source and the PN junction has reached a predetermined value. And a determination circuit that determines and issues a signal.

【0008】また本発明は、パワーデバイスと共通の基
板に形成されてパワーデバイスの過熱を検出する回路で
あって、それぞれデプレッション型MOSFETを用い
た定電流電源、逆バイアスされ一側が低電位に接続さ
れ、他側が前記定電流電源に接続されたPN接合ならび
にその定電流電源とPN接合の中間点の電位が所定の値
に達したことにより基板温度が所定の検出温度に達した
ことを判断して信号を発する判断回路を有する検出温度
の高い第一の検出回路および検出温度の低い第二の検出
回路と、基板温度が上昇して第一の検出回路の検出温度
を超えたときに信号を出力し、次いで基板温度が下降し
て第二の検出温度の検出温度以下になるまで前記信号を
接続して出力するヒステリシス回路とを備えてなるもの
とする。
Further, the present invention is a circuit for detecting overheating of a power device formed on a common substrate with the power device, each of which is a constant current power source using a depletion type MOSFET, and is reverse biased and one side is connected to a low potential. Then, it is determined that the substrate temperature has reached a predetermined detection temperature because the potential of the PN junction whose other side is connected to the constant current power source and the intermediate point between the constant current power source and the PN junction has reached a predetermined value. A detection circuit with a high detection temperature and a second detection circuit with a low detection temperature, and a signal when the substrate temperature rises and exceeds the detection temperature of the first detection circuit. A hysteresis circuit that outputs the signal and then outputs the signal by connecting the signal until the substrate temperature drops and becomes equal to or lower than the detected temperature of the second detected temperature.

【0009】また、デプレッション型MOSFETを用
いた定電流電源が使用できない場合には、デプレッショ
ン型MOSFETを用いた定電流電源の替わりに高電位
に接続された抵抗あるいはエンハンスメント型MOSF
ETを使用することも可能である。
When a constant current power source using a depletion type MOSFET cannot be used, a resistor or enhancement type MOSF connected to a high potential is used instead of the constant current power source using a depletion type MOSFET.
It is also possible to use ET.

【0010】そして、いずれの場合も逆バイアスされる
PN接合の低不純物濃度側の層が5×1013/cm2
上の不純物濃度を有することが有効である。
In any case, it is effective that the layer on the low impurity concentration side of the reverse biased PN junction has an impurity concentration of 5 × 10 13 / cm 2 or more.

【0011】[0011]

【作用】パワーデバイスと同一半導体基板に形成された
PN接合の逆もれ電流は、基板温度の上昇により増加す
る。この逆もれ電流の増加を直列接続されたデプレッシ
ョン型MOSFETの静特性を利用して電圧に変化する
ことにより変化の大きな電気信号に変換でき、この電圧
信号を判断回路で判断して過熱温度領域に達したとき
に、パワーデバイスを遮断するなどのための制御信号を
出すようにすれば、パワーICの熱破壊事故などを未然
に防止することができる。
The reverse leakage current of the PN junction formed on the same semiconductor substrate as the power device increases as the substrate temperature rises. This increase in reverse leakage current can be converted into an electric signal with a large change by changing it to a voltage by using the static characteristics of depletion type MOSFETs connected in series, and this voltage signal can be judged by a judgment circuit to determine the overheat temperature range. If the control signal for shutting off the power device or the like is issued when the temperature reaches, it is possible to prevent a thermal destruction accident of the power IC.

【0012】そしてパワーデバイスと同一半導体基板に
形成され、一側がGND電位にされるPN接合とそれに
直列接続されるデプレッション型MOSFETの中間点
の電位を利用して過熱を検出するため、基板をパワーデ
バイスの出力端子にすることが可能になる。
Then, since the overheat is detected by using the potential of the intermediate point of the PN junction formed on the same semiconductor substrate as the power device and having one side at the GND potential and the depletion type MOSFET connected in series to the PN junction, the substrate is powered. It becomes possible to make it the output terminal of the device.

【0013】さらに、互いに検出温度の異なる上記構成
の過熱検出回路2組とヒステリシス回路とを組み合わ
せ、報知信号の発信と停止との間に所定の温度幅を持た
せるように構成すれば、負荷の変動等によってパワーI
Cに生ずる短時間の温度変化に対して報知信号が繰り返
し出力されることを防止できるので、このような負荷変
動による温度変化を過熱状態と誤認して負荷遮断を行う
などの不都合を排除して信頼性の高い過熱検出を行うこ
とができる。
Further, if two sets of the overheat detection circuits having the above-mentioned constructions, which have different detection temperatures from each other, and the hysteresis circuit are combined so as to provide a predetermined temperature range between the transmission and the stop of the notification signal, the load can be reduced. Power I due to fluctuations
Since it is possible to prevent the notification signal from being repeatedly output with respect to a short-time temperature change that occurs in C, it is possible to eliminate the inconvenience of erroneously recognizing the temperature change due to the load change as an overheated state and cutting off the load. A reliable overheat detection can be performed.

【0014】また、逆もれ電流から電圧への変換のため
にはデプレッション型MOSFETの替わりに高電位に
接続された抵抗あるいはエンハンスメント型MOSFE
Tを用いても良い。
Further, in order to convert the reverse leakage current into voltage, instead of the depletion type MOSFET, a resistor or enhancement type MOSFE connected to a high potential is used.
You may use T.

【0015】[0015]

【実施例】図1は本発明の一実施例の過熱検出回路を構
成する半導体素子を示し、パワーデバイスとしての図2
に示したMOSFETと同一半導体基板に形成されてい
る。半導体基板は、n+ 基板11とその上に形成された
- エピタキシャル層12よりなり、このn- 層12に
+ 拡散層13,p- 拡散層14,n- 拡散層15,n
+ 拡散層16,17,18,19が形成され、n- 層1
2のn+ 層17,18にはさまれた表面の上に絶縁膜2
1を介してゲート電極22,p- 層14のn + 層19と
- 層12の露出部にはさまれた表面の上に絶縁膜23
を介してゲート電極24が多結晶シリコン層で形成され
ている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overheat detection circuit according to an embodiment of the present invention.
Fig. 2 shows a semiconductor device to be formed and is a power device.
It is formed on the same semiconductor substrate as the MOSFET shown in
It The semiconductor substrate is n+Substrate 11 and formed on it
n-The epitaxial layer 12-On layer 12
p+Diffusion layer 13, p-Diffusion layer 14, n-Diffusion layer 15, n
+Diffusion layers 16, 17, 18, 19 are formed, n-Layer 1
N of 2+Insulating film 2 on the surface sandwiched by layers 17 and 18
Through the gate electrode 22, p-N of layer 14 +Layer 19 and
n-The insulating film 23 is formed on the surface sandwiched between the exposed portions of the layer 12.
The gate electrode 24 is formed of a polycrystalline silicon layer through
ing.

【0016】基板表面に露出している接合の保護膜およ
び層間絶縁膜として絶縁膜25,26,27,28,2
9,30が形成され、コンタクトホールを通してp+
13に、またp+ 層13およびp- 層14に共通に接触
し、GND端子に接続される電極31、n+ 層16,1
7およびゲート電極22に接触し、VC 端子に接続され
る電極32、n+ 層18に接触し、VDD端子に接続され
る電極33いずれも金属によって形成されている。基板
の裏面側ではやはり金属よりなり、n+ 層11に出力電
極である出力端子VD に接続されたドレイン電極34が
接触している。
Insulating films 25, 26, 27, 28, 2 as a protective film for the junction and an interlayer insulating film exposed on the surface of the substrate.
Electrodes 31 and n + layers 16 and 1 which are formed to contact the p + layer 13 and the p + layer 13 and the p layer 14 in common through the contact holes and are connected to the GND terminal.
7 and the gate electrode 22, and the electrode 32 connected to the V C terminal and the electrode 33 connected to the n + layer 18 and connected to the V DD terminal are both made of metal. On the back surface side of the substrate, which is also made of metal, the drain electrode 34 connected to the output terminal V D , which is an output electrode, is in contact with the n + layer 11.

【0017】図2に示したMOSFETは、ドレイン電
極34に正の電圧がかけられているとき、ゲート電極2
4にしきい値以上の正の電圧を印加すると、p- 層14
のn + 層19とn- 層12の露出部とにはさまれた部分
が反転してnチャネルが生ずることにより、電極31か
らソース領域19,nチャネル,n- 層12,n+層1
1を経てドレイン電極34に電子が流れることにより導
通する。そしてオフ時に100〜200V以上であった
出力端子VD の電位はGNDに近くなる。
The MOSFET shown in FIG.
When a positive voltage is applied to the pole 34, the gate electrode 2
When a positive voltage above the threshold is applied to 4, p-Layer 14
N +Layers 19 and n-The part sandwiched between the exposed part of layer 12
Is inverted and an n-channel is generated, so that the electrode 31
Source region 19, n channel, n-Layer 12, n+Layer 1
The electrons flow to the drain electrode 34 via 1
Pass through. And it was 100-200V or more when off
Output terminal VDPotential becomes close to GND.

【0018】図3は図1に示した素子により構成される
回路図であり、図1の各部に対応する部分には同一の符
号が付されている。図1のp+ 層13とn+ 層16とよ
りなるダイオード1とn+ 層17をソース、n+ 層18
をドレインとしゲート電極22を備えたデプレッション
型MOSFET2とが直列接続されている。そして、ダ
イオード1とMOSFET2の中間点がFETなどを用
いたバッファ5に接続されている。
FIG. 3 is a circuit diagram composed of the elements shown in FIG. 1, and the portions corresponding to the respective portions in FIG. 1 are designated by the same reference numerals. Source p + layer 13 and n + more becomes a layer 16 diode 1 and the n + layer 17 in FIG. 1, n + layer 18
Is connected in series with the depletion type MOSFET 2 having a gate electrode 22 as a drain. The intermediate point between the diode 1 and the MOSFET 2 is connected to the buffer 5 using an FET or the like.

【0019】次に図4を引用して過熱検出動作について
説明する。図4の線40は中間点電位VC を変化させた
ときのMOSFET2の電流値であり、この値はMOS
FET2の形状,n- 層15の濃度等に依存する。線4
1,42,43,44,45,46はダイオード1の逆
もれ電流で、温度をT1 からT6 へ上昇させていったと
きの値である。図から分かるようにもれ電流は温度Tの
平方根√Tに依存して変化し、温度が上がると増加す
る。温度が低い時、例えば15℃で逆もれ電流が50×
10-15 Aのものは、例えば175℃で200nAに増
加する。この電流値もPN接合面積に依存して変化す
る。VC の電位は線40と線41〜46の交点できま
り、温度T1 のときにはV1 であるが、温度T5 のとき
にはV5 に変化する。従って、一定のしきい値電圧Vth
を有するバッファ5を用い、VC がVth以下になったと
きに信号を出力するようにすれば、異常温度の検出信号
を出力させることができる。この信号を制御信号に変化
し、駆動信号との優先順位を決める論理回路を通して図
2に示したパワーデバイスのMOSFETのゲート電極
24に入力して、その電流を制御すれば、パワーICの
破壊を防止することができる。
Next, referring to FIG. 4, the overheat detecting operation will be described. The line 40 in FIG. 4 is the current value of the MOSFET 2 when the midpoint potential V C is changed, and this value is the MOS value.
It depends on the shape of the FET 2, the concentration of the n layer 15, and the like. Line 4
1, 42, 43, 44, 45 and 46 are reverse leakage currents of the diode 1, which are values when the temperature is increased from T 1 to T 6 . As can be seen from the figure, the leakage current changes depending on the square root √T of the temperature T, and increases as the temperature rises. When the temperature is low, for example, at 15 ℃, the reverse leakage current is 50 ×.
Those of 10 −15 A increase to 200 nA at 175 ° C., for example. This current value also changes depending on the PN junction area. Potential of V C is determined by the intersection of line 40 and line 41 to 46, but when the temperatures T 1 is V 1, when the temperature T 5 is changed to V 5. Therefore, a constant threshold voltage V th
By using the buffer 5 having the above and outputting a signal when V C becomes equal to or lower than V th , an abnormal temperature detection signal can be output. If this signal is changed to a control signal and is input to the gate electrode 24 of the MOSFET of the power device shown in FIG. 2 through a logic circuit that determines the priority order with respect to the drive signal and the current is controlled, the power IC is destroyed. Can be prevented.

【0020】上述のようにMOSFETはオン,オフに
より出力端子VD の電位が変化するが、この出力電位に
より検出温度に誤差が生ずる。すなわちMOSFETが
オンして出力電位がGNDに近いときには低い検出温度
を示す傾向にある。これはn + 層16,p+ 層13,n
- 層12で形成される寄生トランジスタの電流増幅によ
るものと考えられる。
As described above, the MOSFET is turned on and off.
Output terminal VDThe potential of changes, but
An error occurs in the detected temperature. That is, MOSFET
Low detection temperature when output potential is close to GND after turning on
Tend to show. This is n +Layer 16, p+Layers 13, n
-Due to the current amplification of the parasitic transistor formed in layer 12,
It is considered to be one.

【0021】図5はp+ 層13の不純物濃度を変えて検
出温度誤差を測定した結果である。p+ 層13の濃度を
高めて寄生トランジスタのhFEを抑えることにより、誤
差が抑制されることがわかる。制御回路の設計にもよる
がp+ 層13の濃度を5×1013/cm2 以上とするこ
とで実用的な過熱検出回路を形成することができた。
FIG. 5 shows the results of measuring the detection temperature error by changing the impurity concentration of the p + layer 13. It can be seen that the error is suppressed by increasing the concentration of the p + layer 13 and suppressing the h FE of the parasitic transistor. Although depending on the design of the control circuit, a practical overheat detection circuit could be formed by setting the concentration of the p + layer 13 to 5 × 10 13 / cm 2 or more.

【0022】図6は第二の本発明の実施例である過熱検
出回路を示す回路構成図である。この場合はダイオード
1およびデプレッション型MOSFET2が直列接続さ
れた第一の検出回路61とそれと同一半導体基板に形成
されたダイオード3およびデプレッション型MOSFE
T2とが直列接続された第二の検出回路62とを有す
る。そして、第一の検出回路61に接続されるバッファ
5の出力を反転して出力するインバータ51の出力と第
二の検出回路62に接続されるバッファ5の出力とを受
けて合成出力VX を出力する相互にフィードバック結合
された一対のNAND回路52,53を備える。例えば
この過熱検出回路におけるダイオード1のPN接合面積
をダイオード3のPN接合面積より小さくしておくこと
により第一,第二の検出回路のVC がVth以下になる検
出温度を変えることができる。
FIG. 6 is a circuit diagram showing an overheat detecting circuit according to the second embodiment of the present invention. In this case, the first detection circuit 61 in which the diode 1 and the depletion type MOSFET 2 are connected in series, and the diode 3 and the depletion type MOSFET formed on the same semiconductor substrate as the first detection circuit 61.
T2 and the second detection circuit 62 connected in series. Then, it receives the output of the inverter 51 that inverts and outputs the output of the buffer 5 connected to the first detection circuit 61 and the output of the buffer 5 connected to the second detection circuit 62, and outputs the combined output V X. It is provided with a pair of NAND circuits 52 and 53 that are output and feedback-coupled to each other. For example, by setting the PN junction area of the diode 1 in this overheat detection circuit smaller than the PN junction area of the diode 3, the detection temperature at which V C of the first and second detection circuits becomes V th or less can be changed. ..

【0023】例えば、ダイオード1の接合面積をダイオ
ード3の接合面積の1/4〜1/5にすると、第一検出
回路61の検出温度は180℃、第二検出回路の検出温
度は155℃となる。これにより、半導体基板の温度が
180℃を超えると、出力V X はL→Hとなり、再び1
80℃より下がってもそのままで、155℃より基板温
度が下がるとはじめてH→Lに出力VX が変化する。こ
のようにして20℃の検出誤差があっても出力VX の繰
り返し変化が起こることがなく、安定した制御ができ
る。
For example, if the junction area of the diode 1 is
If 1/4 to 1/5 of the joint area of the card 3 is used, the first detection
The detection temperature of the circuit 61 is 180 ° C, the detection temperature of the second detection circuit
The temperature is 155 ° C. As a result, the temperature of the semiconductor substrate
Output V above 180 ° C XBecomes L → H, and becomes 1 again
Even if the temperature falls below 80 ° C, the substrate temperature remains unchanged from 155 ° C.
Output V from H to L for the first time when the degree decreasesXChanges. This
Even if there is a detection error of 20 ° C, the output VXOf
Stable control can be performed without any change in return.
It

【0024】図7はパワーデバイスが絶縁ゲートバイポ
ーラトランジスタ(IGBT)の場合を示し、この場合
は図1のn+ 基板11の代わりにp+ 基板10が用いら
れているが、p+ 層13とn- 層12よりなるダイオー
ドおよびn- 層15、n+ 層17,18およびゲート電
極22からなるMOSFETは図1と同様に形成できる
ことがわかる。また、本発明のいずれも導電型を逆にし
たpチャネル絶縁ゲート型のパワーデバイスに対しても
適用できることはいうまでもない。その場合はGNDは
最高電位となる。
FIG. 7 shows the case the power device is a insulated gate bipolar transistor (IGBT), but this case is p + substrate 10 is used instead of the n + substrate 11 of FIG. 1, the p + layer 13 It can be seen that the diode formed of the n layer 12 and the MOSFET formed of the n layer 15, the n + layers 17 and 18 and the gate electrode 22 can be formed in the same manner as in FIG. Further, it goes without saying that any of the present invention can be applied to a p-channel insulated gate power device in which the conductivity type is reversed. In that case, GND becomes the highest potential.

【0025】以上の実施例のいずれの場合においても、
デプレッション型MOSFETを抵抗あるいはエンハン
スメント型MOSFETで置き替えることが可能であ
る。この場合、抵抗にはn- 層やn+ 層,多結晶シリコ
ン層が利用できる。また、エンハンスメント型MOSF
ETのゲートはVDDに接続する。ただし、抵抗あるいは
エンハンスメント型MOSFETを利用した場合には、
高電位のVDD端子の電位が変化すると検出温度にも若干
の変化が生ずるので注意を要する。
In any of the above embodiments,
It is possible to replace the depletion type MOSFET with a resistor or an enhancement type MOSFET. In this case, the n layer, the n + layer, and the polycrystalline silicon layer can be used for the resistor. In addition, enhancement type MOSF
The gate of ET is connected to V DD . However, if a resistance or enhancement type MOSFET is used,
It should be noted that when the potential of the high potential V DD terminal changes, the detected temperature also changes slightly.

【0026】図8はデプレッション型MOSFETの替
わりに抵抗120を用いた場合の実施例の回路を、図9
はエンハンスメント型MOSFET220を用いた場合
の実施例の回路を示す。エンハンスメント型MOSFE
T220を用いた場合はゲート電極22は配線33によ
ってVDDに接続するのが良い。
FIG. 8 shows a circuit of an embodiment in which a resistor 120 is used instead of the depletion type MOSFET, and FIG.
Shows the circuit of the embodiment when the enhancement type MOSFET 220 is used. Enhancement type MOSFE
When T220 is used, the gate electrode 22 is preferably connected to V DD by the wiring 33.

【0027】図10,図11は図8の抵抗120を用い
た実施例に対応する主要部分の断面図であり、図10は
抵抗120に拡散抵抗層121を用いた場合、図11は
抵抗120にデプレッション型MOSFET2のゲート
電極22に用いているものと同じ多結晶シリコン層を利
用した多結晶シリコン抵抗層122を用いた場合であ
る。いずれの場合にも製造プロセスは図1に示した実施
例のものと同じプロセスで実施できる。
10 and 11 are sectional views of a main portion corresponding to the embodiment using the resistor 120 of FIG. 8. FIG. 10 shows a case where a diffused resistance layer 121 is used for the resistor 120, and FIG. In this case, the polycrystalline silicon resistance layer 122 using the same polycrystalline silicon layer as that used for the gate electrode 22 of the depletion type MOSFET 2 is used. In any case, the manufacturing process can be carried out by the same process as that of the embodiment shown in FIG.

【0028】図12は、デプレッション型MOSFET
2の替わりにエンハンスメント型MOSFET220を
用いた場合の図9の回路の実施例に対応する主要部分の
断面図である。図1との違いはn- 拡散層15が不要な
ことと、ゲート電極22が配線33によりVDDに接続さ
れていることである。以上に実施例を示した抵抗やエン
ハンスメント型MOSFETを用いる例では、先に述べ
たデプレッション型MOSFETを用いる例に比較し
て、例えば、図10では図1でのゲート電極22を形成
するための多結晶シリコン層の堆積プロセスが不要にな
り、図11,図12では図1でのn- 拡散層の形成プロ
セスが不要になるので、低コスト化の面でメリットがあ
るが、VDDの電圧が変動すると加熱検出温度に若干の変
化が生ずるというデメリットもあるので、用途によって
使い分けが必要である。
FIG. 12 shows a depletion type MOSFET.
FIG. 10 is a cross-sectional view of a main portion corresponding to the example of the circuit in FIG. 9 when an enhancement type MOSFET 220 is used instead of 2. The difference from FIG. 1 is that the n diffusion layer 15 is unnecessary and the gate electrode 22 is connected to V DD by the wiring 33. In the example of using the resistance or enhancement type MOSFET described in the above embodiment, as compared with the example of using the depletion type MOSFET described above, for example, in FIG. 10, a large number of layers for forming the gate electrode 22 in FIG. 1 is formed. Since the process of depositing the crystalline silicon layer is unnecessary and the process of forming the n diffusion layer in FIG. 1 is not necessary in FIGS. 11 and 12, there is an advantage in cost reduction, but the voltage of V DD is If it fluctuates, there is a demerit that the heating detection temperature slightly changes, so it is necessary to use it properly depending on the application.

【0029】[0029]

【発明の効果】本発明は、パワーデバイスと同一半導体
基板に形成されたダイオードと定電流電源としてのデプ
レッション型MOSFETを直列接続し、ダイオードに
逆バイアスを印加し、ダイオードのPN接合のP側ある
いはN側をGNDの最低電位あるいは最高電位に接続す
ることにより、基板温度の変化によるダイオードとMO
SFETの中間点の電位変化を利用して基板温度の異常
を検出することができ、ローサイド形に適用可能の自己
分離型パワーICにおけるパワーデバイスの過熱検出回
路を得ることができた。また一対の検出回路の出力をフ
リップフロップと接続することにより、二つの検出温度
の間でヒステリシス動作を行う安定した過熱検出回路を
得ることができた。
According to the present invention, a diode formed on the same semiconductor substrate as a power device and a depletion type MOSFET as a constant current power source are connected in series, a reverse bias is applied to the diode, and the P side of the PN junction of the diode or By connecting the N side to the minimum or maximum potential of GND, the diode and MO
An abnormality in the substrate temperature can be detected by utilizing the potential change at the intermediate point of the SFET, and an overheat detection circuit for a power device in a self-isolated power IC applicable to the low side type can be obtained. Further, by connecting the outputs of the pair of detection circuits to the flip-flop, it was possible to obtain a stable overheat detection circuit that performs a hysteresis operation between two detection temperatures.

【0030】そしてダイオードの低不純物濃度側の層の
不純物濃度を5×1013/cm2 以上とすることによ
り、パワーデバイスのオン時の検出温度の誤差を抑える
ことができた。
By setting the impurity concentration of the layer on the low impurity concentration side of the diode to 5 × 10 13 / cm 2 or more, the error in the detected temperature when the power device is turned on can be suppressed.

【0031】また、デプレッション型MOSFETの替
わりに抵抗あるいはエンハンスメント型MOSFETを
利用した場合にも以上とほぼ同じ結果が得られたが、電
源電位の変化により検出温度に若干の変化が生じるとい
うデメリットがある。
Also, when a resistor or an enhancement type MOSFET is used instead of the depletion type MOSFET, almost the same result as the above is obtained, but there is a demerit that the detection temperature slightly changes due to the change of the power supply potential. ..

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の過熱検出回路を構成する素
子の断面図
FIG. 1 is a sectional view of an element constituting an overheat detection circuit according to an embodiment of the present invention.

【図2】図1の回路で保護されるMOSFETの断面図2 is a cross-sectional view of a MOSFET protected by the circuit of FIG.

【図3】本発明の一実施例の過熱検出回路の回路図FIG. 3 is a circuit diagram of an overheat detection circuit according to an embodiment of the present invention.

【図4】図3の実施例の動作を示す電位とMOSFET
の電流およびダイオードの逆もれ電流の関係線図
FIG. 4 is a potential and MOSFET showing the operation of the embodiment of FIG.
Diagram of the current of the diode and the reverse leakage current of the diode

【図5】ダイオードを構成するp+ 層の濃度と検出温度
誤差の関係線図
FIG. 5 is a diagram showing the relationship between the concentration of the p + layer forming the diode and the detected temperature error.

【図6】別の本発明の一実施例の回路図FIG. 6 is a circuit diagram of another embodiment of the present invention.

【図7】本発明の異なる実施例のIGBTを保護する過
熱検出回路を構成する素子の断面図
FIG. 7 is a cross-sectional view of an element that constitutes an overheat detection circuit that protects an IGBT according to another embodiment of the present invention.

【図8】本発明の異なる実施例の過熱検出回路の回路図FIG. 8 is a circuit diagram of an overheat detection circuit according to another embodiment of the present invention.

【図9】本発明の更に異なる実施例の過熱検出回路の回
路図
FIG. 9 is a circuit diagram of an overheat detection circuit according to still another embodiment of the present invention.

【図10】本発明の異なる実施例の過熱検出回路を構成
する素子の断面図
FIG. 10 is a sectional view of elements constituting an overheat detection circuit according to another embodiment of the present invention.

【図11】本発明の異なる実施例の過熱検出回路を構成
する素子の断面図
FIG. 11 is a cross-sectional view of elements constituting an overheat detection circuit according to another embodiment of the present invention.

【図12】本発明の更に異なる実施例の過熱検出回路を
構成する素子の断面図
FIG. 12 is a cross-sectional view of elements constituting an overheat detection circuit according to still another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 ダイオード 2 デプレッション型MOSFET 3 ダイオード 5 バッファ 61 第一検出回路 62 第二検出回路 63 ヒステリシス回路 VC 中間点電位 120 抵抗 220 エンハンスメント型MOSFETDESCRIPTION OF SYMBOLS 1 diode 2 depletion type MOSFET 3 diode 5 buffer 61 first detection circuit 62 second detection circuit 63 hysteresis circuit V C midpoint potential 120 resistance 220 enhancement type MOSFET

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // H01L 23/58 7220−4M H01L 23/56 D ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location // H01L 23/58 7220-4M H01L 23/56 D

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】パワーデバイスと共通の半導体基板に形成
されてパワーデバイスの過熱を検出する回路であって、
デプレッション型MOSFETを用いた定電流電源と、
逆バイアスされ一側が低電位に、他側が前記定電流電源
に接続されたPN接合と、その定電流電源とPN接合の
中間点の電位が所定の値に達したことを判断して信号を
発する判断回路とを備えてなることを特徴とするパワー
デバイスの過熱検出回路。
1. A circuit formed on a semiconductor substrate common to a power device to detect overheating of the power device, the circuit comprising:
Constant current power supply using depletion type MOSFET,
A signal is issued by determining that the potential of the reverse biased one side has a low potential, the other side has been connected to the constant current power source, and the potential at the intermediate point between the constant current power source and the PN junction has reached a predetermined value. An overheat detection circuit for a power device, comprising: a determination circuit.
【請求項2】パワーデバイスと共通の半導体基板に形成
されてパワーデバイスの過熱を検出する回路であって、
それぞれデプレッション型MOSFETを用いた定電流
電源、逆バイアスされ一側が低電位に接続され、他側が
前記定電流電源に接続されたPN接合ならびにその定電
流電源とPN接合の中間点の電位が所定の値に達したこ
とにより基板温度が所定の温度に達したことを判断して
信号を発する判断回路を有する検出温度の高い第一の検
出回路および検出温度の低い第二の検出回路と、基板温
度が上昇して第一の検出回路の検出温度を超えたときに
信号を出力し、次いで基板温度が下降して第二の検出温
度の検出温度以下になるまで前記信号を接続して出力す
るヒステリシス回路とを備えてなることを特徴とするパ
ワーデバイスの過熱検出回路。
2. A circuit which is formed on a semiconductor substrate common to a power device and detects overheating of the power device,
A constant current power source using depletion type MOSFETs, a reverse biased one side is connected to a low potential, and the other side is connected to the constant current power source and a PN junction and a potential at an intermediate point between the constant current power source and the PN junction is predetermined. The first detection circuit having a high detection temperature and the second detection circuit having a low detection temperature, which has a determination circuit that determines that the substrate temperature has reached a predetermined temperature when the temperature reaches a predetermined value and issues a signal, and the substrate temperature. A signal is output when the temperature rises and exceeds the detection temperature of the first detection circuit, and then the signal is connected and output until the substrate temperature decreases and becomes equal to or lower than the detection temperature of the second detection temperature. An overheat detection circuit for a power device, comprising: a circuit.
【請求項3】請求項1あるいは2記載の回路において、
逆バイアスされるPN接合の低不純物濃度側の層が5×
1013/cm2 以上の不純物濃度を有するパワーデバイ
スの過熱検出回路。
3. The circuit according to claim 1 or 2,
The layer on the low impurity concentration side of the reverse biased PN junction is 5 ×
An overheat detecting circuit for a power device having an impurity concentration of 10 13 / cm 2 or more.
【請求項4】パワーデバイスと共通の半導体基板に形成
されてパワーデバイスの過熱を検出する回路であって、
高電位に接続された抵抗と、逆バイアスされ一側が低電
位に、他側が前記抵抗に接続されたPN接合と、その抵
抗とPN接合の中間点の電位が所定の値に達したことを
判断して信号を発する判断回路とを備えてなることを特
徴とするパワーデバイスの過熱検出回路。
4. A circuit which is formed on a semiconductor substrate common to a power device and detects overheating of the power device,
Judge that the resistance connected to a high potential, the reverse biased one side to a low potential, the other side connected to the resistance, and the potential at the midpoint between the resistance and the PN junction have reached a predetermined value. And a decision circuit for issuing a signal, and an overheat detection circuit for a power device.
【請求項5】パワーデバイスと共通の半導体基板に形成
されてパワーデバイスの過熱を検出する回路であって、
それぞれ高電位に接続された抵抗、逆バイアスされ一側
が低電位に接続され、他側が前記抵抗に接続されたPN
接合ならびにその抵抗とPN接合の中間点の電位が所定
の値に達したことにより基板温度が所定の温度に達した
ことを判断して信号を発する判断回路を有する検出温度
の高い第一の検出回路および検出温度の低い第二の検出
回路と、基板温度が上昇して第一の検出回路の検出温度
を超えたときに信号を出力し、次いで基板温度が下降し
て第二の検出温度の検出温度以下になるまで前記信号を
接続して出力するヒステリシス回路とを備えてなること
を特徴とするパワーデバイスの過熱検出回路。
5. A circuit which is formed on a semiconductor substrate common to a power device and detects overheating of the power device,
A resistor connected to a high potential, respectively, and a reverse biased PN with one side connected to a low potential and the other side connected to the resistor
The first detection with a high detection temperature, which has a determination circuit that issues a signal by determining that the substrate temperature has reached a predetermined temperature when the potential of the junction and the intermediate point between its resistance and the PN junction has reached a predetermined value. Circuit and a second detection circuit with a low detection temperature, outputs a signal when the substrate temperature rises and exceeds the detection temperature of the first detection circuit, and then the substrate temperature falls and the second detection temperature An overheat detection circuit for a power device, comprising: a hysteresis circuit that connects and outputs the signal until the temperature becomes equal to or lower than a detection temperature.
【請求項6】請求項4あるいは5記載の回路において、
逆バイアスされるPN接合の低不純物濃度側の層が5×
1013/cm2 以上の不純物濃度を有するパワーデバイ
スの過熱検出回路。
6. The circuit according to claim 4 or 5,
The layer on the low impurity concentration side of the reverse biased PN junction is 5 ×
An overheat detecting circuit for a power device having an impurity concentration of 10 13 / cm 2 or more.
【請求項7】パワーデバイスと共通の半導体基板に形成
されてパワーデバイスの過熱を検出する回路であって、
高電位に接続されたエンハンスメント型MOSFET
と、逆バイアスされ一側が低電位に、他側が前記エンハ
ンスメント型MOSに接続されたPN接合と、そのエン
ハンスメント型MOSとPN接合の中間点の電位が所定
の値に達したことを判断して信号を発する判断回路とを
備えてなることを特徴とするパワーデバイスの過熱検出
回路。
7. A circuit which is formed on a semiconductor substrate common to a power device and detects overheating of the power device,
Enhancement type MOSFET connected to high potential
Then, it is judged that the reverse biased one side has a low potential, the other side has the PN junction connected to the enhancement type MOS, and the potential at the intermediate point between the enhancement type MOS and the PN junction has reached a predetermined value. And an overheat detection circuit for a power device, comprising:
【請求項8】パワーデバイスと共通の半導体基板に形成
されてパワーデバイスの過熱を検出する回路であって、
それぞれ高電位に接続されたエンハンスメント型MOS
FET、逆バイアスされ一側が低電位に接続され、他側
が前記エンハンスメント型MOSFETに接続されたP
N接合ならびにその抵抗とPN接合の中間点の電位が所
定の値に達したことにより基板温度が所定の温度に達し
たことを判断して信号を発する判断回路を有する検出温
度の高い第一の検出回路および検出温度の低い第二の検
出回路と、基板温度が上昇して第一の検出回路の検出温
度を超えたときに信号を出力し、次いで基板温度が下降
して第二の検出温度の検出温度以下になるまで前記信号
を接続して出力するヒステリシス回路とを備えてなるこ
とを特徴とするパワーデバイスの過熱検出回路。
8. A circuit formed on a semiconductor substrate common to a power device to detect overheating of the power device, the circuit comprising:
Enhancement type MOS connected to high potential
FET, reverse biased P connected to one side at low potential and the other side connected to the enhancement MOSFET
A first detection circuit having a high detection temperature, which has a judgment circuit for judging that the substrate temperature has reached a predetermined temperature when the potential at the intermediate point between the N junction and its resistance and the PN junction has reached a predetermined value A detection circuit and a second detection circuit with a low detection temperature, and outputs a signal when the substrate temperature rises and exceeds the detection temperature of the first detection circuit, and then the substrate temperature falls and the second detection temperature And a hysteresis circuit for connecting and outputting the signal until the detected temperature becomes equal to or lower than the detection temperature.
【請求項9】請求項7あるいは8記載の回路において、
逆バイアスされるPN接合の低不純物濃度側の層が5×
1013/cm2 以上の不純物濃度を有するパワーデバイ
スの過熱検出回路。
9. The circuit according to claim 7 or 8,
The layer on the low impurity concentration side of the reverse biased PN junction is 5 ×
An overheat detecting circuit for a power device having an impurity concentration of 10 13 / cm 2 or more.
JP03292581A 1990-07-17 1991-11-08 Power device overheat detection circuit Expired - Fee Related JP3132587B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP03292581A JP3132587B2 (en) 1990-11-26 1991-11-08 Power device overheat detection circuit
US07/796,266 US5355123A (en) 1990-07-17 1991-11-21 Overheating detection circuit for detecting overheating of a power device
US08/156,700 US5349336A (en) 1990-07-17 1993-11-24 Overheating detection circuit for detecting overheating of a power device

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP32214390 1990-11-26
JP2-322143 1991-09-10
JP3-229238 1991-09-10
JP22923891 1991-09-10
JP03292581A JP3132587B2 (en) 1990-11-26 1991-11-08 Power device overheat detection circuit

Publications (2)

Publication Number Publication Date
JPH05129598A true JPH05129598A (en) 1993-05-25
JP3132587B2 JP3132587B2 (en) 2001-02-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161920A (en) * 1993-12-08 1995-06-23 Nec Corp Semiconductor integrated circuit
US5796290A (en) * 1995-10-26 1998-08-18 Nec Corporation Temperature detection method and circuit using MOSFET
US6268628B1 (en) 1998-04-03 2001-07-31 Fuji Electric Co., Ltd. Depletion type MOS semiconductor device and MOS power IC
US6667660B2 (en) 2000-07-28 2003-12-23 Infineon Technologies Ag Temperature sensor and circuit configuration for controlling the gain of an amplifier circuit
KR100870976B1 (en) * 2005-12-20 2008-12-01 산켄덴키 가부시키가이샤 Overheat protecting circuit of power supply unit and direct current power supply unit
JP2009145170A (en) * 2007-12-13 2009-07-02 Fuji Electric Device Technology Co Ltd Temperature sensor circuit
US7723802B2 (en) 2004-08-27 2010-05-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US8803190B2 (en) 2012-04-02 2014-08-12 Fuji Electric Co., Ltd. Semiconductor device
US20210073438A1 (en) * 2018-06-05 2021-03-11 Mitsubishi Electric Corporation Optimization system, optimization method, control circuit and computer readable storage medium

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KR101812141B1 (en) * 2017-06-05 2018-01-25 김태영 Sawdust crushing device for composting

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161920A (en) * 1993-12-08 1995-06-23 Nec Corp Semiconductor integrated circuit
US5796290A (en) * 1995-10-26 1998-08-18 Nec Corporation Temperature detection method and circuit using MOSFET
US6268628B1 (en) 1998-04-03 2001-07-31 Fuji Electric Co., Ltd. Depletion type MOS semiconductor device and MOS power IC
US6528826B2 (en) 1998-04-03 2003-03-04 Fuji Electric Co., Ltd. Depletion type MOS semiconductor device and MOS power IC
US6667660B2 (en) 2000-07-28 2003-12-23 Infineon Technologies Ag Temperature sensor and circuit configuration for controlling the gain of an amplifier circuit
US7723802B2 (en) 2004-08-27 2010-05-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR100870976B1 (en) * 2005-12-20 2008-12-01 산켄덴키 가부시키가이샤 Overheat protecting circuit of power supply unit and direct current power supply unit
JP2009145170A (en) * 2007-12-13 2009-07-02 Fuji Electric Device Technology Co Ltd Temperature sensor circuit
US8803190B2 (en) 2012-04-02 2014-08-12 Fuji Electric Co., Ltd. Semiconductor device
US20210073438A1 (en) * 2018-06-05 2021-03-11 Mitsubishi Electric Corporation Optimization system, optimization method, control circuit and computer readable storage medium

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