JPH05129596A - Method of forming gate oxide film - Google Patents

Method of forming gate oxide film

Info

Publication number
JPH05129596A
JPH05129596A JP31980091A JP31980091A JPH05129596A JP H05129596 A JPH05129596 A JP H05129596A JP 31980091 A JP31980091 A JP 31980091A JP 31980091 A JP31980091 A JP 31980091A JP H05129596 A JPH05129596 A JP H05129596A
Authority
JP
Japan
Prior art keywords
oxide film
gate oxide
oxidation
forming
dry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP31980091A
Other languages
Japanese (ja)
Inventor
Takaaki Shiota
孝明 塩多
Takayuki Shingyouchi
隆之 新行内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP31980091A priority Critical patent/JPH05129596A/en
Publication of JPH05129596A publication Critical patent/JPH05129596A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a method of forming a gate oxide film in which an insulation breakdown strength is enhanced. CONSTITUTION:A method for forming a gate oxide film on a silicon wafer comprises the steps of oxidizing it in a dry atmosphere and then oxidizing it in a steam atmosphere. When a gate insulating film of a MOS transistor is formed, its gate oxide film is formed by footing a part having a thickness of 20-99% of the thickness of the gate oxide film by a dry oxidizing method and then forming a residual part by a wet oxidizing method. As a result, an insulation breakdown strength of the gate oxide film is enhanced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はシリコンウェーハを熱酸
化することにより形成されるゲート酸化膜の形成方法、
例えばMOS構造のゲート絶縁膜として用いられる熱酸
化膜の形成方法の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate oxide film formed by thermally oxidizing a silicon wafer,
For example, the present invention relates to improvement of a method of forming a thermal oxide film used as a gate insulating film of a MOS structure.

【0002】[0002]

【従来の技術】従来、シリコンウェーハに形成したMO
Sトランジスタにおけるゲート絶縁膜のための熱酸化膜
は、ドライO2酸化法により形成する場合と、ウエット
2酸化法により形成する場合とがあった。前者は、使
用する酸素中の水分を、露点が−80℃以下になる程度
に除去し、きわめて緻密な熱酸化膜(SiO2)を得る
ことができる。後者にあっては、水蒸気を酸化剤とする
ため、酸化速度がドライ酸化に比べて速くなる。
2. Description of the Related Art Conventionally, MO formed on a silicon wafer
The thermal oxide film for the gate insulating film in the S transistor may be formed by the dry O 2 oxidation method or the wet O 2 oxidation method. The former can remove the water in oxygen used to the extent that the dew point becomes −80 ° C. or lower to obtain a very dense thermal oxide film (SiO 2 ). In the latter case, since steam is used as the oxidant, the oxidization rate becomes faster than that in the dry oxidization.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
ドライ酸化のみにより形成された熱酸化膜の場合は、こ
れをゲート絶縁膜として使用したとき、低電界で絶縁破
壊を起こすという課題があった。また、ウエット酸化の
みにより形成された熱酸化膜の場合は、これをゲート酸
化膜として使用したとき、Cモード(真性破壊といわれ
る)での破壊電界が若干低い傾向が見られる。
However, the conventional thermal oxide film formed only by dry oxidation has a problem that when it is used as a gate insulating film, dielectric breakdown occurs at a low electric field. In the case of a thermal oxide film formed only by wet oxidation, when this is used as a gate oxide film, the breakdown electric field in C mode (called intrinsic breakdown) tends to be slightly low.

【0004】そこで、本発明は、絶縁耐圧を高めたゲー
ト酸化膜の形成方法を提供することを、その目的として
いる。
Therefore, an object of the present invention is to provide a method for forming a gate oxide film having a high dielectric strength voltage.

【0005】[0005]

【課題を解決するための手段】本発明は、シリコンウェ
ーハの表面にゲート酸化膜を形成するゲート酸化膜の形
成方法において、上記ゲート酸化膜は、乾燥酸素雰囲気
による酸化後、水蒸気を含む雰囲気で酸化するゲート酸
化膜の形成方法である。
The present invention provides a method for forming a gate oxide film on a surface of a silicon wafer, wherein the gate oxide film is oxidized in a dry oxygen atmosphere and then in an atmosphere containing water vapor. This is a method of forming a gate oxide film for oxidation.

【0006】[0006]

【作用】MOSトランジスタのゲート絶縁膜を形成する
にあたり、目的とするゲート絶縁膜は、例えばそのうち
の20〜99%の厚さの部分をドライ酸化で形成した
後、残りの部分をウエット酸化(スチーム酸化を含む)
で形成する。この結果、MOSトランジスタのゲート絶
縁膜の絶縁破壊耐圧を高めることができる。ドライ酸化
により界面を平坦化し、電界の集中を回避するととも
に、ウエット酸化によって欠陥を安定化し、絶縁破壊耐
圧を高めるものである。
In forming the gate insulating film of the MOS transistor, the target gate insulating film is formed by, for example, dry-oxidizing a portion having a thickness of 20 to 99%, and then wet-oxidizing (steam) the remaining portion. (Including oxidation)
To form. As a result, the breakdown voltage of the gate insulating film of the MOS transistor can be increased. The interface is flattened by dry oxidation to avoid concentration of an electric field, and defects are stabilized by wet oxidation to increase dielectric breakdown voltage.

【0007】[0007]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1(A)〜(E)は本発明に係るゲート酸化膜
の形成方法の実施例を示すグラフである。このグラフに
あって、横軸は絶縁破壊電界(メガボルト/cm)を、
縦軸は頻度(%)を、それぞれ示している。この実施例
では、シリコンミラーウェーハ(口径5インチ、P型
(100)、抵抗値10Ωcm、CZウェーハ)30枚
を酸化炉に入れ、表1およびグラフに示す雰囲気にて9
00℃で熱処理した約25nmの厚さのゲート酸化膜を
形成した。そして、このシリコンウェーハのゲート酸化
膜上にアルミニウム電極を形成、被着して常法にしたが
って絶縁破壊電界を測定した。
Embodiments of the present invention will be described below with reference to the drawings. 1A to 1E are graphs showing an embodiment of a method for forming a gate oxide film according to the present invention. In this graph, the horizontal axis is the breakdown electric field (megavolts / cm),
The vertical axis represents the frequency (%). In this example, 30 silicon mirror wafers (diameter 5 inches, P-type (100), resistance value 10 Ωcm, CZ wafer) were placed in an oxidation furnace and subjected to 9 atmospheres in the atmosphere shown in Table 1 and graphs.
A gate oxide film having a thickness of about 25 nm was formed by heat treatment at 00 ° C. Then, an aluminum electrode was formed and deposited on the gate oxide film of this silicon wafer, and the dielectric breakdown electric field was measured according to a conventional method.

【0008】[0008]

【表1】 [Table 1]

【0009】また、この結果を図1にてヒストグラムに
より示している。同図にて、(A)はドライ酸化を85
分間行い、ゲート酸化膜の厚さを25.3nmとした場
合、(B)は同じくドライ酸化を80分間、その後ウエ
ット酸化を1分間行い、膜厚を26.3nmとした場
合、(C)はドライ酸化を20分間、ウエット酸化を1
5分間、膜厚は24.0nmとした場合、(D)はドラ
イ酸化を5分間、ウエット酸化を18分間行い、膜厚を
22.9nmとした場合、(E)はウエット酸化のみで
20分間行い、膜厚を23.3nmに形成した場合をそ
れぞれ示している。
Further, this result is shown by a histogram in FIG. In the figure, (A) shows a dry oxidation of 85.
When the thickness of the gate oxide film is set to 25.3 nm, the dry oxidation of (B) is performed for 80 minutes, and the wet oxidation is performed for 1 minute, and the film thickness is set to 26.3 nm. Dry oxidation for 20 minutes, wet oxidation 1
When the film thickness is 5 minutes and the film thickness is 24.0 nm, (D) performs the dry oxidation for 5 minutes and the wet oxidation for 18 minutes. When the film thickness is 22.9 nm, (E) is the wet oxidation for 20 minutes. This shows the case where the film is formed to a film thickness of 23.3 nm.

【0010】図2は一実施例に係るゲート酸化膜の酸化
方法と絶縁破壊電界との関係を示すグラフである。この
図にあって、横軸はドライ酸化とウエット酸化の組合せ
時間(分)を変更した場合の酸化方法を、縦軸は絶縁破
壊電界を、それぞれ示している。D60W5とは、ドラ
イ酸化を60分間行った後、ウエット酸化を5分間施し
た場合を意味している。したがって、D85とはドライ
酸化85分のみによる結果を、W24とはウエット酸化
を24分行った場合のみの結果を、それぞれ示すもので
ある。グラフにて○は実験結果の測定値の平均値を示し
ている。
FIG. 2 is a graph showing the relationship between the method of oxidizing the gate oxide film and the dielectric breakdown electric field according to one embodiment. In this figure, the horizontal axis shows the oxidation method when the combined time (minutes) of dry oxidation and wet oxidation is changed, and the vertical axis shows the dielectric breakdown electric field. D60W5 means a case where dry oxidation is performed for 60 minutes and then wet oxidation is performed for 5 minutes. Therefore, D85 shows the result only after 85 minutes of dry oxidation, and W24 shows the result only after 24 minutes of wet oxidation. In the graph, ○ indicates the average value of the measured values of the experimental results.

【0011】以上の結果、ドライ酸化に続いてウエット
酸化を行うことにより、当該ゲート酸化膜の絶縁破壊電
界を高めることができる。
As a result of the above, by performing the wet oxidation subsequent to the dry oxidation, the dielectric breakdown electric field of the gate oxide film can be increased.

【0012】また、図3は本発明の他の実施例について
図2と同様にその絶縁破壊電界と酸化方法との関係をグ
ラフにて示している。この実施例では実際のデバイスに
良く使用されるポリシリコン電極をゲート電極として使
用し、図3は、上記実施例と同様に、ドライ酸化後ウエ
ット酸化を実施したゲート絶縁膜についての測定の結果
を示している。このグラフからもわかるように絶縁破壊
電界が高められるという効果がより顕著に示されてい
る。
Further, FIG. 3 is a graph showing the relationship between the dielectric breakdown electric field and the oxidation method in another embodiment of the present invention as in FIG. In this embodiment, a polysilicon electrode that is often used in an actual device is used as a gate electrode, and FIG. 3 shows the result of measurement of a gate insulating film which is dry-oxidized and then wet-oxidized as in the above-described embodiment. Shows. As can be seen from this graph, the effect of increasing the dielectric breakdown electric field is more significantly shown.

【0013】[0013]

【発明の効果】以上説明してきたように、本発明に係る
ゲート酸化膜の形成方法にあっては、該ゲート酸化膜の
絶縁破壊耐圧を高めることができ、このゲート酸化膜を
用いた半導体装置の品質を向上させることができ、か
つ、その製造歩留まりを高めることができる。
As described above, in the method of forming a gate oxide film according to the present invention, the breakdown voltage of the gate oxide film can be increased, and a semiconductor device using this gate oxide film can be increased. Can be improved in quality, and the manufacturing yield thereof can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る酸化方法による絶縁破
壊耐圧の分布を示すグラフである。
FIG. 1 is a graph showing a distribution of dielectric breakdown voltage by an oxidation method according to an embodiment of the present invention.

【図2】本発明の一実施例に係る酸化方法と絶縁破壊電
界との関係を示すグラフである。
FIG. 2 is a graph showing a relationship between an oxidation method and a dielectric breakdown electric field according to an example of the present invention.

【図3】本発明の他の実施例に係る酸化方法と絶縁破壊
電界との関係を示すグラフである。
FIG. 3 is a graph showing a relationship between an oxidation method and a dielectric breakdown electric field according to another embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 シリコンウェーハの表面に熱酸化法によ
りゲート酸化膜を形成するゲート酸化膜の形成方法にお
いて、 上記ゲート酸化膜は、乾燥酸素雰囲気による酸化後、水
蒸気を含む雰囲気で酸化することを特徴とするゲート酸
化膜の形成方法。
1. A method for forming a gate oxide film on a surface of a silicon wafer by a thermal oxidation method, wherein the gate oxide film is oxidized in a dry oxygen atmosphere and then oxidized in an atmosphere containing water vapor. A characteristic method of forming a gate oxide film.
JP31980091A 1991-11-07 1991-11-07 Method of forming gate oxide film Withdrawn JPH05129596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31980091A JPH05129596A (en) 1991-11-07 1991-11-07 Method of forming gate oxide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31980091A JPH05129596A (en) 1991-11-07 1991-11-07 Method of forming gate oxide film

Publications (1)

Publication Number Publication Date
JPH05129596A true JPH05129596A (en) 1993-05-25

Family

ID=18114333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31980091A Withdrawn JPH05129596A (en) 1991-11-07 1991-11-07 Method of forming gate oxide film

Country Status (1)

Country Link
JP (1) JPH05129596A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291365B1 (en) 1999-02-10 2001-09-18 Nec Corporation Method for manufacturing thin gate silicon oxide layer
WO2002059980A1 (en) 2001-01-25 2002-08-01 National Institute Of Advanced Industrial Science And Technology Semiconductor device manufacturing method
WO2002101809A1 (en) * 2001-06-11 2002-12-19 Motorola, Inc. Method for forming an oxide layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291365B1 (en) 1999-02-10 2001-09-18 Nec Corporation Method for manufacturing thin gate silicon oxide layer
WO2002059980A1 (en) 2001-01-25 2002-08-01 National Institute Of Advanced Industrial Science And Technology Semiconductor device manufacturing method
WO2002101809A1 (en) * 2001-06-11 2002-12-19 Motorola, Inc. Method for forming an oxide layer

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990204