JPH05129202A - Thin film semiconductor device and its manufacture and silicon film - Google Patents

Abstract

PURPOSE:To improve quality of a silicon film by depositing a silicon film on a substrate whose surface is an insulating substance, by performing thermal treatment for the silicon film at a temperature of about a specific value and by depositing a silicon oxide film by electron cyclotron resonance plasma CVD method (ECR-PECVD method). CONSTITUTION:A silicon thin film 104 which becomes a channel part is deposited by making silane flow. Then, a heat treatment is performed for a substrate to proceed crystallization of the silicon thin film 104 and to increase crystalline grain. Crystallization of the silicon thin film is performed by a thermal treatment at a temperature of about 600 deg.C. Then, immediately after a natural oxide film of a source/drain region 103 and a channel part silicon thin film 105 is removed and a clean silicon surface is exposed, an SiO2 film 108 which becomes a gate insulating film is deposited by an electron cyclotron plasma CVD device (ECR-PECVD device). Thereby, transistor characteristics can be greatly improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device formed on an insulating material such as a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display, a manufacturing method thereof and a silicon film. More specifically, the present invention relates to a method of manufacturing a thin film semiconductor device which is formed by a low temperature process in which the maximum temperature of the manufacturing process is about 600 ° C. or less.

[0002]

2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays, the drive system has been changed from a simple matrix system to an active matrix system, and a large amount of information can be displayed. The active matrix system can be used for a liquid crystal display having more than several hundred thousand pixels, and a switching transistor is formed for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as fused quartz plate or glass that enables a transmissive display is used.

However, in order to enlarge the display screen and reduce the price, it is essential to use inexpensive ordinary glass as an insulating substrate. Therefore, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining the economical efficiency.

Amorphous silicon or polycrystalline silicon is usually used for the channel semiconductor layer of the thin film transistor. However, when the drive circuit is integrated into a thin film transistor, polycrystalline silicon having a high operating speed is used. It is advantageous.

Conventionally, in the case of forming such a thin film transistor, after forming a silicon layer of a channel portion, a substrate of oxygen (O ₂ ) or laughing gas (N ₂ ) is used to form a gate insulating layer.
O), water vapor (H ₂ O), etc., and the temperature is set to a high temperature of about 800 ° C. to 1100 ° C. to oxidize a part of the channel part silicon layer to form a gate insulating layer. The oxidation method was used. On the other hand, various methods have been attempted to manufacture a thin film semiconductor device using polycrystalline silicon at a maximum process temperature of about 600 ° C. or less that can withstand the use of an inexpensive ordinary glass substrate. For example,
The channel part semiconductor layer is formed by the low pressure chemical vapor deposition method (LPCV).
D method), a gate insulating film is formed by an electron cyclotron resonance plasma CVD method (ECR-PECVD method), and then hydrogenation treatment such as hydrogen plasma irradiation is performed. Alternatively, the channel semiconductor layer may be amorphous.
After depositing a silicon thin film, heat treatment is performed at 600 ° C. for about 24 hours, and then atmospheric pressure chemical vapor deposition (APCVD)
Method), a gate insulating film is formed, and hydrogenation treatment is performed. (Japanese J, Appl, P
hys, 30L 84 '91)

[0006]

However, many problems have been pointed out in the above-mentioned conventional methods. First of all, in the formation of a SiO ₂ film by the thermal oxidation method, the heat treatment of at least 800 ° C. or higher accompanies the formation thereof, so that the heat resistance of the thin film layer or the substrate located below the oxide film becomes a problem. For example, when making a switching transistor of a large area liquid crystal display, a substrate such as a fused silica plate, which is very expensive, cannot withstand such a high temperature. Further, even in a three-dimensional LSI device, the lower layer transistor is deteriorated at a high temperature, so that this thermal oxidation method cannot be practically used.

Next, the channel semiconductor layer is formed by the LPCVD method, the gate insulating film is formed by the ECR-PECVD method, and further the hydrogen plasma treatment is performed, the mobility is 4-5 cm ² / V. It is as low as sec, which is still insufficient as a thin film semiconductor device. In addition, due to the hydrogenation process that is performed to improve the characteristics of the thin film semiconductor device, some of the various thin films that make up the thin film semiconductor device are etched and some of the many thin film semiconductor devices are destroyed. I have a problem. In addition, a method of depositing an amorphous silicon thin film on the semiconductor layer of the channel part, then performing heat treatment at about 600 ° C., forming a gate insulating film by the APCVD method, and further performing hydrogenation treatment such as hydrogen plasma irradiation. Has a large interface trap level of about 10 ¹² and exhibits depletion type semiconductor device characteristics, and is still insufficient as a thin film semiconductor device. Further, as in the previous case, the problems associated with the Yahari hydrogenation process remain, and it is not possible to uniformly and stably form a thin film semiconductor device in a large area.

Therefore, there is a demand for a thin film semiconductor device having a high mobility, at the same time having a clean MOS interface and a low interface trap level, and exhibiting no depletion. Moreover, such a thin film semiconductor device is produced. There has been a demand for a manufacturing method that does not require hydrogenation treatment in the process and uniformly and stably produces a good thin film semiconductor device as described above in a large area.

The present invention has been made in view of the above circumstances, and its object is to obtain good semiconductor device characteristics in a low temperature process in which the maximum process temperature is about 600 ° C. or less in a MIS thin film semiconductor device. And a method of manufacturing such a thin film semiconductor device uniformly and stably over a large area.

[0010]

The above object is to form a channel portion silicon film semiconductor layer on one surface of a substrate at least the surface of which is an insulating material, and to form a gate insulating layer and a gate electrode on the semiconductor layer. In the thin film semiconductor device forming the MIS field effect transistor described above, a step of depositing a silicon film forming a channel portion silicon film semiconductor layer and then performing a heat treatment at a temperature of 600 ° C. or lower, and an ECR-PECVD of the gate insulating film. Method including a step of forming by a method, or irradiating oxygen plasma on the amorphous silicon film after forming an amorphous silicon film forming a channel portion silicon film semiconductor layer and before forming a gate insulating layer. And then heat treatment at a temperature of 600 ° C. or lower.

[0011]

EXAMPLES Example 1 Examples of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following examples.

1 (a) to 1 (e) are sectional views showing a manufacturing process of a silicon thin film semiconductor device which constitutes a MIS field effect transistor having a self-unaligned staggered structure according to the first embodiment. ..

In the first embodiment, 2 is used as the base substrate 101.
Although 35 mm square fused silica glass was used, the kind and size of the substrate or base material is not limited as long as it is a substrate or base material that can withstand the maximum process temperature of 600 ° C. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a silicon substrate.
Ceramic substrates such as carbide, alumina, and aluminum nitride can also be used as the base substrate.

First, the base substrate 101 is immersed in an organic solvent such as acetone, methyl-ethyl-ketone, methyl-iso-butyl-ketone, or cyclohexanone, and ultrasonic cleaning is performed. After cleaning, the product is dried in nitrogen or under reduced pressure, ultrasonically cleaned with ethanol, and then rinsed with pure water with nitrogen bubbling. Next, the base substrate 101 was immersed in boiling nitric acid having a concentration of 60% for 5 minutes, and further washed in pure water with nitrogen bubbling. When a material such as a metal that is corroded by acid or deteriorates and is used as a substrate is used, the washing with nitric acid is not required. Further, in the washing with this strong acid, sulfuric acid or the like can be used as the acid in addition to nitric acid.

2000 Å of silicon dioxide film (SiO ₂ film) 102 as a base protection film was deposited on the thus cleaned quartz substrate by atmospheric pressure chemical vapor deposition (APCVD method). The underlying SiO ₂ film 102 is necessary to stabilize the film quality of a silicon thin film to be deposited later and the performance of a thin film transistor using the same when using various substances as described above as a substrate. At the same time, for example, when ordinary glass is used as the substrate 101, mobile ions such as sodium contained in the glass are also generated in the substrate 101.
Also, when various ceramic plates are used, they also play a role of preventing the sintering aid raw material added to the substrate from diffusing into the transistor section. In addition, the metal plate is the substrate 10
When used as 1, the underlying Si layer is used to ensure insulation.
O ₂ is essential. Moreover, in the three-dimensional LSI element,
It corresponds to an interlayer insulating film between transistors and between wirings.
The substrate temperature at the time of depositing the underlying SiO ₂ film 102 is 300 ° C.
84 silane 600 SCCM diluted to 20% with nitrogen
It was deposited by APCVD with 0 SCCM oxygen. At this time, the deposition rate of the SiO ₂ film was 3.9 Å / sec.

Then, a silicon thin film 103 containing impurities serving as a donor or an acceptor was deposited by a low pressure CVD method. In the first embodiment, phosphorus was selected as an impurity for the purpose of producing an n-type transistor.
Group 6 and 6 elements, if P type, boron and other groups 2,
Group 3 elements can be added as impurity elements. The silicon thin film 103 containing the impurities is to be a source / drain region at a site which is to be the source / drain regions.
In addition to the method of adding impurities, first, an intrinsic silicon film containing no impurities is first formed, and then the impurities are diffused and added from the vapor phase or the solid phase in contact with the intrinsic silicon film. Then, there is a method of implanting into the intrinsic silicon film. By using the method of adding impurities by the diffusion method or the ion implantation method after forming the intrinsic silicon film, it becomes possible to add the impurities only to a desired portion of the intrinsic silicon film. A self-aligned transistor whose source end or drain end is self-aligned becomes possible.
By changing the concentration of added impurities in each part, it is possible to change the current density and the specific resistance in the silicon film so that the current can flow only to the desired part.

Since phosphorus is selected as the impurity in the first embodiment, the silicon thin film 103 containing impurities is 1500 Å using a gas in which phosphine (PH ₃ ) and silane are mixed.
Deposited.

In Example 1, 200 SCCM of monosilane, 6 SCCM of helium / phosphine mixed gas of 99.5% of helium and 0.5% of phosphine, and 100 SCCM of helium were placed in a low pressure CVD furnace having a volume of 184.5 l. It was flown and deposited at a deposition temperature of 600 ° C. and a furnace pressure of 100 mtorr. At this time, the deposition rate was 29.6 Å / min, and the sheet resistance immediately after film formation was 2,025 Ω / □.

Next, a resist is formed on the silicon thin film, and the thin film is patterned by using a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form the source / drain regions 103. (FIG. 1 (a)). Subsequently, impurities such as residual resist are removed by washing in boiling nitric acid for 5 minutes, and then immersed in 1.67% hydrofluoric acid for 20 seconds to remove the natural oxide film on the surface of the source / drain region 103.
Immediately, a silicon thin film to be a channel portion was deposited by the low pressure CVD method.

At this time, the volume of the low pressure CVD reactor is 184.
At 5 l, the substrate is placed horizontally near the center of the reactor. The raw material gas and the dilution gas such as helium, nitrogen, argon, hydrogen, etc. are introduced into the furnace from the lower part of the reaction furnace and exhausted from the upper part of the reaction furnace as needed. Outside the reactor made of quartz glass, there are heaters divided into 3 zones,
By adjusting them independently, a soaking zone is formed near the center of the reactor at a desired temperature. This soaking zone spreads at a height of about 350 mm, and the temperature deviation within that range is, for example, 6
When set to 00 ° C, it is within 0.2 ° C. Therefore, if the distance between the inserted substrates is 10 mm, it is possible to process 35 substrates in one batch. In Example 1, 17 substrates were installed in the soaking zone at intervals of 20 mm.

Exhaust was carried out by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reaction furnace was measured by a diaphragm pressure gauge (MKS Co. Baratron Manometer) whose measured value did not depend on the type of gas. 5 reactors
When the temperature was kept at 50 ° C, the gas inlet valve was closed, and both pumps were evacuated, the reactor internal pressure was 0 mtorr.
Therefore, the background vacuum degree is at most about 10 ⁻⁴ torr.

Source / drain regions 103 are formed,
The substrate from which the native oxide film on the surface of the region was removed was immediately inserted into the low pressure CVD furnace with the front side facing downward. The temperature inside the reaction furnace at the time of insertion is maintained at about 395 ° C to 400 ° C. This is to reduce the formation of a natural oxide film on the source / drain regions 103 as much as possible.
It is desirable that the temperature inside the reaction furnace during insertion be as low as possible. For example, it is possible to set the temperature in the reaction furnace at the time of insertion to room temperature, but in this case it takes several hours or more to raise the temperature in the reaction furnace to the deposition temperature, and the number of arrows to return to room temperature after deposition. It takes time. Approximately 4 SL in the reaction furnace when inserting the substrate
Nitrogen of M to 10 SLM is flowed to maintain the inside of the reaction furnace in an inert atmosphere. In addition, about 6 SLM near the entrance of the reactor
A nitrogen curtain is formed with 20 SLM of nitrogen to minimize the flow of air into the reaction furnace when the substrate is inserted.
When moisture and oxygen in the air enter the reaction furnace, they are adsorbed by the Si layer on the inner wall of the reaction furnace or react with Si and remain in the reaction furnace, and are removed during the deposition of the silicon film that becomes the channel part. It appears as a gas and causes deterioration of the film quality of the deposited silicon film.

After inserting the substrate, a vacuum was drawn and a leak test was performed. In the leakage inspection, all the valves leading to the reactor were closed to completely isolate the reactor, and changes in the reactor pressure were examined.
In Example 1, after the reactor was completely isolated at 400 ° C. for 2 minutes, the reactor pressure was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature inside the reaction furnace is raised from the insertion temperature of 400 ° C. to the deposition temperature. In Example 1, since the silicon thin film to be the channel portion was deposited at 550 ° C., it took 1 hour to raise the temperature. It takes about 35 minutes for the temperature in the furnace to reach the deposition temperature of 550 ° C., but in order to sufficiently release the degas from the reaction furnace wall, the temperature rising period of at least 1 hour or more, preferably several hours is desirable. ..
During this temperature rising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995%. These gases can be pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton, and mixed gases of these gases are also possible. In the first embodiment, helium having a purity of 99.9999% or more is used as 350
Continue to flow SCCM, the reactor pressure is 80.7 ± 1.2 mtorr
It was.

After reaching the deposition temperature, a predetermined amount of silane, which is a raw material gas, or a mixed gas of silane and a diluent gas is introduced into the reaction furnace to deposit the silicon thin film 104. As the dilution gas, the same kind of combination as the gas flowed in the previous temperature rising period can be used, but it is desirable that the purity of each gas is 9
9.999% or more is good. In this Example 1, a silicon thin film 104 was deposited by using 100 SCCM of silane having a purity of 99.999% or more without using a diluent gas. At this time, the pressure inside the reaction furnace is adjusted by adjusting the opening / closing degree of the conductance valve installed between the reaction furnace and the mechanical booster pump.
It was maintained at 398.6 ± 1.9 mtorr. In the first embodiment, the silicon thin film 104 serving as the channel portion is 21.2Å / m.
It was deposited to a film thickness of 248 Å at a deposition rate of in (Fig. 1
(B)).

In the first embodiment, the silicon thin film is deposited by LP.
Although the CVD method was used and monosilane was used as the source gas, it is also possible to deposit by plasma CVD method, APCVD method, sputtering method or the like. In addition, the source gas is not limited to monosilane, but higher order silanes such as disilane and trisilane, and dichlorosilane can also be used. Of course, it is also possible to deposit a silicon thin film by a combination of the above various CVD methods and the above various raw materials.

Then, the substrate thus obtained was subjected to heat treatment to promote crystallization of the silicon thin film 104 and increase the number of crystal grains. The heat treatment furnace is a vertical furnace, which is normally kept at 400 ° C and contains 20 SL of nitrogen gas having a purity of 99.999% or more.
The flow of M is continued and the inside of the heat treatment furnace is maintained in an inert atmosphere. The substrate that had reached temperature equilibrium with room temperature was placed in a vertical heat treatment furnace at 400 ° C. for 17 minutes. Keep the temperature at 400 ° C for 30 minutes after insertion, and keep the temperature in the furnace at 400 ° C regardless of the position of the substrate.
After reaching the uniform temperature of ° C, the temperature of the heat treatment furnace is raised to 600 ° C. By keeping the temperature at 400 ° C. for 30 minutes, the same thermal history can be obtained anywhere regardless of the position of the substrate, and the crystallization of the silicon thin film can be performed uniformly. Since 20 SLM of nitrogen continues to flow into the heat treatment furnace and the volume of the heat treatment furnace is about 176 l, this 40
By preheating at 0 ° C., the inside of the heat treatment furnace is completely replaced with a nitrogen atmosphere. The temperature rise from 400 ° C. to 600 ° C. is performed for about 1 hour, and after reaching the temperature equilibrium at 600 ° C., crystallization of the silicon thin film proceeds by heat treatment for 7 hours or more. In Example 1, after reaching 600 ° C., 23
Heat treatment was applied for an hour.

The silicon thin film thus obtained was patterned with a resist and then etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form a channel portion silicon thin film 105. (Fig. 1
(C)) The silicon thin film formed in this Example 1 was subjected to vacuum plasma discharge of 15 Pa with the ratio of CF ₄ and O ₂ being 50 SCCM to 100 SCCM, and the etching was 2.1 Å / sec when the output was 700 W. Had speed.

Next, this substrate was washed with boiling nitric acid having a concentration of 60%, and further washed with a 1.67% hydrofluoric acid aqueous solution.
Immersion for 0 seconds to remove the native oxide film on the source / drain region 103 and the channel portion silicon thin film 105 to expose a clean silicon surface, and immediately thereafter, electron cyclotron resonance plasma CVD device (ECR-PECVD device)
Then, a SiO ₂ film 106 to be a gate insulating film was deposited.
(FIG. 1D) ECR-PECVD used in this Example 1.
The outline of the apparatus is shown in FIG. At the time of depositing the gate insulating film, a microwave of 2.45 GHZ is introduced into the reaction chamber 202 through the waveguide 201, and 100 SCCM of oxygen introduced from the gas introduction pipe 203 is first turned into plasma. At this time,
The microwave output is 2250 W, and the external coil 204 installed outside the reaction chamber 202 allows the reaction chamber 202 to
By applying a magnetic field of 875 Gauss to the oxygen plasma inside, the electrons in the plasma satisfy the ECR condition. This oxygen plasma is drawn out of the reaction chamber by the divergent magnetic field, and the substrate 205 placed perpendicular to the plasma is removed.
Irradiate for 0 seconds. A heater 206 is provided on the back surface of the substrate 205.
And the entire substrate was kept at 100 ° C. At this time, the pressure in the reaction chamber was 1.85 mtorr. Immediately after the oxygen plasma outlet, another gas introduction pipe 207 is provided. After the oxygen plasma is sufficiently stabilized for 10 seconds, the silane 60 SCCM having a purity of 99.999% or more is supplied from the gas introduction pipe 207 to the oxygen plasma. Mix in. The substrate thus obtained is irradiated with the oxygen-silane mixed plasma thus obtained for 30 seconds so that the SiO ₂ film 106 serving as a gate insulating layer is formed into 150
0Å was deposited (Fig. 1 (d)). At this time, the pressure in the reaction chamber was 2.35 mtorr.

Next, chromium was deposited by a sputtering method to a thickness of 1500 Å, and the gate electrode 107 was formed by patterning. At this time, the sheet resistance value is 1.356 ± 0.047Ω /
It was □. Although chromium is used as the gate electrode material in the first embodiment, it is needless to say that other conductive materials can be used, and the forming method is not limited to the sputtering method, and the vapor deposition method or C
The VD method or the like is also possible. Subsequently, an SiO ₂ film to be the interlayer insulating film 108 was deposited by 5000 Å by the APCVD method. This deposition was performed under exactly the same conditions as the deposition of the underlying SiO ₂ film 102 in Example 1, but was changed only at the deposition time. After forming the interlayer insulating film, contact holes are opened, and source / drain extraction electrodes 109 are formed by a sputtering method or the like to complete the transistor (FIG. 1E). In Example 1, aluminum was used as a source / drain extraction electrode material and deposited to a film thickness of 8000 Å by a sputtering method to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film is 42.48 ± 2.0.
It was 2 mΩ / □.

An example of the characteristics of the thin film transistor (TFT) prototyped in this way is shown in FIG. 3 as Vgs-Ids curve.
-A. Here, the source-drain current Ids was measured at a source-drain voltage Vds = 4V and a temperature of 25 ° C. Transistor size is channel length L = 1
The width was 0 μm and the width W was 10 μm. Vds = 4V, Vg
The on-current when the transistor was turned on at s = 10V was 235 mm □ on the center of the substrate and five square transistors were measured, and ION = 4.65 ± 0.39 μA. A thin film semiconductor with good transistor characteristics. The device is obtained.
In addition, the field effect transfer μo and the trap density Nt (J. Levinson et.
al. J. Appl. Phys 53 . 1193.1
982) is μo = 25.85 ± 0.96 cm ² /
v. sec, Nt = (6.81 ± 0.15) × 10 ¹¹ 1
It was / cm ² . For comparison, 3-b in FIG. 3 shows the transistor characteristics of a thin film semiconductor device manufactured according to an example of the related art. That is, a thin film semiconductor device was manufactured by the same steps as those of the present invention of Example 1 except that a channel silicon thin film was deposited at 600 ° C. by a low pressure CVD method and no heat treatment was performed for 24 hours. .. At this time, low pressure CVD
The apparatus for depositing the silicon thin film in the channel portion by the method is the same as the apparatus used in the present invention of the first embodiment, the source gas monosilane is made to flow at 12.5 SCCM, and the pressure in the reaction furnace is 9.0 m.
torr, deposition rate is 11.75Å / min and 256Å
Deposited to a film thickness of. The on-current of the TFT of this prior art example is Ids = 0.91 ± 0.12 μA and the field-effect mobility is μo = 4.75 ± 0.20 cm ² / v. sec, trap density Nt = (5.18 ± 0.13) × 10 ¹¹ 1 / cm ² . In addition to this, the silicon thin film in the channel part is similarly subjected to the low pressure CVD method at 600 ° C. and the monosilane flow rate is 12.5 SCCM.
And the gate insulating film is deposited in the same step as the present invention of the first embodiment, and then hydrogen plasma treatment is performed by an ECR-PECVD apparatus. Otherwise, the same step as the present invention of the first embodiment. A thin film semiconductor device was created. This is also an example of a conventional technique for performing hydrotreatment. The hydrogenation process is performed by depositing the gate insulating film with the ECR-PECVD apparatus shown in FIG.
The substrate 205 is evacuated and further heated by the heater 206.
The temperature was raised to 300 ° C. over 1 hour and the temperature was raised.
125 SCCM of hydrogen gas having a purity of 99.9999% or more was introduced into the reaction chamber 202 through the gas introduction pipe 203 to establish hydrogen plasma. The microwave power was 2000 W and the pressure in the reaction chamber was 2.63 mtorr. Hydrogen plasma irradiation was performed for 30 minutes. The T of the thin film semiconductor device thus created
When the FT characteristic was measured, the on-current Ids = 0.96 ±
0.13 μA, electric field effect mobility μo = 4.68 ± 0.2
2 cm ² / v. sec, capture density Nt = (5.12 ± 0.
13) × 10 ¹¹ 1 / cm ² . That is, the silicon film in the channel portion is formed with or without hydrogen plasma treatment.
Compared to the conventional technique of depositing by low pressure CVD at 0 ° C.,
The present invention brings about a great improvement in transistor characteristics, for example, by increasing the field effect mobility to about 5 times.

Next, another example of the prior art will be compared with the present invention. That is, as another example of the prior art, the formation of the channel portion silicon thin film is performed in the same manner as in the present invention of the first embodiment, but the conventional technique of depositing the gate insulating film by the APCVD method and the gate insulating film by the APCVD method. Later, we see a great advantage of the present invention over the prior art of performing hydrogen plasma treatment. The conventional gate insulating film is APCV
In the step of depositing the thin film semiconductor device by the D method, the thin film semiconductor device was produced by the same process as that of the present invention of the first embodiment except that the gate insulating film was deposited to 1500 Å by the APCVD method. In the APCVD method, the substrate temperature is kept at 300 ° C., nitrogen containing 20% silane in nitrogen, silane mixed gas of 300 SCCM, and oxygen of 420 SCCM are flowed, and about 140 SL.
Nitrogen for dilution of M is caused to flow along with these source gases to form SiO.
_Two films were deposited. The deposition rate was 1.85Å / sec. The transistor characteristics of the thin film semiconductor device according to the conventional technique thus produced are shown in 3-C of FIG. The on-current of this transistor is ION = 1.49 ± 0.05μ
A, electric field effect mobility μo = 24.60 ± 0.72 cm ² /
v · sec, capture density Nt = (9.20 ± 0.15) ×
It was 10 ¹¹ 1 / cm ² . Comparing the present invention with this prior art, it becomes clear that the present invention has produced a very good thin film semiconductor device in which the trap level is significantly reduced and which rises sharply near the gate voltage Ov. In the conventional technique of depositing the gate insulating film by the APCVD method, the mobility can be increased as much as the present invention, but in fact, the minimum value of the source / drain current is around -11v and the trap density is high, so The inclination of was not so practical as a thin film semiconductor device. On the other hand, an example of another conventional technique is shown in FIG.
Shown in d. Here, the formation of the channel portion silicon thin film is performed in the same manner as in the present invention of the first embodiment, but the gate insulating film is deposited by the APCVD method, and then hydrogen plasma treatment is performed. Example 1 except that a gate insulating film was deposited under the same conditions as described above, and immediately thereafter, hydrogen plasma irradiation was performed under the same conditions as described above using an ECR-PECVD apparatus.
A thin film semiconductor device was manufactured through the same steps as those of the present invention. The characteristics of the TFT thus obtained are shown in 3-d of FIG. On-state current is Ids = 2.91 ± 0.30 μA, field-effect mobility μo = 24.51 ± 0.67 cm ² / v · s
ec, capture density Nt = (7.94 ± 0.15) × 10 ¹¹
It was 1 / cm ² . It can be seen that the present invention exhibits excellent characteristics in all parameters even when compared with the conventional technique using this plasma treatment. Further, in the transistor manufactured by the conventional technique which has been subjected to the hydrogen plasma treatment, one of the measured five transistors has a threshold voltage Vth of about + 2V.
The values of this transistor are not included in the average value and standard deviation value of each parameter described above. That is, the conventional technique using the hydrogen plasma treatment improves the transistor characteristics as compared with the conventional technique in which the hydrogen plasma treatment is not performed, but it has been difficult to form a uniform transistor in a large area. In addition, samples subjected to hydrogen plasma treatment have large lot-to-lot variations, making stable production difficult. In particular, the deviation of the threshold voltage and the fluctuation of the gate voltage value that minimizes the source / drain current are extremely large between lots. On the other hand, according to the present invention, it can be seen that the excellent hydrogenation process can be uniformly formed on a large area by eliminating the hydrogenation process that causes the variation.

(Embodiment 2) The same steps as those of the present invention of Embodiment 1 are carried out except that the deposition time of the silicon thin film (FIG. 1.104) to be the channel portion is changed to change the deposited film thickness of the silicon thin film 104. Accordingly, a thin film semiconductor device was created. Example 2
Then the silicon thin film 104 is 190Å, 280Å, 515
Thin film semiconductor devices were prepared with 6 different film thicknesses, Å, 1000 Å, 1100 Å, and 1645 Å. FIG. 4 shows the result of the ratio of the on-current and the off-current of the thin film semiconductor device thus obtained plotted against the film thickness of the channel portion silicon film. As can be seen from this figure, in the thin film semiconductor device in which the film thickness of the silicon film semiconductor layer of the channel portion is 500 Å or less, the on / off ratio was drastically improved and good characteristics of 7 digits or more were obtained.

(Embodiment 3) A thin film semiconductor device (off-set type thin film semiconductor device) having a structure in which at least one of a source region and a drain region does not overlap with a gate electrode via a gate insulating film is implemented. It was prepared by the same manufacturing method as in the present invention of Example 1. Example 3
Then, the staggered thin film semiconductor device shown in FIG. 5A was created as an off-set thin film semiconductor device by performing alignment with high accuracy. Things are also possible. For example, as shown in FIG. 5B, a method of forming source / drain regions 503 by implanting impurity ions in an intrinsic silicon thin film using the gate electrode 504 as a mask, and FIG.
It is also possible to use an inverted staggered type thin film semiconductor device having the gate electrode 505 shown in (c) on the lower side and forming the source / drain regions 507 by using the mask material 506.

In the third embodiment, the diameter of the base substrate is 75 mm.
An off-set type thin film semiconductor device was produced by the same manufacturing method as that of the present invention of Example 1 except that the fused silica glass of Example 1 was used.
That is, the substrate is first cleaned and the underlying SiO ₂ film is removed by APCV.
After depositing by the D method or the like, the silicon film to which phosphorus is added is
The source / drain regions 501 were formed by depositing by the PCVD method and further patterning. Here, the distance between the source and drain regions, which becomes the channel length L later, is 10.
It was 5 μm. Next, in the same manner as in the present invention of Example 1, a silicon thin film to be a channel portion was deposited at a deposition rate of 21.2Å / min to a film thickness of 248Å. However, Example 1
In the present invention, the substrate was inserted into the reaction furnace with the front side of the substrate facing downward, but in the third embodiment, a substrate having a diameter of 75 mm was placed on the 235 mm square dummy quartz plate with the front side facing upward, and was inserted into the reaction furnace. Then, heat treatment was performed by the same manufacturing method as that of the present invention in Example 1, a gate insulating layer was deposited, and a gate electrode 502 was further formed. The width of this gate electrode 502 is 1
High precision alignment was performed so that the center of the source-drain distance of 10.5 μm and the center of the gate electrode width of 10.0 μm were aligned at 0.0 μm. As a result, the distance (offset distance) between the gate electrode end position and the source region end in the channel region is 0.25 μm.
After that, an interlayer insulating film was deposited by the same manufacturing method as that of the present invention in Example 1, and after forming contact holes, wiring was performed using aluminum, and a thin film semiconductor device was completed.

An example of the transistor characteristics of the thin film semiconductor device thus prepared is shown in FIG.
shown in a. Reference numeral 3-a in FIG. 6 shows the transistor characteristics of the self-unaligned staggered structure thin film semiconductor device manufactured by the present invention as the first embodiment. As can be clearly seen from the figure, in the present invention of the third embodiment, it is possible to greatly reduce the leak current generated when the gate voltage is negative. In fact, in the present invention of the third embodiment, the source / drain current is suppressed to about 0.1 pA when the gate voltage is −2.5 V or less. 6-b of FIG. 6 shows, for comparison, transistor characteristics obtained when an offset type thin film semiconductor device is manufactured according to the conventional technique of the first embodiment. That is, the channel portion silicon thin film is deposited by the low pressure CVD method at 600 ° C., the center of the source-drain distance of 10.5 μm and the gate electrode width 10.
This is a transistor characteristic obtained when the center of 0 μm is aligned with high precision alignment to produce an offset type thin film semiconductor device. Therefore, 6-b of FIG. 6 can be directly compared with the transistor characteristic diagram 3-b of the prior art self-unaligned staggered thin film semiconductor device. Even in the off-set type thin film semiconductor device according to the conventional technique, it is possible to keep the leak current as low as about 0.1 pA or less, but when the offset type thin film semiconductor device is produced by the conventional technique, the on-current and the movement are reduced. However, the positive characteristics of the transistor, such as frequency, have also deteriorated and it has been put out of practical use. For example, the on-current of the offset type thin film semiconductor device according to the related art is Ids = 0.
The on-current is 090 ± 0.01 μA, which is one digit or more lower than that of the self-unaligned thin film semiconductor device. In addition, the mobility at this time is also degraded by about 30% similarly to μo = 3.33 ± 0.15 cm ² / v · sec. For this reason, the manufacturing of offset type thin film semiconductor devices according to the prior art was not worth it. On the other hand, the present invention of the third embodiment is 6 in FIG.
As indicated by −a, the leak current is kept low and the on-current is also kept high. In the present invention of the third embodiment, Ids = 3.71 ± 0.43 μA is obtained as the on-current, which is almost comparable to the on-current of the self-unmatched thin film semiconductor device. Further, in the present invention of Example 3, the mobility also shows a good value of μo = 22.00 ± 0.95 cm ² / v · sec.

(Embodiment 4) In Embodiment 3, an offset type thin film semiconductor device was produced by performing high precision alignment. Of course, the present invention is effective other than this. Figure 5
In (b), an offset type thin film semiconductor device was prepared by depositing an intrinsic silicon film, patterning the gate electrode, and then adding impurity ions. This method will be described in detail.

FIGS. 7A to 7D are sectional views showing the structural steps of the silicon thin film semiconductor device which constitutes the MIS field effect transistor of the offset staggered structure according to the fourth embodiment. First, a substrate 701 similar to that of the first embodiment
After cleaning the SiO ₂ film, a SiO ₂ film is used as a base protective film 702.
Accumulate about 000Å. Then, the first silicon film is applied to 30
A silicon film 703 to be a pad is formed by depositing about 0Å or more and patterning. In this embodiment, as the first silicon film, the LPCVD apparatus in which the channel portion silicon film is deposited in Embodiment 1 is used and the deposition temperature is 600 ° C.
The silane flow rate was 12.5 SCCM and the deposition was carried out at 1250 Å.
The silicon film may be deposited at about ℃, disilane (Si ₂ H ₆ ) may be used as a source gas at a deposition temperature of about 450 ℃, or the silicon film may be deposited by PECVD at about 250 ℃. It is possible. Any method may be used as long as the film forming temperature does not exceed the process maximum temperature of 600 ° C. Next, a second silicon film 704 is deposited. The thickness of the second silicon film is about 300 Å or more, and the resistance value of the source / drain region after the impurity implantation is in the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 703 to be the pad is not required. In the fourth embodiment, the second silicon film 704 is deposited by the same method as that of the silicon thin film which becomes the channel portion in the present invention of the first embodiment. That is L
The deposition temperature is 5 by using monosilane as a source gas by the PCVD method.
50 ℃, Silane flow rate 100SCCM Deposition rate 21.2Å / m
It was deposited to a film thickness of 250Å in. However, as with the first silicon film, the second silicon film forming method may be any method as long as the film forming temperature does not exceed the process maximum temperature of 600 ° C. For example, the second silicon film may be deposited at a deposition temperature of 600 ° C., a silane flow rate of 12.5 SCCM, and a reactor pressure of 9.0 mtorr, or a high-order silane such as disilane or trisilane may be used as a source gas. It is also possible to form a film at a lower temperature. In this way, the second silicon film 704 was formed by some method (FIG. 7B), and after patterning, the gate insulating layer 705 was formed by the same method as in the present invention of Example 1. That is, ECR-PEC
An SiO ₂ film was deposited by the VD method at 1500 Å. As a method for forming the gate insulating layer 705, when the second silicon film 704 is a polycrystalline silicon film, it can be formed by the APCVD method. Next, a metal film or the like to be the gate electrode is formed. In Example 4, a silicon film to which phosphorus was added at a high concentration was used as a gate electrode material. Here, a deposition temperature of 600 ° C., monosilane of 200 SCCM, helium of 99.5% and phosphine of 0.5% helium / phosphine mixed gas of 6 SCCM and helium of 100 SCCM are flown by the LPCVD method.
At a furnace pressure of 100 mtorr, a film having a thickness of 3000 Å was deposited.
The sheet resistance value immediately after film formation was 744 Ω / □. Subsequently, a resist was applied, the resist was patterned, and then the phosphorus-added silicon film was patterned by a mixed plasma of CF ₄ and O ₂ . Patterning was performed at an incident wave output of 700 W with CF ₄ and O ₂ ratios of 200 SCCM and 200 SCCM, respectively. At this time, the phosphorus-added silicon film was etched at a rate of 15.4 Å / sec for 5 minutes 57 seconds to form a gate electrode 706. Since the film thickness of the phosphorus-added silicon film was 3000 Å, the width of the gate electrode was narrowed by 2,500 Å in each of the left and right sides as compared with the resist 707 by this plasma etching (FIG. 7).
(C)). Next, impurity ions are added while the resist 707 used for forming the gate electrode 706 is left without being peeled off. In the fourth embodiment, phosphorus was selected as an impurity to aim at an n-type thin film semiconductor device, but other elements can of course be used according to the purpose. In the present Example 4, impurity ion addition was performed using an ion implanter without a mass spectrometer. Phosphine with a concentration of 5% diluted in hydrogen was used as a source gas, and 3 × 10 ¹⁵ 1 / cm 2 at an acceleration voltage of 110 kV.
Driven to a concentration of ² . In this manner, the first silicon film and a part of the second silicon film are partially removed from the source / drain region 7.
08, and the resist 707 used for forming the gate electrode
Has a film thickness of about 2 μm, the second silicon film located thereunder is not ion-added and the channel portion 7
09 (Fig. 7 (c)). Further, according to this method, an offset type thin film semiconductor device is produced. Next, after removing the resist 707 for forming the gate electrode, the substrate is subjected to heat treatment at 600 ° C. for 7 hours or more to activate the additive impurity ions and crystallize when the crystallinity of the channel portion silicon film 709 is insufficient. Promote the transformation. In this Example 4, heat treatment was performed for 23 hours at 600 ° C. in a nitrogen atmosphere, similar to the heat treatment performed in the present invention in Example 1. Then, SiO ₂ 710 is deposited as an interlayer insulating film by an APCVD method or the like to 500
Hydrogen was accumulated at 0 Å and ion-implantation equipment without mass spectrometer was used to accelerate hydrogen at 5 × 10 ¹⁵ at an accelerating voltage of 80 kV.
After driving in 1 / cm ² , open a contact hole,
The wiring 711 is formed of aluminum or the like, and the offset type thin film semiconductor device is completed.

When the transistor characteristics of the offset type thin film semiconductor device thus produced were measured, L = W = 10 μ
m, Vds = 4V, ON current is 3.4 μA, and minimum source / drain current is 0.09 when Vgs = −3.5V.
The off current defined by pA and Vgs = -10V is 0.2.
The leakage current at the time of turning off the transistor was 8 pA, which was low, and a good on-current could be obtained.

As described in the third and fourth embodiments, after the source region / drain region is formed in the offset type thin film semiconductor device, a heat treatment is applied to obtain a thin film semiconductor device having a high on-current and a small leak current. Although it can be produced, the present invention is by no means limited to the method of manufacturing the offset type thin film semiconductor device described in detail in the third and fourth embodiments. For example, in Example 4, as a method of forming the offset thin film semiconductor device, a resist having a width wider than the width of the gate electrode was used as the implantation mask, but there are various other methods. For example, an offset thin film semiconductor device can be produced by using a metal as a gate electrode, oxidizing the surface and side surfaces of the gate electrode to narrow the gate electrode, and then implanting impurity ions. Further, as shown in FIG. 5C, even in the inverted staggered structure, the width of the mask material 506 is set to the width of the gate electrode 50.
An offset type thin film semiconductor device can be obtained by expanding the width from 5 or more. The present invention is effective for offset type thin film semiconductor devices produced by any of these manufacturing methods.

(Embodiment 5) FIGS. 8A to 8F are MISs.
FIG. 3 is a cross-sectional view showing a manufacturing process of a silicon thin film semiconductor device for forming a field effect transistor.

In the fifth embodiment, two insulating substrates 801 are used.
35 mm square quartz glass was used, but of course the type and size are not limited as long as it is a substrate or base material that can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer is also possible as the base substrate. First, a quartz glass substrate 801 that has been subjected to organic cleaning and acid cleaning
A base SiO ₂ film 802 is formed on the upper surface by atmospheric pressure chemical vapor deposition (A
PCVD method). The base SiO ₂ film 802 is formed by a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, and oxygen of 84.
It was deposited at 0 SCCM and about 140 SLM nitrogen. At this time, the deposition rate was 3.9 Å / sec, and the deposition time was 8 minutes 33 seconds. Then, a silicon thin film 803 containing impurities serving as a donor or an acceptor is formed by a low pressure chemical vapor deposition method (LPCV).
It was deposited by the D method) (FIG. 8A). In the fifth embodiment, phosphorus is selected as an impurity, and phosphine (PH ₃ ) 0.0
3 SCCM and 200 SCCM of silane (SiH ₄ ) were used as source gases, and 1500 Å was deposited at a deposition temperature of 600 ° C. At this time, the deposition rate was 30Å / min, and the sheet resistance immediately after film formation was 1
It was 951Ω / □. Next, a resist is formed on the silicon thin film 803, and patterning is performed with a mixed plasma of carbon tetrafluoride (CF ₄ ), oxygen (O ₂ ), nitrogen (N ₂ ) and the like to form source / drain regions 804. .. Then, after removing the dirt and natural oxide film on the surface of the region 804, the amorphous silicon thin film 805 is immediately depressurized C
It was deposited by the VD method. (FIG. 8 (b)) The low pressure CVD apparatus in the fifth embodiment is 184.5 l, and the reaction chamber is made of quartz glass. A heater divided into three zones is installed outside the reaction chamber, and by adjusting these three heaters independently, an isothermal region at a desired temperature is formed near the central portion of the reaction chamber. The substrate was placed horizontally within this isothermal region and an amorphous silicon thin film 805 was deposited. The amorphous silicon thin film 805 used disilane (Si ₂ H ₆ ) 100 SCCM as a source gas and helium (He) 100 SCCM as a diluent gas. The deposition temperature was 450 ° C. The exhaust of the low pressure CVD furnace used for depositing the amorphous silicon thin film 805 of the fifth embodiment is performed by directly connecting a mechanical booster pump and a rotary pump. Mechanical booster
A conductance valve is installed between the pump and the reaction furnace, and the pressure inside the reaction chamber can be adjusted and maintained at a desired value by adjusting the opening / closing amount of this valve. In Example 5, while depositing the amorphous silicon thin film 805,
The pressure in the reaction chamber was kept at 306 mtorr. Deposition rate is 1
An amorphous silicon thin film 805 was deposited to a film thickness of 307Å at 8.07Å / min. Next, a resist is formed on the thus formed amorphous silicon thin film 805, and patterning is performed with a mixed plasma of carbon tetrafluoride, oxygen, nitrogen, etc., and a strong amorphous silicon thin film is formed at a position which will eventually become a channel portion. Leaving 806.

Next, this substrate is boiled at a concentration of 60%.
The substrate is washed with nitric acid as described above and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film on the source / drain region 804 and the amorphous silicon thin film 806 left at a position where it will become a channel part. Immediately after the appearance of a clean silicon film, oxygen plasma 807 was irradiated by an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). (FIG. 8 (c)) The outline of the ECR-PECVD apparatus used in this Example 5 is shown in FIG. Oxygen plasma uses microwave of 2.45 GHz between waveguides 20
1 was introduced into the reaction chamber 202, and 100 SCCM of oxygen was introduced from the gas introduction pipe 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.84 mtorr, and the microwave output was 2500 W. An external coil 204 is provided outside the reaction chamber, and the oxygen plasma is 875 Ga.
By applying a magnetic field of uss, the electrons in the plasma satisfy the ECR condition. The substrate 205 is placed perpendicular to the plasma, and the heater 206 keeps the substrate temperature at 300 ° C. Under this condition, the oxygen plasma 807 was irradiated for 8 minutes and 20 seconds to oxidize the amorphous silicon thin film 806 left at the position where the channel portion will eventually be obtained, and the SiO ₂ film 808 which will be a part of the gate insulating layer was obtained. .. At this time, the amorphous silicon thin film 809, which will eventually become the channel portion, remains below the SiO ₂ film 808, which is a part of the gate insulating layer. (Fig. 8
(D)) Si that becomes a gate insulating layer continuously without breaking the vacuum.
An O ₂ film 810 was deposited. This SiO ₂ film 810 was deposited for 18.75 seconds at a microwave output of 2250 W, a silane flow rate of 60 SCCM, an oxygen flow rate of 100 SCCM, and a substrate temperature of 300 ° C. The pressure in the reaction chamber during the deposition was 2.62 mtorr. The multi-layer film thus formed is subjected to multi-wavelength dispersion ellipsometry (multi-wavelength spectroscopic ellipsometry: MOS of Sopra Co.).
S-ES4G), and the remaining film thickness of the amorphous silicon film 809 which will eventually become the channel part,
SiO ₂ formed by oxidizing an amorphous silicon film
When the film thickness of the film 808 and the film thickness of the SiO ₂ film 810 deposited by the ECR-PECVD method were measured, the result was amorphous.
Silicon thin film 809 is 205Å, SiO ₂ film 808 is 1
20Å, SiO ₂ film 810 was 1500Å. At this time, the refractive index of the SiO ₂ film at a wavelength of 632.8 nm was 1.42 for the SiO ₂ film 808 and 1.40 for the SiO ₂ film 810.

Next, the substrate thus obtained was inserted into an electric heating furnace maintained at 600 ° C. and heat-treated for 48 hours.
At this time, nitrogen gas having a purity of 99.999% or more was continuously flowed in the electric heating furnace at 20 l / min to keep an inert atmosphere. By this heat treatment at 600 ° C. in the inert atmosphere, the amorphous silicon thin film remaining in the channel portion is crystallized and converted into the silicon thin film 811 forming the channel portion. (FIG. 8 (e)) Then, this substrate is again E
The substrate was placed in a CR-PECVD apparatus, and the substrate heat-treated using the apparatus was irradiated with hydrogen plasma. At this time, the substrate temperature is 300 ° C., the microwave output is 2000 W, and hydrogen is 1
Hydrogen plasma was established by flowing 00 SCCM. In this state, the pressure inside the reaction chamber was 1.97 mtorr. Hydrogen plasma irradiation was performed for 45 minutes.

Next, chromium was deposited by a sputtering method at 1500 Å, and a gate electrode 812 was formed by patterning. At this time, the sheet resistance value was 1.36 Ω / □. After that, a contact hole is formed in the gate insulating film, a source / drain extraction electrode 813 is formed by a sputtering method or the like, and patterning is performed, whereby the transistor is completed. (FIG. 8 (f)) In the fifth embodiment, aluminum having a film thickness of 8000Å was used as the source / drain extraction electrode material. The sheet resistance of aluminum at this time is 42
It was mΩ / □.

An example of the characteristics of the thin film transistor (TFT) prototyped in this way is shown by the Vgs-Ids curve in FIG.
-A. Where Ids is the source-drain voltage,
It was measured at Vds = 4V and a temperature of 25 ° C. Transistor
The size of the channel part is L = 10 μm, width W = 10
It was 0 μm. The on-current when the transistor is turned on at Vds = 4V and Vgs = 10V is Ids = 34.5.
A thin film semiconductor device having good transistor characteristics of μA was obtained. Further, the field effect mobility obtained from the saturation current region of this transistor was 12.52 cm ² / v · sec. For comparison, 9-b of FIG. 9 shows the transistor characteristics of the thin film semiconductor device manufactured by the conventional technique. That is, in the prior art, a thin film semiconductor device was produced in all the same steps as in Example 5 except that the channel portion silicon thin film was deposited at 600 ° C. by the low pressure CVD method and the oxygen plasma irradiation was not performed. .. At this time, the apparatus for depositing the channel silicon thin film by the low pressure CVD method is the same as the apparatus for depositing the amorphous silicon thin film in the fifth embodiment, the raw material gas monosilane is made to flow at 24 SCCM, and the pressure in the reaction furnace is 13.8 mtorr. , Deposition rate is 19.00 Å / min
Deposited to a film thickness of 252Å. The on current of this conventional TFT is Ids = 4.6 μA and the field effect mobility is 4.40.
It was cm / v · sec. In addition to this, after the channel portion silicon thin film is similarly deposited at 600 ° C. by the low pressure CVD method, oxygen plasma irradiation is performed before the gate insulating film deposition, and all other steps are the same as those in the fifth embodiment. When a thin film semiconductor device was prepared with, and the TFT characteristics were measured, the TFT characteristics hardly changed with and without the oxygen plasma irradiation, and the Vgs-Ids curve of the TFT subjected to the oxygen plasma irradiation is shown in FIG.
9-b. At this time, the ON current of the TFT is Ids
= 4.7 μA, field effect mobility is 4.44 cm ² / v
It was sec. That is, the channel silicon thin film is
The effect of oxygen plasma irradiation is very small in the conventional technique of depositing by low pressure CVD at 00 ° C. 9-c of FIG. 9 shows a TFT of a thin film semiconductor device manufactured by another conventional technique.
The characteristics are illustrated. In this conventional technique, a thin film semiconductor device is manufactured by the same steps as those in the present embodiment except that the oxygen plasma irradiation is not performed in the fifth embodiment. That is, although an amorphous silicon thin film is first deposited as a channel silicon layer and then a heat treatment at 600 ° C. is performed,
This is a step in which oxygen plasma irradiation was not performed before forming the gate insulating layer. The TFT produced by this conventional technique exhibits a depletion of -10 V and the rising characteristics are not good. The on-current of this thin film semiconductor device is Vds
= 4 V, Vgs = 10 V, 12.1 μA, and field-effect mobility was 9.94 cm ² / v · sec.

From these results, as shown in the fifth embodiment, only when the amorphous silicon thin film to become the channel part is irradiated with oxygen plasma and then heat treatment is performed to crystallize the channel part silicon thin film, the thin film is formed. It can be seen that the transistor characteristics of the semiconductor device are significantly improved. This is because the surface of the amorphous silicon thin film was first oxidized by oxygen plasma, so that a clean MIS interface was formed and then crystallization proceeded. From this, it is understood that the embodiment of the present invention has remarkably good semiconductor characteristics as compared with the thin film semiconductor device manufactured by the conventional technique.

Example 6 After forming a silicon film and a silicon oxide film on an insulating material, impurities serving as donors or acceptors were added to the silicon film to form a conductive layer based on the silicon film.

In Example 6, a fused silica substrate having a diameter of 75 mm was used as the substrate. However, of course, any substrate may be used as long as it can withstand a heat treatment at about 600 ° C.
For example, a processed silicon substrate or the like is also possible. First, a base SiO ₂ film is formed on the upper surface of the substrate that has been organically and acid-cleaned.
It was deposited by the PCVD method. The formation of the underlying SiO ₂ film is performed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM,
It was deposited with about 140 SLM of nitrogen. The deposition rate at this time is 3.
At 9Å / sec, the deposition time was 12 minutes 49 seconds. Next, a silicon film was deposited in the same manner as in Example 1 by using the LPCVD apparatus used to deposit the channel portion silicon film in Example 1. That is, the deposition temperature was 550 ° C., the silane flow rate was 100 SCCM, and the reaction chamber pressure was 400 mtorr.
A silicon film was deposited for 1 minute and 20 seconds. The thickness of the silicon film thus obtained was 252Å.

Next, the substrate thus obtained was subjected to heat treatment to enhance the crystallinity of the silicon film. This heat treatment method is the same as the heat treatment performed to enhance the crystallinity of the silicon film 104 in the first embodiment. That is, 2 at 600 ° C. in a nitrogen atmosphere
Heat treatment was performed for 3 hours. After the heat treatment was completed, this silicon film was patterned with a resist and further etched by a mixed plasma of CF ₄ and O ₂ to form a wiring pattern of the silicon film.

Subsequently, this substrate was washed with boiling nitric acid having a concentration of 60%, and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film on the silicon film, and a clean silicon surface was exposed. And then ECR-PECVD immediately
A silicon oxide film was deposited with a device to a thickness of 1500Å. Here, the deposition of the silicon oxide film was performed by the same method as the method of forming the gate insulating film in the present invention of Example 1. Next, using an ion implanter, impurities serving as donors or acceptors were added to the wiring formed of the silicon film. In the sixth embodiment, phosphorus was selected as an impurity to form the n-type conductive layer, but other elements can of course be used according to the purpose.
In the sixth embodiment, impurity ions are added by using a bucket type non-separation type ion implanter. Using phosphine having a concentration of 5% diluted in hydrogen as a raw material gas, a phosphine having a concentration of 3 × 10 ¹⁵ 1 / cm ^{2 was} implanted at an accelerating voltage of 110 KV through a silicon oxide film. Next, this substrate was placed in a furnace maintained at 300 ° C. in a nitrogen atmosphere and subjected to heat treatment. The heat treatment time was just one hour. 300 ° C,
After completion of the heat treatment for 1 hour, a contact hole was opened in the silicon oxide film, and an extraction electrode was made of aluminum. When the resistance of the impurity-added silicon film wiring thus formed was measured, the sheet resistance value was (71 ± 15) kΩ / □ with a 95% reliability coefficient. Generally, impurity ions are added to a thin film with a thickness of several hundred Å
It was believed that it was impossible to activate the added ions at a low temperature of about ℃ to obtain a conductive layer. However, in the present invention, the film quality of the heat-treated silicon film is
By covering with a silicon oxide film deposited by the R-PECVD method, and succeeded in improving the quality of the silicon film such as reducing the trap density of the surface of the silicon film, the electron scattering density was lowered,
For the first time, it became possible to create a thin film conductive layer. By comparing this with the silicon film according to the conventional technique, the superiority of the present invention is clarified.

First, after depositing a silicon film at 600 ° C. by the LPCVD method, impurities are added to the silicon film of the prior art on which a silicon oxide film is formed by the ECR-PECVD method, and activation is performed at a low temperature of 300 ° C. An attempt was made to create a silicon film conductive layer. Here, the silicon film is made to flow at 600 ° C., the monosilane is made to flow at 12.50 SCCM, and the pressure in the reaction chamber is set to 9.2 mtor.
Impurity-added silicon film wiring was formed by the same process as in the present invention of Example 6 except that the film was deposited to a film thickness of 263Å by r. The sheet resistance of the silicon film of the prior art obtained in this manner was 1 GΩ / □ or more when measured at 5 points in the substrate, and virtually no current flowed.

Secondly, the silicon film is formed by heat treatment at 600 ° C. in exactly the same manner as in the present invention of the sixth embodiment, and then A
An impurity was added to a conventional silicon film having a silicon oxide film formed by the PCVD method, and an attempt was made to form a silicon film conductive layer by activating at 300 ° C. at a low temperature. Here, the silicon oxide film is APCV
The substrate temperature was kept at 300 ° C by the method D, 300 SCCM of nitrogen / silane mixed gas containing 20% silane in nitrogen and 420 SCCM of oxygen were flowed, and about 140 SLM of diluting nitrogen was flowed together with these source gases, and 1500 Å Deposited to a film thickness.
Except for this, the impurity-added silicon film wiring was formed in the same steps as in the present invention of Example 6 in all cases. The sheet resistance of the conventional silicon film thus obtained was (175 ± 56) kΩ / □ with a 95% reliability coefficient. Then, this substrate was mounted on the ECR-PECVD apparatus again and subjected to hydrogen plasma treatment. Substrate temperature 30 for hydrogen plasma treatment
Flowing hydrogen 125SCCM at 0 ℃, microwave output 2000
W for 30 minutes. After the hydrogen plasma treatment, the resistance value at 5 points in the substrate was measured and the sheet resistance at 2 points was 1 GΩ.
It is above with / □, and the average value of the remaining 3 places is 158 kΩ
The standard deviation value was 68 kΩ / □.

It can be seen that a high-quality silicon film can be obtained by covering the silicon film thus heat-treated at 600 ° C. or lower with the silicon oxide film formed by the ECR-PECVD apparatus. Therefore, as shown in Example 1, the silicon film of the present invention is used for the channel portion of the thin film semiconductor device, and E
When a silicon oxide film formed by a CR-PECVD device is used as a gate insulating layer, a thin film semiconductor device with excellent characteristics can be obtained.
Further, as shown in the sixth embodiment, when impurity ions are added to the silicon film of the present invention, it becomes possible to obtain a silicon film conductive layer having a low resistance at a low temperature. Therefore, the silicon film of the present invention is not only effective for a thin film semiconductor device but also for a charge coupled device (C
It can be used very effectively as a non-single-crystal silicon film used for various electronic devices such as a gate electrode of CD) and wiring.

(Embodiment 7) The step of adding impurity ions to a silicon film by using the bucket type mass non-separation type ion implantation apparatus of the present invention in Example 6 is changed to the mass separation type ion implantation apparatus, and the mass number is changed. An attempt was made to form an impurity-doped silicon film conductive layer in exactly the same steps as in the present invention of Example 6, except that the implantation of monovalent phosphorus ions of 31 was performed. In Example 7, phosphorus ions were implanted at 90 KV at 3 × 10 ¹⁵ 1 / cm ² . When the resistance of the impurity-added silicon film thus obtained was measured, it was found that at all 5 locations in the substrate, it was 1 GΩ / □, and substantially no current flowed. This is because, in the present invention of Example 6, impurities are added by using a mass non-separation type ion implanter and a hydrogen / phosphine mixed gas is used as a source gas, so that hydrogen ions are inevitably added when a phosphorus element is added to a silicon film. Is simultaneously performed, and defects generated at the time of ion addition are repaired by hydrogen ions. Therefore, a low-resistance silicon conductive layer is formed at a low temperature only in the high-quality silicon film of the present invention.

(Embodiment 8) FIGS. 10A to 10D show an M of the self-aligned staggered structure according to the eighth embodiment.
It is the figure which showed the manufacturing process of the silicon thin film semiconductor device which comprises an IS type field effect transistor by the cross section. First, after washing the substrate 1001 as in Example 1, the base protective film 10
As 02, a SiO ₂ film is deposited to about 2000 Å. Then, a first silicon film is deposited on the order of 1500 Å and patterned to form a silicon film 1003 to be a pad (FIG. 10A). In Example 8, as the first silicon film, the LPCVD apparatus in which the channel portion silicon film was deposited in Example 1 was used to deposit 1500 ° C. at a deposition temperature of 600 ° C. and a silane flow rate of 12.5 SCCM. It is possible to deposit a silicon film at a deposition temperature of about 550 ° C. by using an apparatus, or to deposit disilane (Si ₂ H ₆ ) as a source gas at a deposition temperature of about 450 ° C. It is also possible to deposit a silicon film. Any method may be used as long as the film forming temperature does not exceed the process maximum temperature of 600 ° C. Next, a second silicon film 1004 is deposited. The second silicon film has a film thickness of about 300 Å or more, and the resistance value of the source / drain region after the impurity implantation is in the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 1003 to be the pad is not required. In the eighth embodiment, the second silicon film 1004 is deposited by the same method as that of the silicon thin film which becomes the channel portion in the present invention of the first embodiment. That is, LP
The deposition temperature is 55 with monosilane as the source gas by the CVD method.
0 ℃, Silane flow rate 100SCCM Deposition rate 21.2Å / mi
n was deposited to a film thickness of 250Å. After that, the same heat treatment as that performed to enhance the crystallinity of the silicon film in the present invention of Example 1 was performed. That is, 23 at 600 ° C under nitrogen atmosphere
Heat treatment was performed for an hour. (FIG.10 (b)). Next, after patterning the second silicon film, a gate insulating layer 1005 was formed by the same method as in the present invention of Example 1. That is, a 1500 Å SiO ₂ film was deposited by the ECR-PECVD method. Next, a metal film or the like to be the gate electrode is formed.
In Example 8, a chromium film having a thickness of 2000 Å was used as the gate electrode material. Chromium film has a substrate temperature of 18
It was formed by a sputtering method at 0 ° C. The sheet resistance value of chromium immediately after film formation was 994 mΩ / □. Subsequently, by APCVD method, Si is deposited on chromium at a substrate temperature of 300 ° C.
An O ₂ film was deposited at 3000 Å. After that, patterning was performed with a resist to form a protective cap layer 1007 consisting of the gate electrode 1006 and the SiO ₂ film, and impurity ions were added. In Example 8, phosphorus was selected as an impurity to aim at the production of an n-type thin film semiconductor device, but it goes without saying that other elements are possible depending on the purpose. In the present Example 8, impurity ion addition was performed using an ion implanter without a mass spectrometer. 5% concentration diluted in hydrogen as source gas
Phosphine of 5 × 10 ¹⁵ at an acceleration voltage of 110 kV
Implanted to a density of 1 / cm ² . In this way, the first silicon film and a part of the second silicon film become the source / drain regions 1008, and the protective cap layer 1007 made of the SiO ₂ film is present. The film is not ion-added and reaches the channel part 1009 (FIG. 10C). Next, the substrate was heat-treated in a nitrogen atmosphere at 350 ° C. for 2 hours to activate the added impurity ions. Thereafter, a SiO ₂ film 1010 is deposited as an interlayer insulating film at a thickness of 5000 Å, a contact hole is subsequently opened, and wiring 1011 is made of aluminum or the like to complete a self-aligned thin film semiconductor device (FIG. 10).
(D)).

When the transistor characteristics of the self-aligned thin film semiconductor device thus prepared were measured, L = W =
10 μm, Vds = 4 V, Vgs = 10 V, ON current is 4.89 μA, minimum source / drain current is Vgs
= -3.5 V, 0.21 pA, and Vgs = -10 V, the off-current defined is 2.65 pA, and the field effect mobility μo.
= 26.1 cm ² / v · sec, which is a very good self-aligned thin film semiconductor device.

For comparison, the channel silicon film is LP
A self-aligned thin film semiconductor device was manufactured by the same steps as those of the present invention of Example 8 except that the film was manufactured by the CVD method at 600 ° C. However, as described in detail in Example 6, the conventional silicon film does not activate the doped impurity element in the thin film portion, and the resistance of the doped silicon film in the thin film portion is too high. Therefore, the on-current of the transistor is 47. It became unpractical as 0.9 pA. On the other hand, in the present invention of Example 8, the hydrogenated plasma treatment, which is the main cause of the characteristic variation, was eliminated, and a good self-aligned thin film semiconductor device was successfully created because it was difficult in the low temperature process. This is because even if the silicon film semiconductor layer of the channel portion is thinned to 500 Å or less as shown in Embodiment 2 to improve the basic semiconductor characteristics, the thin film conduction according to the present invention of Embodiment 6 is still achieved. This is a result of the formation of the source / drain regions of the thin film portion at low temperature by the formation of the conductive silicon film. That is, activation of impurities serving as donors or acceptors cannot be achieved unless a heat treatment at about 550 ° C. or more is applied to a silicon film having a film thickness of about 1000 Å or more. Therefore, in the self-aligned thin film semiconductor device, the film thickness of the channel portion is necessarily 100.
It was about 0Å or more, and the characteristics were poor. In addition, after the gate insulating layer and the gate electrode are completed, heat treatment at about 550 ° C. or more is performed for the purpose of activating the additive impurity ions, so that the film quality of the gate insulating film deteriorates and hydrogenation treatment is indispensable. There was Further, since it was difficult to use a metal material as the gate electrode, the resistance of the gate line was high, and it was necessary to separately form the gate electrode and the gate line. However, according to the present invention, a metal material can be used as a gate electrode, and at the same time, hydrogen treatment, which is a main cause of variations, can be eliminated, and a thin film semiconductor device with high characteristics can be stably manufactured by a simpler manufacturing method. did.

[0058]

As described above, according to the present invention,
Deposit a silicon film on a substrate whose surface is an insulating material,
After subjecting the silicon film to a heat treatment at about 600 ° C., EC
The film quality of the silicon film can be improved by depositing a silicon oxide film by the R-PECVD method. For example, according to this, in forming a thin film semiconductor device on a substrate whose surface is an insulating material, a step of depositing a channel portion silicon film and then performing a heat treatment at a temperature of 600 ° C. or lower, and a gate insulating film ECR-
A method for manufacturing a thin film semiconductor device including a step of forming by a PECVD method, or after depositing an amorphous silicon film constituting a channel portion silicon film semiconductor layer and before forming a gate insulating layer, oxygen is formed on the amorphous silicon film. Transistor characteristics are drastically improved by a manufacturing method that includes a step of irradiating plasma and then heat treatment at a temperature of 600 ° C. or less, and a thin film semiconductor device having such excellent transistor characteristics can be uniformly formed over a large area. It can be formed by various methods, and has a great effect that multi-layering of LSI and high performance and cost reduction of an active matrix liquid crystal display using a thin film transistor are realized.

[Brief description of drawings]

FIG. 1 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing an outline of an electron cyclotron resonance plasma CVD apparatus used in an example of the present invention.

FIG. 3 is a diagram showing an effect of the present invention.

FIG. 4 is a diagram showing the effect of the present invention.

FIG. 5 is an element sectional view of a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 6 is a diagram showing an effect of the present invention.

FIG. 7 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 8 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 9 is a diagram showing the effect of the present invention.

FIG. 10 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

[Explanation of symbols]

101 ... Base substrate 102 ... Base protection film 103 ... Source / drain region 104 ... Silicon thin film 105 ... Channel part silicon thin film 106 ... Gate insulating film 107 ... Gate electrode 108 ... Interlayer insulating film 109 ... Source / drain extraction electrode 201 ... Waveguide Tube 202 ... Reaction chamber 203 ... Gas introduction tube 204 ... External coil 205 ... Substrate 206 ... Heater 207 ... Gas introduction tube 501 ... Source / drain region 502 ... Gate electrode 503 ... Source / drain region 504 ... Gate electrode 505 ... Gate electrode 506 Mask material 507 Source / drain region 701 Substrate 702 Base protection film 703 Pad silicon film 704 Second silicon film 705 Gate insulating layer 706 Gate electrode 707 Resist 708 Source / drain region 709 ... cha Silicon film 710 ... Interlayer insulating film 711 ... Wiring 801 ... Insulating substrate 802 ... Base SiO ₂ film 803 ... Silicon thin film containing impurities 804 ... Source / drain region 805 ... Amorphous silicon thin film 806 ... in the SiO ₂ film 809 ... one channel unit to become remaining to have amorphous silicon thin film 810 ... ECR-PECVD method formed by oxidizing an amorphous silicon thin film 807 ... oxygen plasma 808 ... amorphous silicon thin film left length in SiO ₂ film 811 ... silicon thin film constituting the channel portion 812 ... the gate electrode 813 ... source-drain extraction electrodes 1001 ... substrate 1002 ... protective underlayer 1003 ... silicon film 1004 serving as the pad ... second silicon film 1005 deposited ... Over gate insulating layer 1006 ... gate electrode 1007 ... protective cap layer 1008 ... source and drain regions 1009 ... channel portion silicon film 1010 ... interlayer insulating film 1011 ... wire

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 21/31 C 8518-4M 21/324 Z 8617-4M 21/336 29/784 H05H 1/18 9014-2G

Claims (9)

[Claims] 1. A channel portion silicon film semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material,
M in which a gate insulating layer and a gate electrode are formed on the semiconductor layer
In a thin film semiconductor device forming an IS field effect transistor, a step of depositing a silicon film forming a channel portion silicon film semiconductor layer on an insulating material, and a substrate on which the silicon film is formed at 600 ° C. or lower. A method of manufacturing a thin film semiconductor device, comprising: a step of heat treatment at a temperature; and a step of forming a gate insulating layer formed on a channel portion silicon film semiconductor layer by an electron cyclotron resonance plasma CVD method. 2. The thin film semiconductor device according to claim 1, wherein the channel portion silicon film semiconductor layer has a film thickness of 500 Å or less, and a manufacturing method thereof. 3. A gate electrode formed on one surface of a substrate, at least the surface of which is made of an insulating material, so as to face the channel region, the source region, the drain region, and the gate insulating layer with the gate region interposed therebetween. In a thin film semiconductor device having a structure in which at least one of a source region and a drain region does not overlap with a gate electrode through a gate insulating film in a MIS field effect transistor comprising It includes a step of depositing a silicon film forming a layer, a step of forming a source region and a drain region, and a step of heat-treating the substrate on which the channel region and the source region / drain region are formed at a temperature of 600 ° C. or lower. A method for manufacturing a thin film semiconductor device, comprising: 4. A channel portion silicon film semiconductor layer is formed on one surface of a substrate, at least the surface of which is an insulating material,
M in which a gate insulating film and a gate electrode are formed on the semiconductor layer
In a thin film semiconductor device forming an IS type field effect transistor, an amorphous silicon film forming a channel portion silicon film semiconductor layer is deposited on an insulating material, and then a gate insulating layer is formed on the amorphous silicon film. Before
A method of manufacturing a thin film semiconductor device, comprising: a step of irradiating the amorphous silicon film with oxygen plasma; and a step of heat-treating the substrate irradiated with oxygen plasma at a temperature of 600 ° C. or lower. 5. A silicon film formed on a substrate, at least the surface of which is an insulating material, wherein the silicon film is 60
A silicon film, which has been subjected to a heat treatment at 0 ° C. or less, and a part of the silicon film is covered with a silicon oxide film formed by an electron cyclotron resonance plasma CVD method. 6. A silicon film containing impurities serving as a donor or an acceptor, characterized by including the following steps. (1) A step of depositing a silicon film and a step of heat-treating the substrate having the silicon film formed thereon at a temperature of 600 ° C. or lower. (2) A step of forming a silicon oxide film after the above steps. (3) After passing through the above steps, using the bucket type mass non-separation type ion implantation apparatus, using the mixture of the hydride of the impurity element and hydrogen as the source gas, the impurity serving as the donor or the acceptor is used to form the silicon film. Step to drive into. 7. The silicon film according to claim 6, wherein the silicon oxide film is formed by an electron cyclotron resonance plasma CVD method. 8. A channel portion silicon film semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material,
M in which a gate insulating layer and a gate electrode are formed on the semiconductor layer
A method of manufacturing a thin film semiconductor device comprising the following steps in a thin film semiconductor device constituting an IS type field effect transistor. (1) A step of depositing a silicon film on an insulating material, and a step of heat-treating the substrate having the silicon film formed thereon at a temperature of 600 ° C. or lower. (2) A step of forming a gate insulating layer after the above steps. (3) A step of forming a gate electrode on the gate insulating film so as to cover a portion which will later become a channel region after the above steps. (4) After the above steps, a bucket type mass non-separation type ion implanter is used with impurities serving as donors or acceptors using the gate electrode as a mask, and a mixture of hydride of the impurity element and hydrogen as a source gas. Forming a source region and a drain region by implanting. 9. The gate insulating layer is formed by an electron cyclotron resonance plasma CVD method.
A method for manufacturing a thin film semiconductor device according to claim 1.