JPH0512880A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To always write the data in a short writing pulse width by setting temporarily the memory cell driving signal in a non-selection state. CONSTITUTION:A memory cell array consists of the memory cells 1 including the bipolar transistors. A word line driving circuit 2 is added to drive each cell 1 with input of the address input signals VX-VXi and VY1-VYj together with a digit line driving circuit 3, a read/write control circuit 4 which controls the read/write operations of the cell 1 with inversion of a write input signal WE, and a pulse generating circuit 5 which controls both circuits 2 and 3 with the one-shot pulse signal produced with sense of the inversion of the signal WE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device composed of a bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, a device composed of a bipolar transistor has been used as a high speed semiconductor memory device.

FIG. 4 is a circuit diagram of a conventional semiconductor memory device. As shown in FIG. 4, a conventional semiconductor memory device has m rows and n columns of memory cells (MC11 to MCmn).
1 through a word line drive circuit 2 for driving these memory cells 1 via word lines WT1 to WTm, and inversion of digit lines D1 and D1 to inversion of Dn and Dn. It has a digit line drive circuit 3 for driving, a read / write control circuit 4 for controlling reading and writing of data of the memory cell 1 by inverting a write input signal WE, and a sense amplifier 6. These drive circuits 2 and 3 receive an input signal (VX1, VX1, which is a decoded output signal from an address input signal).
It is driven by VXi, VY1 to VYj), but description thereof is omitted here.

Next, the operation of the semiconductor memory circuit will be described. First, the drive circuit 2 selects one word signal line WTi to attain a high level, and at the same time, the drive circuit 3 selects the inversion of one digit line pair Dj, Di. The read current ID or I is applied to the memory cell (MC) 1 selected by these drive circuits 2.3.
The inversion of D flows. Here, in the read operation,
Depending on the potential difference between the read signal potential driven by the read / write control circuit 4 and the internal potential of the selected memory cell 1, the read current ID or ID inversion flows from the selected memory cell, or the read transistor QR.
1 to QRn (inversion of QR1 to inversion of Qn).
For this reason, a difference occurs in the collector currents of the transistors QR and QR that are inverted. The sense amplifier 6 performs a read operation by this difference current. On the other hand, in the write operation, the read / write control circuit 4 outputs a write control signal having a complementary relationship. In the case of a high level signal, the digit line potential becomes high level, and the transistor connected to this digit line also becomes high level in the emitter potential and is turned off. On the contrary, when this is a low level signal, the emitter potential also becomes low level and the transistor is forcibly turned on, and the write operation is performed.

In such a semiconductor memory device, during the write operation, if the setup time of the address input signal with respect to the write input signal is sufficiently long, the time required for writing the data becomes long, and conversely, if the setup time is short,
The data writing time is shortened.

5A and 5B are a setup time characteristic diagram and a write pulse width characteristic diagram in FIG. 4, respectively. As shown in FIGS. 5A and 5B, when the setup time tsA becomes the − side, the write pulse signal t
Since wP is written in the memory cell before the address signal Add changes, it becomes long. That is, when the setup time tsA is short, a cell selected by a change in the address input signal Add is in a transitional period from a non-selected state to a selected state, in other words, in an unstable state, so that data can be easily written by a write signal. It will be possible.
However, if the setup time is sufficiently long, the selected cell is in a stable state, and therefore it takes time to write data.

FIG. 6 is a specific circuit diagram of the memory cell shown in FIG. As shown in FIG. 6, the memory cell 1 has PNP transistors Q1 and Q2 as loads and NPN transistors Q3 and Q4 as data holding means. This P
Since the NP load type memory cell 1 is operated in a deep saturation state, the accumulated charge is large, and this accumulated charge may greatly affect the setup time. Therefore, there is a difference of twice or more between the write pulse widths when the setup time is short and when the setup time is long.

[0008]

The conventional semiconductor memory device described above has a drawback in that the width of the write pulse varies depending on the length of the setup time.

An object of the present invention is to provide a semiconductor memory device which can always write with a short pulse width in the write operation regardless of the length of the setup time.

[0010]

A semiconductor memory device according to the present invention includes a memory cell array including bipolar transistors, a word line drive circuit and a digit for driving each memory cell of the memory cell array in response to an address input signal. A line driving circuit; a read / write control circuit for controlling the read and write operations of each memory cell according to a write input signal; and a word line driving circuit and the word line driving circuit for sensing and generating a one-shot pulse signal. And a pulse generation circuit for controlling the digit line drive circuit.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory device showing an embodiment of the present invention. As shown in FIG. 1, this embodiment has m
A memory cell array composed of memory cells (MC11 to MCmn) 1 in rows and n columns, and a word line drive circuit 2 for driving these memory cells 1 via word lines WT1 to WTm
And the drive circuit 3 driven through the inversion of the digit lines D1 and D1 to the inversion of Dn and Dn, and the write input signal W
The read / write control circuit 4 for controlling the reading and writing of memory cell data by inputting the inversion of E and the sense amplifier 6 are almost the same as the conventional example of FIG. 4 described above. A big difference from the example is that a circuit 5 that senses the inversion of the write input signal WE and generates a one-shot pulse, and transistors QX1 and QY1 that transmit the one-shot pulse signal to the drive circuits 2 and 3.
Is added. In short, this embodiment is
The one-shot pulse is forcibly applied as noise to the selected cell via the transistors QX1 and QY1 of the word line drive circuit 2 and the digit line drive circuit 3 by the output of the pulse generation circuit 5 that generates the shot pulse. ..

FIG. 2 is an input / output waveform diagram of the pulse generating circuit shown in FIG. As shown in FIG. 2, the pulse generation circuit 5 outputs the one-shot pulse signal when the inversion of the write input signal WE is input and becomes low level. Here, the description returns to FIG. 1 again.

First, in the write operation, the pulse generation circuit 5 senses a WE inversion low edge as an input signal and generates a high one-shot pulse signal. That is, the row input signal applied as the write signal is converted into the one-shot pulse output signal by the pulse generation circuit 5, and the inputs of the transistors QX1 to QXm and QY1 to QYn connected to the drive circuits 2 and 3, respectively. It is transmitted as a signal. These drive circuits 2 and 3 are N
Since it is composed of an AND circuit, the selected drive circuit is temporarily brought into a non-selected state by the input one-shot pulse signal. As a result, the memory cell 1 is temporarily brought into an unstable state, and a write control signal driven via the read / write control circuit 4 enters there. Therefore, even when the setup time is long, when the inversion of the write input signal WE is applied, noise is temporarily introduced into the memory cell 1 and writing is easily performed.

On the other hand, in the read operation, since the pulse generating circuit 5 does not respond and the low level is generated, the normal read operation is performed.

FIG. 3 is a circuit diagram of a semiconductor memory device showing another embodiment of the present invention. As shown in FIG. 3, this embodiment also has a memory cell array composed of memory cells 1 arranged in m rows and n columns.
A word line drive circuit 2 and a digit line drive circuit 3 that drive the memory cell 1, and a read / write control circuit 4 that controls reading and writing of data in the memory cell 1.
The pulse generation circuit 5 and the sense amplifier (SA) 6 which generate the one-shot pulse by sensing the inversion of the write input signal WE are the same as those in the above-described embodiment. The present embodiment is different from the above-described one embodiment in that the diode D is provided at the output of the drive circuit 2.3 for driving the memory cell 1.
This is because X1 to DXm and DY1 to DYn were connected, and the cathode side, which is the common connection portion, was connected to the constant current source circuit. In such a memory circuit, the one-shot pulse signal from the pulse generation circuit 5 is transmitted to this constant current source circuit to control the current, but in the normal state, the constant current of this constant current source circuit does not flow, and the pulse signal is Set the constant current to flow only when there is a request. As a result, when the inversion of the write input signal WE is applied during the write operation,
Since the shot pulse signal is generated and the constant current due to this pulse signal flows through the diode connected to the selected drive circuits 2 and 3, the selected drive circuits 2 and 3 are temporarily deselected, Writing will be performed easily.

[0017]

As described above, the semiconductor memory device of the present invention includes a circuit for sensing a write input signal and generating a one shot pulse signal, and a signal for driving a memory cell by the one shot pulse signal. By having a drive circuit which is temporarily in a non-selected state, there is an effect that writing can be always performed with a short writing pulse width in a writing operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is an input / output waveform diagram of the pulse generation circuit shown in FIG.

FIG. 3 is a circuit diagram of a semiconductor memory device showing another embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor memory device showing a conventional example.

5 is a characteristic diagram showing a relationship between a setup time and a write pulse width in FIG.

FIG. 6 is a specific circuit diagram of the memory cell shown in FIG.

[Explanation of symbols]

 1 memory cell 2 word line drive circuit 3 digit line drive circuit 4 read / write control circuit 5 pulse generation circuit 6 sense amplifier (SA) WE inversion write input signal WT1 to WTm word line D1 to Dn, D1 inversion to Dn inversion digit line

Claims (1)

Claim: What is claimed is: 1. A memory cell array including bipolar transistors, a word line drive circuit and a digit line drive circuit for driving each memory cell of the memory cell array in response to an address input signal, and writing. A read / write control circuit that controls read and write operations of each memory cell according to an input signal, and a word line drive circuit and a digit line drive circuit that are controlled by a one-shot pulse signal generated by sensing the write input signal. A semiconductor memory circuit having a pulse generating circuit for