JPH05128741A - Synchronous byte detecting circuit - Google Patents

Abstract

PURPOSE:To keep a tolerance for trouble and to prevent erroneous detection of a synchronous byte by masking the detection signal, which indicates detection of the synchronous byte, or input data in accordance with the detection result of a level signal. CONSTITUTION:Serial data is inputted to a detecting means 111, and this means 111 sends the detection signal indicating detection of the synchronous byte when the degree of coincidence between a bit pattern having a prescribed width of input data and the synchronous byte indicating the synchronizing position of input data is within a prescribed allowable range. A discriminating means 112 discriminates the level signal noticed by the detecting means 111. An output control means 113 normally outputs the detection signal from the means 111 as it is and stops output of the detection signal in accordance with input of the discrimination result indicating detection of the level signal from the means 112. Thus, the tolerance for trouble of the detection processing in the means 111 is effectively used and erroneous detection due to detection in the allowable range of the means 111 is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous byte detecting circuit for detecting a synchronous byte indicating a synchronous position of data read from a recording medium of a magnetic disk device.

In a recording medium of a magnetic disk device,
Following a predetermined bit pattern called a synchronous byte, for example, 1 / 7RLLC (Run Length Limited C
Data that has been modulated by the ode) method is recorded. In this case, the synchronous byte is detected from the read data read from the recording medium, the start position of the data is recognized, the read data is converted to parallel data from this start position, and demodulation processing is performed.

For this reason, there is a need for a synchronous byte detecting circuit that reliably and accurately detects a synchronous byte.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional synchronous byte detecting circuit. Further, FIG. 7 shows an example of read data including a synchronous byte.

This synchronous byte detecting circuit uses a bit pattern "10000" included in the synchronous byte.
10101 "(indicated by symbols (9) to (0) in FIG. 7) is detected, a detection signal indicating that a synchronous byte is detected is transmitted.

In FIG. 6, the read data is input to a 10-bit shift register 201, and the 0th bit, the 2nd bit, and the 4th bit of the output of this shift register 201.
Bit, 9th bit, 6th bit and 7th bit
A bit pair of bits is a 5-input AND gate 202.
a to 202d and four-input AND gate 203 are input in various combinations. Specifically, the bit pairs of the sixth bit and the seventh bit are inverted and input to each of the AND gates 202a to 202d, and the respective bits of the 0th bit, the 2nd bit, the 4th bit, and the 9th bit are input. The three bits are input in various combinations. Further, each bit of the 0th bit, the 2nd bit, the 4th bit, and the 9th bit is input to the AND gate 203.

These AND gates 202a to 202d
The AND gate 203 determines whether or not the input data combination matches the corresponding bit combination of the above-described bit pattern, and sends the determination result to the OR gate 204. The output of the OR gate 204 is output as a detection signal indicating whether or not a synchronous byte has been detected.

That is, the condition and the sign (6) that each bit corresponding to the four bits shown by the signs (0), (2), (4) and (9) in FIG. 7 is a logic "1" respectively. , (7) is configured to output a detection signal indicating that a synchronous byte has been detected when at least four of the conditions that both bit pairs are logical "0" are satisfied.

As described above, since the detection condition of the synchronous byte has a redundancy, it is indicated by reference numerals (0), (2), (4), (9) due to a defect of the recording medium. Even if any of the four bits are missing, or if the bits of the codes (6) and (7) that should originally be logical “0” spring out, such defects can be tolerated. Therefore, it is possible to reliably detect the synchronous bite. As described above, by configuring the synchronous byte detection circuit to have a resistance to a failure, it is possible to prevent the read data from being demodulated and to improve the reliability of the magnetic disk.

[0010]

By the way, when the cable for transmitting the read data from the magnetic head is disconnected during the reading from the recording medium, the level corresponding to the logic "1" is held at the Hi level. The signal may be input to the synchronous byte detection circuit as read data. In this case, in the conventional synchronous byte detection circuit, the output of the AND gate 203b becomes logic "1", and the OR gate 204 sends a detection signal indicating that the synchronous byte has been detected to the demodulation circuit in the subsequent stage. .. In this way, if the conditions for detecting synchronous bytes are made redundant as in the conventional synchronous byte detection circuit, the Hi level signal may be mistakenly recognized as a synchronous byte. there were.

It is an object of the present invention to provide a synchronous byte detecting circuit capable of preventing erroneous detection of a synchronous byte while maintaining resistance to a failure.

[0012]

FIG. 1 is a diagram showing a structure of a synchronous byte detecting circuit according to a first aspect of the present invention. According to a first aspect of the present invention, when serial data is input and the degree of coincidence between the bit pattern of the predetermined width of the input data and the synchronous byte indicating the synchronization position of the input data is within a predetermined allowable range, the synchronous data is synchronized. Detecting means 111 for transmitting a detection signal indicating that a byte has been detected, and determining means 112 for determining whether or not the bit pattern of interest of the detecting means 111 is a level signal in which logic "1" is continuous. When,
Usually, the output control means 113 outputs the detection signal from the detection means 111 as it is and stops the output of the detection signal in response to the input of the determination result indicating that it is the level signal from the determination means 112. Is characterized by.

FIG. 2 is a diagram showing the structure of the synchronous byte detection circuit according to the second aspect. According to a second aspect of the present invention, the level signal detecting means 121 outputs a level detection signal indicating that the level signal has been detected when serial data is input and bits having a logic "1" are continuously input. ,
Serial data is input, and in response to the input of the level detection signal, the transmission control unit 122 that stops the transmission of the serial data, and the serial data is input via the transmission control unit 122, and the predetermined input data is input. And a detection unit 123 for transmitting a detection signal indicating that the synchronous byte is detected when the degree of coincidence between the width bit pattern and the synchronous byte indicating the synchronization position of the input data is within a predetermined allowable range. Is characterized by.

[0014]

According to the first aspect of the present invention, when the Hi level signal in which the bit having the logic "1" is continuous with the predetermined width or more is input, the output control means 113 is operated in accordance with the judgment result by the judgment means 112. The detection signal from the detection means 111 can be masked. On the other hand, when the input data is other than the Hi level signal, the detecting means 111 detects the synchronous byte within a predetermined allowable range as in the conventional case. As a result, it is possible to prevent the erroneous detection of the synchronous byte while maintaining the tolerance of the failure that the detecting unit 111 has.

According to the second aspect of the invention, when the Hi level signal in which the bits of logic "1" are continuous is input, the sending control means 122 responds to the level detection signal from the level signal detection means 121, Input data to the detection means 123 can be masked. On the other hand, when the input data is other than the Hi level signal, the detecting means 123 is used as in the conventional case.
Thus, the synchronous byte is detected within a predetermined allowable range. This makes it possible to prevent erroneous detection of synchronous bytes while maintaining the tolerance of the detection means 123 to the failure.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 3 shows the configuration of an embodiment of the synchronous byte detection circuit according to the first aspect.

In FIG. 3, the detecting means 111 has the same structure as that of the conventional synchronous byte detecting circuit (see FIG. 6).
It is composed of a 0-bit shift register 201, 5-input AND gates 202a to 202d, 4-input AND gate 203, and OR gate 204. This detecting means 111, like the conventional one, uses the 0th bit, the 2nd bit and the 4th bit of the bit pattern held in the shift register 201.
Bit, 9th bit, 6th bit and 7th bit
It is checked whether or not a bit pair of bits matches the five characteristics of the synchronous byte, and when four or more of the five characteristics match, a detection signal indicating that the synchronous byte is detected is output. Has become. That is, when only one of the five features of the synchronous byte does not match, it is determined that the degree of feature matching is within the allowable range and is detected as a synchronous byte.

Further, in FIG. 3, the 0th bit, the 2nd bit, the 4th bit, the 6th bit, the 7th bit, and the 9th bit of the shift register 201 are the AND gates 2.
The AND gate 211 is configured to determine whether or not all of these bits are logic "1".

Here, in the normal data modulated by the 1/7 RLLC method, the bits of logic "1" do not continue, so that the above-mentioned six bits are all logic "1". In this case, the read data is considered to be a Hi level signal. That is, the output of the AND gate 211 described above indicates whether or not the 10-bit read data held in the shift register 201 is all logical “1”.
The function of the determination means 112 is fulfilled.

Further, the inverter 212 and the AND gate 2
13 forms the output control means 113, and the output of the AND gate 211 described above is input to one of the input terminals of the AND gate 213 via the inverter 212. The output of the OR gate 204 of the detecting means 111 described above is input to the other input terminal of the AND gate 213, and the AND gate 213 outputs a detection signal indicating whether or not a synchronous byte is detected. It is configured to send output.

Therefore, when a Hi level signal is input as the read data, the output of the AND gate 211 masks the output signal regardless of whether the detecting means 111 detects the synchronous byte. On the other hand, if the read data is other than the Hi level signal, the output signal of the detection means 111 is sent as it is as the detection signal.

In this manner, as in the conventional case, the synchronous byte is detected with resistance to a failure such as a defect of the medium, and the Hi level signal is synchronized with the allowable range of the matching degree of the detecting means 111. It is possible to prevent erroneous detection as a NAS byte, and it is possible to reliably and accurately detect a synchronous byte.

Further, when this synchronous byte detecting circuit is applied, when apparently abnormal read data such as a Hi level signal is input, the demodulating circuit detects that the synchronous byte has been detected. Since no signal is transmitted, the demodulation circuit does not start the demodulation process. Therefore, when an abnormality such as a cable disconnection from the magnetic head occurs, random demodulation data is not output from the demodulation circuit, and it is necessary to specify that the abnormality occurred before the demodulation circuit. Therefore, quick and appropriate maintenance work can be performed.

As shown in FIG. 4, instead of the AND gate 211 shown in FIG. 3, a 10-input AND gate 3 is provided.
11 may be used to form the determination means 112, and each bit of the read data held in the shift register 201 may be input to each input terminal of the AND gate 311.

In this case, the output of the AND gate 311 becomes the logic "1" only when the read data whose value is the logic "1" is continuous for 10 bits or more.
According to 2, it is possible to more accurately determine whether the input read data is a Hi level signal.

Here, if the Hi level signal is simply detected, it may be determined whether or not the read data of a plurality of consecutive bits are all logical "1". However,
When the number of consecutive bits of logic "1" is less than 10, the output of the AND gate 203 of the detection means 111 does not become logic "1". In this case, therefore, the output signal of the detection means 111 is changed. Masking is useless. On the other hand, if it is assumed that the signal is the Hi level signal when 11 bits or more continue, the output of the AND gate 203 described above is output when the Hi level signal in which the logic "1" is held for exactly 10 bits is input. I can't mask it.

Therefore, in the judging means 112, the range used by the detecting means 111 for detecting the synchronous bytes, that is, the continuous read data of 10 bits is all logical "1".
It is most suitable to determine whether or not

Next, the synchronous byte detecting circuit of claim 2 will be described. FIG. 5 shows a block diagram of an embodiment of the synchronous byte detecting circuit according to the present invention. In FIG. 5, the 8-bit shift register 411 and the 8-input AND gate 412 form a level signal detecting means 121, and the shift register 411 converts the serially input read data into 8-bit parallel data. The AND gate 412 performs the conversion, determines whether or not all the bits of the parallel data are logic "1", and sends the determination result as the detection result of the Hi level signal.

Further, in FIG. 4, the inverter 413 and the AND gate 414 form the sending control means 122, and the detection result by the level signal detecting means 121 is as follows.
The read data is input to one of the input terminals of the AND gate 414 via the inverter 413, and the read data described above is input to the other input terminal of the AND gate 414,
The output of the AND gate 414 is the read data.
It has been sent to the detection means 123.

That is, when the output of the AND gate 411 becomes the logic "1", the sending control means 122
Since the read data is masked, the Hi level signal is not input to the detecting means 123 as the read data.

Therefore, the detecting means 111 shown in FIG.
Similarly, the 10-bit shift register 201, the 5-input AND gates 202a to 202d, the 4-input AND gate 203, and the OR gate 204 form the detection means 123, and the detection means 123 is the same as the conventional one. By performing the byte detection operation, it is possible to prevent the erroneous detection of the synchronous byte while maintaining the resistance to the failure.

Further, as described above, in the 1/7 RLLC method and the 2/7 RLLC method, since the bit which is logic "1" does not continue in the read data, the output of the AND gate 412 is logic "1". If it is, it is clear that the read data is abnormal.

Therefore, if the above-mentioned detection result of the level signal detecting means 121 is sent as an error detection signal to an error processing section (not shown) of the magnetic disk device, the read data from the magnetic head is transmitted. It is possible to easily identify a location where an abnormality has occurred, such as when the cable is cut.

[0034]

As described above, according to the present invention, the detection processing by the detection means has the function of masking the detection signal itself indicating that a synchronous byte is detected or the input data according to the detection result of the level signal. It is possible to prevent erroneous detection of synchronous bytes due to this detection means having a permissible range while making use of tolerance to failures, and to detect synchronous bytes reliably and accurately. A circuit can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a synchronous byte detection circuit according to claim 1;

FIG. 2 is a diagram showing a configuration of a synchronous byte detection circuit according to claim 2;

FIG. 3 is a configuration diagram of an embodiment of a synchronous byte detection circuit according to claim 1;

FIG. 4 is a block diagram of another embodiment of the synchronous byte detection circuit of claim 1;

FIG. 5 is a configuration diagram of an embodiment of a synchronous byte detection circuit according to claim 2;

FIG. 6 is a configuration diagram of a conventional synchronous byte detection circuit.

FIG. 7 is a diagram showing an example of read data including a synchronous byte.

[Explanation of symbols]

111, 123 Detection means 112 Judgment means 113 Output control means 121 Level signal detection means 122 Transmission control means 201, 411 Shift registers 202, 203, 211, 213, 311, 412, 4
14 AND GATE 204 OR GATE 212,413 INVERTER

Claims (2)

[Claims] 1. When the serial data is input and the coincidence between the bit pattern of the predetermined width of the input data and the synchronous byte indicating the synchronization position of the input data is within a predetermined allowable range, the synchronous byte is Detecting means (111) for sending out a detection signal indicating that it has been detected, and determining whether or not the bit pattern of interest by the detecting means (111) is a level signal in which logic "1" is continuous. The determination means (112) and, normally, the detection signal from the detection means (111) is output as it is, and the detection signal is input in response to the determination result input from the determination means (112) indicating that it is a level signal. And a output control means (113) for stopping the output of the synchronous byte detection circuit. 2. A level signal detecting means (121) for outputting a level detection signal indicating that a level signal has been detected when serial data is input and bits having a logic “1” are continuously input. , The serial data is inputted, and the transmission control means (122) for stopping the transmission of the serial data in response to the input of the level detection signal; and the serial control via the transmission control means (122). Data is input, and when the degree of coincidence between the bit pattern of the specified width of the input data and the synchronous byte indicating the synchronization position of the input data is within the specified allowable range, a detection signal indicating that the synchronous byte is detected is sent. Detection means for sending (12
3) A synchronous byte detecting circuit comprising: