JPH0512868A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain a testing mode and to improve the reliability of a semiconductor storage by reducing the amplitude of the output signal of a sense amplifier and equivalently reducing the stored charge amount of a memory cell. CONSTITUTION:A word driver 123 drives selectively the level of a word line based on the decoding output of an X address latch/X decoder 122 provided at the precedent stage. At the same time, a Y selection switch circuit 127 is driven based on the decoding output of a Y address/Y decoder 126. Thus the data can be read out and written into a specified memory cell. A sense amplifier part 129 is connected to a memory cell array 124, and the memory cell information is amplified by the part 129. A control part 125 includes a logic circuit which controls an element to reduce the amplitude of the output signal of a sense amplifier and reduces equivalently the stored charge amount of the memory cell. As a result, a testing mode is attained and the memory cell capacity is easily screened. Then the reliability of a semiconductor storage is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a drive control technique of a sense amplifier included therein, which is, for example, a dynamic RAM (random access memory).
Memory) applied to effective technology.

[0002]

2. Description of the Related Art For example, IS SCS 90, Session 15: Innovative Circuit Design FPM 15.1: Level Shifted and Voltage Reduce 0.5 Micron by Seamos Circuit, pages 36 to 237. Page (ISSCC90, SES
SION15: Innovative Circuit
Design FPM15.1 Level-Shift
ed and Voltage-Reduced Bi
As discussed in CMOS Circuits P236-237), there is known a technique in which a power supply level or an output amplitude level is used separately in timing.

In addition, ISC S8
9, Session 16: Dynamic Rams FM 16.5 A55 Nanosecond 16 Megabit Deramu 246 to 247 (ISSCC89, SES
SION16: DynamicRAMs FAM16.
5 A55ns 16Mb DRAM P246-24
As discussed in 7), when the minute signal Vsig is output from the memory cell, the memory cell and the sense amplifier are disconnected, and the memory cell and the sense amplifier are brought into conduction before the row address strobe signal is reset. A technique for restoring the sense amplifier output is known.

[0004]

On the basis of demands for facilitating testing and high-speed sensing of a semiconductor memory device, application of a technique for using the above-mentioned power supply level or output amplitude level separately in timing. As a result of a study made by the present inventor, it is impossible to use such a technique for testing and high-speed sensing of a semiconductor memory device by simply using the power supply level or the output amplitude level separately in timing. Was found. In addition, as described above, when the minute signal Vsig is output from the memory cell, the memory cell and the sense amplifier are disconnected, and the memory cell and the sense amplifier are electrically connected to each other before the row address strobe signal is reset. In the technique for restoring the bit line, the bit line minute signal (Vsig) is latched before the sensing is started, and it is taken into consideration that Vsig destruction is caused by noise generated in such a latch operation. However, it was found by the present inventor that there is a problem in stable operation.

It is an object of the present invention to make it possible to easily screen the memory cell capacity and easily test the soft error rate margin and the bit line noise margin by making the accumulated charge amount of the memory cell equivalently small. To provide.

Another object of the present invention is to stabilize the sense operation.

Another object of the present invention is to stabilize the operation by reducing power source noise.

Another object of the present invention is to provide a technique capable of preventing Vsig data destruction due to noise during latch operation in the latched sense system.

Another object of the present invention is to reduce the power consumption of the memory cell array.

Another object of the present invention is to improve the reliability of a semiconductor memory device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, as a first means, when a semiconductor memory device is formed including a sense amplifier for amplifying a read signal from a memory cell and a control means for driving and controlling the sense amplifier, the sense amplifier is used. And a control logic for realizing the testing mode by controlling the element to narrow the output signal amplitude of the sense amplifier and equivalently reduce the accumulated charge amount of the memory cell. And are provided.

As a second means, when a semiconductor memory device is formed including a sense amplifier for amplifying a read signal from a memory cell and a control means for driving and controlling the sense amplifier, the output of the sense amplifier is formed. The above control including an element capable of adjusting a signal amplitude and a control logic for controlling the element to realize an operation mode in which the output signal amplitude at the start of sensing of the sense amplifier is narrower than the subsequent output signal amplitude It forms a means.

As a third means, a sense amplifier for amplifying a read signal from a memory cell, a control means for driving and controlling the sense amplifier, and an amplified output of the sense amplifier are transmitted to a common I / O line. When a semiconductor memory device is formed including the column selection switch of the above item, an element for adjusting the output signal amplitude of the sense amplifier and an output signal amplitude at the start of sensing of the sense amplifier by controlling this element. And a control logic that realizes an operation mode for narrowing the output signal amplitude and narrowing the output signal amplitude after the column selection switch is turned on.

As a fourth means, a sense amplifier for amplifying a read signal from the memory cell, a switch for disconnecting the memory cell and the sense amplifier, a control means for driving and controlling the sense amplifier, and the above-mentioned. When a semiconductor memory device is formed including a column selection switch for transmitting an amplified output of a sense amplifier to a common I / O line, an element for adjusting the output signal amplitude of the sense amplifier and a memory cell Immediately after the read minute signal starts to be amplified by the sense amplifier, the switch is turned off to separate the memory cell and the sense amplifier, and the element is controlled to widen the output amplitude of the sense amplifier. After the output is transmitted to the common I / O line, the sense amplifier is turned on by turning on the switch. An output and a control logic for implementing the mode of operation to restore to the memory cell is intended to form the control means.

As a fifth means, a sense amplifier for amplifying a read signal from a memory cell, a control means for driving and controlling the sense amplifier, and an output signal amplitude of the sense amplifier to be narrower than an internal power supply voltage. A semiconductor memory device is formed including an element and level conversion means for limiting the signal amplitude of write data on a bit line when writing data to the memory cell.

[0018]

According to the above-mentioned first means, the control logic is
A testing mode is realized by controlling the elements to narrow the output signal amplitude of the sense amplifier and equivalently reducing the amount of charge accumulated in the memory cell, which results in screening of the memory cell capacity and soft error. Enables testing of rate margin and noise margin between bit lines.

According to the above-mentioned second means, the control logic controls the element to realize an operation mode in which the output signal amplitude at the start of sensing of the sense amplifier is narrower than the output signal amplitude thereafter. This achieves a stable sense operation.

According to the above-mentioned third means, the control logic controls the element to narrow the output signal amplitude at the start of sensing of the sense amplifier, and after the column selection switch is turned on. A mode of operation that widens the amplitude of the output signal is realized, which achieves stabilization of operation by reducing power supply noise.

According to the above-mentioned fourth means, the control logic controls the memory cell and the sense amplifier by turning off the switch immediately after the minute signal read from the memory cell starts to be amplified by the sense amplifier. And the output amplitude of the sense amplifier is expanded by controlling the elements, and after the output is transmitted to the common I / O line, the switch is turned on to output the sense amplifier output to the memory. The operation mode of restoring to the cell is realized, which prevents Vsig data destruction due to noise during the latch operation in the latched sense system.

According to the above-mentioned fifth means, the element is
The output signal amplitude of the sense amplifier is made narrower than the internal power supply voltage, and the level conversion means limits the signal amplitude of the write data on the bit line when writing data to the memory cell. Acts to reduce power consumption.

[0023]

FIG. 9 shows a dynamic RAM according to an embodiment of the present invention. Dynamic RA shown in FIG.
Although not particularly limited, M is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 9, reference numeral 124 denotes a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction and data input terminals of the memory cells are connected to each other. It is coupled to complementary bit lines in each column direction. Each complementary bit line is commonly connected to the complementary common bit line through a Y selection switch circuit 127 including a plurality of column selection switches coupled to the complementary bit line on a one-to-one basis.

Although not particularly limited, the dynamic RAM of the present embodiment adopts the address multiplex method, and the row and column address input signals are fetched from a common address terminal by shifting their timings. That is, the X address latch and X decoder 122 and the Y address latch and Y decoder 12
An address multiplexer 121 is arranged in the preceding stage of 6, and an address signal taken in via the address buffer 120 is distributed by the address multiplexer 121 to an X address latch and X decoder 122 and a Y address latch and Y decoder 126. In order to smoothly perform such address input, two types of clock signals, a row address strobe signal RAS * (* indicates low active) and a column address strobe signal CAS *, are externally supplied. Since only one read or write operation is possible during one memory cycle (one cycle of the RAS * clock), the row address is at the falling edge of the RAS * clock and the column address is at the falling edge of the CAS * clock. Are taken into the internal circuit, and it is possible to judge whether the cycle is a write cycle or a read cycle depending on the state of the write enable signal WE *. The control unit 125 performs such determination and operation control of each unit.

The word driver 123 drives the word line to the selection level based on the X address latch and the decode output of the X decoder 122 arranged in the preceding stage.
Then, the Y selection switch circuit 127 is driven based on the Y address latch and the decoded output of the Y decoder 126, thereby enabling data read or data write from the specified memory cell. A sense amplifier unit 129 is coupled to the memory cell array 124, and the memory cell information is amplified by the sense amplifier unit 129. In this case, the data input / output circuit 128 includes a main amplifier, an input buffer, etc., so that data can be exchanged with the outside.

FIG. 1 shows the detailed structure of the main part of the dynamic RAM.

In the memory cell array 124, a plurality of dynamic memory cells each having two memory cell capacitors CS connected in series and having N-channel MOSFETs 51 and 52 coupled thereto are arranged. A plate level VP is connected to the serial connection point of the two memory cell capacitors CS.
L (potential of about 1/2 of internal power supply VDL) is applied. The gates of the MOSFETs 51 and 52 are coupled to the word lines 8 and 9, and the sources are coupled to the bit line pair (complementary bit line). This bit line pair includes a high side bit line 18 and a low side bit line 19.

The sense amplifier section 129 includes a sense amplifier SA connected to the bit lines 18 and 19 and a precharge / equalize circuit PE for the bit lines 18 and 19.
Including and The sense amplifier SA is a P-channel type MOS
It is formed by coupling two sets of inverters INV1 and INV2, each of which is composed of an FET and an N-channel MOSFET connected in series. Also, the above precharge
The equalize circuit PE has a bit line precharge level H.
N-channel MOSF for applying VDL (potential of about 1/2 of internal power supply VDL) to the bit lines 18 and 19.
It includes ETs 54 and 55 and N-channel MOSFET 53 for short-circuiting bit lines 18 and 19. This MO
The SFETs 53, 54 and 55 are driven by the bit line precharge signal PC.

The Y selection switch circuit 127 is selectively driven by the column selection switch signals 20 and 21.
By including the OSFET 56, the selection operation of the MOSFET 56 enables the bit lines 18 and 19 to be selectively coupled to the common I / O lines 22 to 25.

Further, the control section 125 includes a logic circuit 200 for controlling the operation of the sense amplifier SA based on the sense amplifier start signal SAS, the refresh signal REF and the half restore test signal QCTEST. , Is formed as follows.

Inverter 66 is arranged, and sense amplifier starting signal SAS is inverted by this inverter 66 and transmitted to P-channel MOSFET 11. The MOSFET 11 is coupled to the N-channel common source 16 of the sense amplifier SA and the external low potential side power source VSS. In addition, the output signal of the inverter 66 is inverted by the inverter 64 and then the N-channel type M
It is transmitted to the OSFET 12. The MOSFET 12 is a P channel common source 17 of the sense amplifier SA.
Is coupled to the internal power supply VDL. Furthermore, the refresh signal REF and the half restore test signal QCTEST
The NAND logic of and is obtained by the 2-input NAND gate 61, and the output of the NAND gate 61 is inverted by the inverter 62 at the subsequent stage and transmitted to one input terminal of the 2-input NOR gate. In the NOR gate 63, NAND logic of the outputs of the inverters 62 and 66 is obtained, and the NAND logic output is delayed by the delay circuit 13 arranged in the subsequent stage for a predetermined time, and then the N-channel MOSFET 14 and the inverter 65 in the subsequent stage are output. It is transmitted to the P-channel type MOSFET 15 via. The MOSFET 14 is coupled to the N-channel common source 16 of the sense amplifier SA and the external low potential side power supply VSS. Further, the MOSFET 15 is coupled to the P-channel common source 17 of the sense amplifier SAS and the internal power supply VDL.

Although not particularly limited in the above structure,
When the external high-potential-side power supply VCC is set to 5V, the internal power supply VDL is set to about 3.3V, and the memory cell plate level VPL and the bit line precharge level HVDL are about 1/2 the value of the internal power supply VDL, that is, 1.V. It is set to about 65V. Now, after the bit line precharge signal PC is asserted to set the bit lines 18 and 19 to the bit line precharge level HVDL, the memory cell array 1
Consider the case where 24 word lines 9 are driven to the selected level. At that time, if the information written in the memory cell is at a high level, a high level minute signal due to charge sharing appears on the bit line 18, and conversely, if the memory cell information is at a low level, a low level minute signal is generated. The signal is read. Such a minute signal Vsig is amplified by the sense amplifier SA. The signals on the bit lines 18 and 19 are transmitted to the common I / O lines 24 and 25 when the column selection switch signal 20 is asserted. Similarly, when the other column selection switch signal 20 is asserted, the signal on the bit line corresponding to the asserted common I / O signal.
It can be transmitted to the O lines 24 and 25.

The main operations of this embodiment include a half restore operation, a full restore operation, and a two-stage sense operation, which will be described in detail below.

FIG. 2 shows a logical state of a main part in the half restore operation.

As shown in FIG. 2, the refresh signal REF is asserted to the high level while the half restore test signal QCTEST is asserted to the high level, thereby enabling the half restore test at the time of refresh. . That is, when the sense amplifier activation signal SAS is asserted to the high level, the MO
The SFETs 11 and 12 are turned on, and the minute signals Vsig read from the memory cells are caused by the respective threshold voltages.
Are amplified to the levels of VDL-VTN1 and VSS + VTP1. Here, VTP1 and VTN1 are threshold values of the MOSFETs 11 and 12, respectively. Such an amplitude is about 1/2 of the normal inter-bit-line amplitude VDL when it is considered that | VDL-VSS | is almost equal to four times the threshold value of the MOSFET. This VDL-V
TN1, VSS + VTP1 level is bit line 1 respectively
The data is restored to the memory cell via 8 and 19. The accumulated charge amount QC is about ½ of that at the time of full restoration when the amplitude of the normal VDL is normal. By this operation, the amount of accumulated charge when the memory cell capacitance CS is equivalently reduced can be obtained.
That is, the accumulated charge amount QC (H) at the time of full restore is QC (H) = 1/2 (CS × VDL), and the accumulated charge amount Q′C (H) at the time of half restore.
Is Q′C (H) = CS × (VDL / 2−VTN1), and QC (H) −Q′C (H) = CS × VTN1 | VTN1 | ≈≈VDL / 4 Equivalent memory cell capacity C
SH is set as CSH≈CS (| VTP1 | ≈VDL / 4) / 2.

Therefore, according to the half-restoring operation, the accumulated charge amount when the memory cell capacitance CS is equivalently reduced can be obtained, so that there is an abnormality in the memory cell capacitance CS due to a failure or the like, and the capacitance value is predetermined. If it is less than the value, it can be screened. The minute signal Vsig read from the memory cell is V
It is amplified to the level of DL-VTN1 and VSS + VTP1, and since such an amplitude becomes smaller than the normal VDL amplitude, a soft error is likely to occur. In addition, noise resistance between bit lines is reduced. Because of this, a soft error rate test and a test for noise margin between bit lines can be performed simultaneously during the screening.

FIG. 3 shows a logical state of a main part in the full restore operation.

Incidentally, it is assumed that during the full restore operation, the involvement of the delay circuit 13 is eliminated or the delay time there is set to an extremely short time.

As shown in FIG. 3, when the half restore test signal QCTEST is negated to low level and the refresh signal REF is asserted to high level, the output of the inverter 62 in FIG. 1 is set to low level, A change in the output state of the inverter 66 that inverts the sense amplifier activation signal SAS is made to be able to pass through the NOR gate 63. As a result, the sense amplifier activation signal SA
When S is asserted to the high level, the MOSF
After the ETs 11 and 12 are turned on, a slight time delay occurs due to a signal transmission delay in the NOR gate 63 and the like, and the MOSFET 1
4, 15 are turned on. That is, at the start of sense,
The common sources 16 and 17 of the sense amplifier SA are driven by turning on the MOSFETs 11 and 12, and the potentials of the common sources 16 and 17 of the sense amplifier SA become VSS and VDL by turning on the MOSFETs 14 and 15 after a short time. When it reaches the VDL amplitude, it is restored to the memory cell. That is, when the amplification of the minute signal Vsig from the memory cell is started, the MOS
By turning off the FETs 14 and 15, the drive source at the start of amplification of the minute signal Vsig can be reduced to about 1/2 of that at the time of full sense.
It is possible to stabilize the sense operation by improving the sense sensitivity at the start of amplification of the.

FIG. 4 shows the logical states of the main parts in the two-stage sensing operation.

As shown in FIG. 4, when the half restore test signal QCTEST is negated to the low level and the refresh signal REF is asserted to the high level, the output of the inverter 62 in FIG. 1 is set to the low level, A change in the output state of the inverter 66 that inverts the sense amplifier activation signal SAS can be transmitted to the delay circuit 13 via the NOR gate 63. Thereby, after the sense amplifier activation signal SAS is asserted to the high level to turn on the MOSFETs 11 and 12, after a predetermined delay time T1 in the delay circuit 13, the MOSFET 1 is turned on.
4, 15 are turned on. That is, after the small signal Vsig is amplified to VDL-VTN1 to VSS + VTP1 at the start of sensing, it is delayed by the delay time T1 in the delay circuit 13 and further fully sensed to VDL to VSS. The column selection switch signal 20 is asserted to a high level before the start of this full sense to couple the bit lines 18 and 19 to the common I / O lines 24 and 25,
External output of the full sense result is enabled. According to such an operation, the common source current peak value can be dispersedly reduced by the two-stage sense timing having a predetermined delay, so that the power source noise is reduced and the operation is stabilized.

According to the above embodiment, the following operational effects can be obtained.

(1) Half restore test signal QCTE
By asserting the refresh signal REF to the high level while the ST is asserted to the high level, the half-restoration test at the time of refresh can be performed. In such a testing mode, the output signal amplitude of the sense amplifier SA can be obtained. Is realized by narrowing the memory capacity, and the accumulated charge amount QC is set to about half of that at the time of full restoration at the time of normal VDL amplitude, whereby an abnormality such as a failure of the memory cell capacitance CS can be screened. At the same time, it is possible to perform a soft error rate test and a test for noise margin between bit lines. By performing such screening and testing, the dynamic R
AM reliability is improved.

(2) Half restore test signal QCTE
ST is negated to the low level, and the refresh signal R
When EF is asserted to the high level, the change in the output state of the inverter 66 is enabled to pass through the NOR gate 63. In this mode, the involvement of the delay circuit 13 is eliminated, and after the MOSFETs 11 and 12 are turned on by asserting the sense amplifier activation signal SAS to a high level, a slight time delay occurs due to a signal transmission delay in the NOR gate 63 or the like. The MOSFETs 14 and 15 are turned on. That is, at the start of sensing, the MOSFET 11,
When the switch 12 is turned on, the common sources 16 and 17 of the sense amplifier SA are driven.
When T14 and T15 are turned on, the sense amplifier SA
When the potentials of the common sources 16 and 17 reach VSS and VDL, the VDL amplitude is expanded. In this way, the amplitude of the sense amplifier output signal at the start of amplification of the minute signal Vsig is suppressed to about 1/2 of that at the time of full sense, so that the sense sensitivity at the start of amplification of the minute signal Vsig is improved and the sense operation is stabilized. It is possible to improve the reliability of the dynamic RAM of this embodiment.

(3) Half restore test signal QCTE
ST is negated to the low level, and the refresh signal R
When EF is asserted to a high level, a change in the output state of the inverter 66 can be transmitted to the delay circuit 13 via the NOR gate 63, and the sense amplifier start signal SAS can be transmitted.
Is asserted to a high level
The two-stage sense mode is realized by turning on the MOSFETs 14 and 15 after a predetermined delay time T1 in the delay circuit 13 after the T11 and 12 are turned on. In this mode, the minute signal Vsig is V
After being amplified to DL-VTN1 to VSS + VTP1,
After delaying by the delay time T1 in the delay circuit 13, VD
Since full sensing is performed from L to VSS, the common source current peak value is reduced by dispersion and the power supply noise is reduced, so that the operation is stabilized and the reliability of the dynamic RAM of this embodiment is improved.

FIG. 5 shows a detailed structure of a main part of a dynamic RAM according to another embodiment of the present invention.

In FIG. 5, the same symbols are given to those having the same functions as those shown in FIG.

In FIG. 5, reference numerals 38 and 39 denote mat-divided memory cell arrays, each of which includes a plurality of memory cells. Although the detailed structure of the memory cell is not shown, as in the case of FIG. 1, two memory cell capacitors CS are connected in series and an N channel type MOS is connected to the memory cell capacitor CS.
A combination of FETs 51 and 52 is applied.
A shared switch 80 for disconnecting the memory cell array 38 on the left side of the drawing from the sense amplifier unit 129.
Is provided, and a shared switch 81 for disconnecting the memory cell array 39 on the right side of the drawing from the sense amplifier unit 129 is provided. This shared switch 80,8
1 is formed by a plurality of N-channel MOSFETs corresponding to the bit lines 18 and 19, respectively, and the control unit 12
The operation is controlled by the one-shot pulse latch signals 35 and 36 generated by the logic circuit 200A forming the main part of FIG. The logic circuit 200A is configured as follows.

Inverter 6 is similar to that shown in FIG.
6 is arranged, the sense amplifier starting signal SAS is inverted by the inverter 66, and the P channel type MOSF
It is transmitted to ET11. The MOSFET 11 is coupled to the N-channel common source 16 of the sense amplifier SA and the external low potential side power source VSS. The output signal of the inverter 66 is inverted by the inverter 64 and then transmitted to the N-channel MOSFET 12. This MOSFET 12 is the P of the sense amplifier SA.
The channel common source 17 is coupled to the internal power supply VDL. The N-channel MOSFET 14 coupled to the N-channel common source 16 of the sense amplifier SA and the external low potential side power source VSS has a full sense signal 33.
The P-channel common source 17 of the sense amplifier SA and the P-channel MOSFET 15 coupled to the internal power supply VDL are driven and controlled by the full sense signal 3
The drive is controlled by the control unit 4.

Further, a delay circuit 37 for delaying the sense amplifier activation signal SAS by a predetermined time is provided, and the delayed output is inverted at the subsequent stage of the delay circuit 37 and transmitted to one input terminal of a 2-input NAND gate 72. An inverter 71 for performing the operation is arranged. A full sense signal 33 for driving and controlling the N-channel MOSFET 14 is taken out from the input side of the inverter 71, and the P-channel MOSFET 1 is output from the output side of the inverter 71.
A full sense signal 34 for driving and controlling 5 is taken out. The sense amplifier starting signal SAS is also transmitted to the other input terminal of the NAND gate 72, and the NAND logic between the sense amplifier starting signal SAS and the output signal of the inverter 71 is obtained. There is. And this NAND logic is applied to the inverter 73 in the subsequent stage.
Is transmitted to one of the input terminals of the 2-input NOR gates 43A and 43B. The shared switch selection signal SHRL is input to the other input terminal of the NOR gate 43A after being inverted by the inverter 74, and the NOR logic between the output of the inverter 74 and the output of the inverter 73 is It can be obtained by the NOR gate 43A. The output of the NOR gate 43A serves as a one-shot pulse latch signal 35 for controlling the operation of the shared switch 80. The shared switch selection signal SHRR is input to the other input terminal of the NOR gate 43B after being inverted by the inverter 75, and the NOR logic of the output of the inverter 75 and the output of the inverter 73. Are obtained by this NOR gate 43B. The output of the NOR gate 43B serves as a one-shot pulse latch signal 36 for controlling the operation of the shared switch 81. Here, the NOR gate 43
The power supply voltage VCH of A and 43B is not particularly limited,
5V, which is approximately equal to VDL + 2VTH.

Next, the main operation of the above configuration will be described.

FIG. 6 shows a logical state of a main part in the half-latched sense operation.

In the logic state shown in FIG. 6, the shared switch selection signal SHRL is asserted to the high level,
It is assumed that the shared switch selection signal SHRR is negated to the low level and the sense amplifier activation signal SAS is asserted to the high level. The half-latched sense operation is started by the assertion of the sense amplifier activation signal SA, and the minute signal Vsi read from the memory cell in the memory cell array 38 is read.
Immediately after g is started to be amplified by the sense amplifier SA, the logic state of the bit lines 41 and 42 in the memory array is latched. Further, the minute signal Vsig
It is amplified to a slightly larger amplitude. Such a signal is
The one-shot pulse latch signal 35 is set to the low level and the shared switch 80 is turned off to prevent the restore, and the sense amplifier SA further increases the V level.
After being amplified to the amplitudes of DL-VTN1 to VSS + VTP1, the column selection signal 20 is set to the high level, so that the common I / 0 lines 24 and 25 are selectively transmitted. The sense amplifier activation signal SAS is transmitted to the delay circuit 37 at T2.
Full sense signal 3 obtained by time delay
By asserting 3, 34, the sense amplifier S
After A starts full-sense, the one-shot pulse operation causes the one-shot pulse latch signal 35 output from the NOR gate 43A to be set to the high level and the shared switch 80 to be turned on, whereby VDL to VS.
The full amplitude of S depends on the bit lines 41, 4 in the memory cell array.
Restored via 2 to the memory cell.

According to the above embodiment, the following operational effects can be obtained.

(1) According to the half-latched sense operation as described above, the half-sense operation is started by the assertion of the sense amplifier activation signal SA, and the minute signal read from the memory cell in the memory cell array 38 is started. Immediately after Vsig starts to be amplified by the sense amplifier SA, the shared switch 80 is turned off to latch the logic states of the bit lines 41 and 42 in the memory array. The minute signal Vsig is the sense amplifier SA
Is amplified to VDL-VTN1 to VSS + VTP1 amplitudes, transmitted to the common I / 0 lines 24 and 25, and then fully restored by turning on the shared switch 80. As a result, the minute signal Vsig is amplified to a level at which it is not damaged even if it receives noise during the latch operation, so that malfunction is eliminated and the reliability of the dynamic RAM of this embodiment is improved.

(2) In the half-latched sense operation, since the shared switch 80 is turned off, the bit lines 41 and 42 in the memory array do not become the load of the sense amplifier SA, so the load of the sense amplifier SA is reduced. There is an advantage that

(3) In the half-latched sense operation, the two-stage sense (restore) of amplification up to VDL-VTN1 to VSS + VTP1 amplitude and VDL to VSS restore
Since it is an operation, the common source current peak can be dispersed / reduced by the two-stage sense timing, a stable operation can be obtained by reducing the power source noise, and a high-speed amplification operation by the latched sense can be performed.

7 and 8 show the structure of the main part of a dynamic RAM according to another embodiment of the present invention.

For example, in FIG. 1 and FIG. 5, a P-channel MOSFET 1 used for full restore (sense).
Even if the 4 and P-channel MOSFETs 15 are omitted, the above half restore operation is possible.
FIG. 7 shows the main part of the logic circuit 200B forming the control unit 125 in such an embodiment. In that case, VDL-VTN1, as shown in FIG.
VSS + VTP1 level conversion circuit 90 and write circuit 91
It is possible to configure the dynamic RAM including.

VDL-VTN1, VSS + VTP1
The level conversion circuit 90 is configured as follows. P-channel type MOSFET 95 and N-channel type MOSFET
An inverter INV3 formed by connecting T96 in series and P
Channel type MOSFET 98 and N channel type MOS
The inverter INV4 formed by connecting the FET 97 in series is coupled, and the P-channel type MOSFETs 95 and 9 are connected.
8 is coupled to the high-potential-side internal power supply VDL via the N-channel MOSFET 12A,
SFETs 96 and 97 are P-channel MOSFETs 11
It is coupled to the low potential side internal power supply VSS via A.

Further, the write circuit 91 has a common I /
It includes an N-channel MOSFET 93 arranged between the O line 22 and the output terminal of the inverter INV3, and an N-channel MOSFET 94 arranged between the common I / O line 23 and the inverter INV4. Reference numeral 46 is a main amplifier that amplifies the signals of the common I / O lines 22 and 23. The MOSFETs 93 and 94 are controlled by the read / write signal 47. That is, when the read / write signal 47 is at high level, the MOSFETs 93, 9
4 is turned on and the input data Din is common I / O line 2
2, 23, and data can be written in the memory cell. Further, when the read / write signal 47 is at the low level, the MOSFETs 93 and 94 are turned off, and the data read from the memory cell is transferred to the common I / O lines 22 and 2.
It can be taken into the main amplifier 46 via

In the above configuration, the amplitude of the write / read signal restored to the memory cell is | (VDL-VTN
1) − (VSS + VTP1) | ≧ 2VTH, and having a memory cell capacity CS capable of ensuring sufficient Vsig, CB (bit line capacity) / CS (memory cell capacity) ≧ 12, in the level conversion circuit 90, Signal amplitude from memory cell to main amplifier | (VDL-VTN
1)-(VSS + VTP1) |
The signal amplitude in the memory array is about 1/2 of the peripheral circuit power supply voltage
Therefore, the power consumption of the memory cell array can be reduced. The power consumption in the memory array is about 40 of the entire chip when the VDL amplitude is the same in the memory array and the peripheral circuits.
Since this occupies about 50%, the power consumption in this memory array is about 20 to 30% of the whole chip when this method is used.
It can be reduced. Further, such a reduction in power consumption reduces the temperature rise of the junction associated with the memory cell, thereby reducing the amount of leakage of information holding charges from the memory cell. That is, it is possible to prevent the deterioration of the information holding time margin due to the rise in the chip temperature, and to improve the reliability of the dynamic RAM.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example, in the above embodiment, it has been described that a plurality of operation modes are realized in a single dynamic RAM, but it is of course effective to realize one of the plurality of operation modes in a single RAM. To be done.

In the above description, the invention made by the present inventor was mainly described as a dynamic RAM which is a field of application which is the background of the invention, but the present invention is not limited thereto, and a pseudo static RAM, a video RAM, etc. The present invention can be widely applied to various semiconductor memory devices, as well as a memory on-chip in a semiconductor integrated circuit such as a microcomputer.

The present invention can be applied on condition that at least a memory cell is included.

[0067]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the testing mode is realized by controlling the elements to narrow the output signal amplitude of the sense amplifier and equivalently reducing the accumulated charge amount of the memory cell, thereby screening the memory cell capacity. Also, it is possible to easily perform the soft error rate margin and the bit line noise margin testing. By performing such screening and testing, the reliability of the semiconductor memory device is improved.

By stabilizing the sense operation by realizing the operation mode in which the output signal amplitude at the start of sensing of the sense amplifier is narrower than the subsequent output signal amplitude, the reliability of the semiconductor memory device is improved. Is improved.

By realizing an operation mode in which the output signal amplitude at the start of sensing of the sense amplifier is narrowed and the output signal amplitude is widened after the column selection switch is turned on, the power supply noise is reduced and the operation is reduced. Of the semiconductor memory device is improved, thereby improving the reliability of the semiconductor memory device.

Immediately after the minute signal read from the memory cell starts to be amplified by the sense amplifier, the switch is turned off to disconnect the memory cell and the sense amplifier and control the element to control the sense amplifier. The output amplitude of the common I /
After being transmitted to the O line, by turning on the switch, an operation mode for restoring the output of the sense amplifier to the memory cell is realized, and Vs caused by noise at the latch operation in the latched sense system is realized.
Since the ig data destruction is prevented, the reliability of the semiconductor memory device is improved.

The output signal amplitude of the sense amplifier is narrower than the internal power supply voltage, and the signal amplitude of the write data on the bit line is limited when writing data to the memory cell, thereby reducing the power consumption of the memory cell array. As a result, the deterioration of the information retention time margin due to the rise in the chip temperature is prevented, and the reliability of the semiconductor memory device is improved.

[Brief description of drawings]

FIG. 1 is a dynamic R according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a main part of AM.

FIG. 2 is an explanatory view of a main part state in a half restore operation of the dynamic RAM.

FIG. 3 is a state explanatory diagram of a main part in a full restore operation (full sense operation) of the dynamic RAM.

FIG. 4 is an explanatory view of a main part state in a two-stage sensing operation of the dynamic RAM.

FIG. 5 is a circuit diagram showing a configuration of a main part of a dynamic RAM according to another embodiment of the present invention.

FIG. 6 is an explanatory view of a state of a main part in a half latched sense operation of the dynamic RAM shown in FIG.

FIG. 7 is a circuit diagram showing a configuration of a main part of a dynamic RAM according to another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a main part of a dynamic RAM according to another embodiment of the present invention.

FIG. 9 is an overall configuration block diagram of a dynamic RAM.

[Explanation of symbols]

CS memory cell capacity QCTEST Half restore test signal REF refresh signal SAS sense amplifier start signal SHRL shared switch selection signal SHRR shared switch selection signal 11 P-channel MOSFET 12 N-channel MOSFET 14 N-channel MOSFET 18 bit line 19 bit line 15 P-channel MOSFET 35 One-shot pulse latch signal 36 One-shot pulse latch signal 120 address buffer 121 address multiplexer 122 X Address Latch and X Decoder 123 word driver 124 memory cell array 125 control unit 126 Y address latch and Y decoder 127 Y selection switch circuit 128 data input / output circuit 129 Sense amplifier section 200 logic circuits 200A logic circuit 200B logic circuit

Claims (5)

[Claims] 1. A semiconductor memory device comprising a sense amplifier for amplifying a read signal from a memory cell and a control means for driving and controlling the sense amplifier, wherein the control means controls the output signal amplitude of the sense amplifier. And a control logic that controls the element to narrow the output signal amplitude of the sense amplifier and equivalently reduce the amount of charge stored in the memory cell to realize a testing mode. A semiconductor memory device characterized by the above. 2. A semiconductor memory device comprising a sense amplifier for amplifying a read signal from a memory cell and a control means for driving and controlling the sense amplifier, wherein the control means controls the output signal amplitude of the sense amplifier. An element that is adjustable, and control logic that controls the element to realize an operation mode in which the output signal amplitude at the start of sensing of the sense amplifier is narrower than the subsequent output signal amplitude. Semiconductor memory device. 3. A sense amplifier for amplifying a read signal from a memory cell, a control means for driving and controlling the sense amplifier, and an amplified output of the sense amplifier as a common I.
In a semiconductor memory device including a column selection switch for transmitting to the / O line, the control means includes an element capable of adjusting the output signal amplitude of the sense amplifier, and the sense amplifier of the sense amplifier by controlling the element. A semiconductor memory device, comprising: a control logic that narrows an output signal amplitude at the start of sensing and realizes an operation mode in which the output signal amplitude is widened after the column selection switch is turned on. 4. A sense amplifier for amplifying a read signal from a memory cell, a switch for disconnecting the memory cell and the sense amplifier, a control means for driving and controlling the sense amplifier, and a sense amplifier of the sense amplifier. In a semiconductor memory device including a column selection switch for transmitting an amplified output to a common I / O line, the control means includes an element capable of adjusting an output signal amplitude of the sense amplifier,
Immediately after the minute signal read from the memory cell starts to be amplified by the sense amplifier, the switch is turned off to disconnect the memory cell and the sense amplifier, and at the same time, control the element to control the output amplitude of the sense amplifier. And a control logic for realizing an operation mode for restoring the output of the sense amplifier to the memory cell by turning on the switch after the output is transmitted to the common I / O line. A characteristic semiconductor memory device. 5. A sense amplifier for amplifying a read signal from a memory cell, a control means for driving and controlling the sense amplifier, and an element for narrowing an output signal amplitude of the sense amplifier below an internal power supply voltage. A semiconductor memory device comprising level conversion means for limiting a signal amplitude of write data on a bit line when writing data to the memory cell.