JPH05127901A - Processor - Google Patents

Abstract

PURPOSE:To provide a high speed processor whose performance is not deteriorated by means of an instruction whose processing speed is slow. CONSTITUTION:An instruction reader 2 sequentially reads instructions stored in an instruction storage device 1 with subsequent and plural instructions at every machine cycle, and temporarily stores them in a temporary instruction storage device 3. An execution controller 5 checks a subsequent multiplication instruction stored in the temporary instruction storage device 3 and allocates division instructions decoded by an instruction decoding device 4 to a high speed multiplication/division device 7 or a low speed division device 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor for high speed processing.

[0002]

2. Description of the Related Art In recent years, processors having a built-in addition / subtraction device and a multiplication / division device for performing division by iterative calculation of multiplication have become mainstream.

An example of a conventional processor will be described below with reference to the drawings. FIG. 3 is a block diagram of a conventional processor. In FIG. 3, 11 is an instruction storage device for storing instructions, 12 is an instruction reading device for reading out instructions, 13 is an instruction decoding device for decoding the read instructions, 14 is an addition / subtraction device for performing addition or subtraction, and 15
Is a multiplication / division device for performing multiplication or division, and 16 is a data storage device for storing data. Instruction reading device 1
2, instruction decoding device 13, addition / subtraction device 14, multiplication / division device 1
5 operates in a pipeline, the instruction reading device 12, the instruction decoding device 13, and the addition / subtraction device 14 perform processing in one machine cycle, and the multiplication / division device 15 performs multiplication in one machine cycle, and division is repeated by iterative calculation of multiplication to obtain four divisions. Do it in a machine cycle.

The operation of the processor configured as described above will be described below.

The instruction reading device 12 is an instruction storage device 11.
The instructions stored in are sequentially read every machine cycle. The instruction decoding device 13 decodes the instruction read by the instruction reading device 12 in one machine cycle, allocates an addition instruction or a subtraction instruction to the addition / subtraction device 14, and allocates a multiplication instruction or a division instruction to the multiplication / division device 15. The adder / subtractor 14 adds or subtracts the instructions assigned by the instruction decoder 13 in one machine cycle.
Similarly, the multiplication / division device 15 performs multiplication or division,
Multiplication is performed in one machine cycle and division is performed in four machine cycles. The calculation performed by the adder / subtractor 14 and the multiplication / division device 15 is performed on the data stored in the data storage device 16, and the calculation result is stored in the data storage device 16. FIG. 4 shows a pipeline state diagram from instruction decoding to execution of a conventional processor in the case where division, multiplication, division, multiplication and instructions follow. However, it is assumed that the data used in the calculation to be executed is stored in the data storage device 16 at the start of the calculation.

[0006]

However, in the above configuration, when there is a multiplication instruction following a division instruction, the multiplication / division device cannot perform other processing during the four machine cycles of the division execution. The subsequent multiplication has to be performed after the division is completed, which has a problem of degrading the performance of the processor.

In view of the above problems, the present invention provides a high-speed processor which does not deteriorate the performance due to an instruction having a slow processing speed.

[0008]

In order to solve the above problems, a processor according to the present invention comprises a plurality of execution units having different execution speeds for processing a plurality of same-type instructions and an instruction for reading a plurality of instructions. A reading device, an instruction temporary storage device for temporarily storing a plurality of instructions read by the instruction reading device, an instruction decoding device for decoding an instruction stored in the instruction temporary storage device, and the instruction temporary storage An execution control device for allocating an instruction decoded by the instruction decoding device to any one of a plurality of execution devices by using a plurality of instructions stored in the device.

[0009]

With the above-described structure, the present invention allocates an instruction with a slow processing speed to either a high-speed execution device or a low-speed execution device by using a plurality of subsequent instructions, and Performance degradation can be minimized.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A processor according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a processor according to an embodiment of the present invention. In FIG. 1, 1 is an instruction storage device for storing instructions, 2 is an instruction reading device for reading out instructions, 3 is an instruction temporary storage device for temporarily storing a plurality of read instructions, and 4 is an instruction for decoding instructions. Decoding device, 5 is an execution control device for allocating the decoded instruction to the execution device, 6 is an addition / subtraction device for performing addition or subtraction, 7 is a high speed multiplication / division device for performing multiplication or division, and 8 is a small speed division for performing division. A device, 9 is a data storage device for storing data. The instruction reading device 2, the instruction decoding device 4, the execution control device 5, the addition / subtraction device 6, the high speed multiplication / division device 7, and the low speed division device 8 operate in pipeline, and the instruction reading device 2 and the addition / subtraction device 6 perform processing in one machine cycle. The instruction decoding device 4 and the execution control device 5 perform the processing in parallel in one machine cycle, and the high speed multiplication / division device 7 performs the multiplication in one machine cycle, and the division is performed by the iterative calculation of multiplication in four machine cycles. The division device 8 divides by 8
Do it in a machine cycle.

The operation of the processor configured as described above will be described below.

The instruction reading device 2 temporarily stores the instructions stored in the instruction storage device 1 together with a plurality of subsequent instructions in the sequential read instruction temporary storage device 3 every machine cycle. The instruction temporary storage device 3 stores a plurality of unexecuted consecutive instructions, and the executed instructions are removed.
The instruction decoding device 4 decodes the instruction stored in the instruction temporary storage device 3. The execution control device 5 assigns an addition instruction or a subtraction instruction to the addition / subtraction device 6, a multiplication instruction to the high speed multiplication / division device 7, and a division instruction to the high speed multiplication / division device 7 or the low speed division device 8. The instruction decoder 4 and the execution controller 5 perform processing in parallel in one machine cycle. The adder / subtractor 6 adds or subtracts the instructions assigned by the execution controller 5 in one machine cycle. Similarly, the high speed multiplication / division device 7 performs multiplication or division, but the multiplication is performed in one machine cycle and the division is performed in four machine cycles. The low speed division device 8 performs division in eight machine cycles.

The execution control device 5 allocates the division instruction to the high speed multiplication / division device 7 or the low speed division device 8, and determines which one to allocate by using a plurality of subsequent instructions stored in the instruction temporary storage device 3. When there is no multiplication instruction during the following four machine cycles, the division instruction is assigned to the high speed multiplication / division device 7. When there is a multiplication instruction during the following four machine cycles, the division instruction is assigned to the low speed division device 8 in order to avoid the multiplication instruction from being kept waiting for the processing due to the division execution. However, if the subsequent multiplication instruction uses the decoded result of the division instruction, or if the slow division device 8 is already performing division, the division instruction is added to the fast multiplication / division device 7.
Assign to. The operations performed by the adder / subtractor 6, the high-speed multiplier / divider 7, and the low-speed divider 8 are performed on the data stored in the data storage device 9, and the operation result is stored in the data storage device 9.

FIG. 2 shows a pipeline state diagram from instruction decoding to execution in a conventional processor in the case where division, multiplication, division, multiplication and instructions follow. However, it is assumed that the data used for the calculation to be executed is stored in the data storage device 9 at the start of the calculation.

As described above, according to the processor of this embodiment, the execution control device 5 allocates the division instruction to either the high speed multiplication / division device 7 or the low speed division device 8 by using the subsequent multiplication instruction. Subsequent multiplication instructions can be prevented from waiting for processing due to division execution, and the performance degradation of the processor can be minimized.

Although the processor of this embodiment requires the low-speed multiplication / division device 8 in addition to the high-speed multiplication / division device 7, the low-speed multiplication / division device 8 can be constituted by a small-scale circuit having a reduced bit width. Therefore, the circuit scale of the entire processor does not increase.

[0018]

As described above, according to the present invention, by providing the execution control device for allocating the instruction having the slow processing speed to the high-speed execution device or the low-speed execution device by using the plurality of subsequent instructions, The performance degradation of the processor due to slow instructions can be minimized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor according to a first embodiment of the present invention.

FIG. 2 is a pipeline state diagram in the same embodiment.

FIG. 3 is a block diagram of a conventional processor

FIG. 4 is a pipeline state diagram of a conventional processor.

[Explanation of symbols]

 1 instruction storage device 2 instruction reading device 3 instruction temporary storage device 4 instruction decoding device 5 execution control device 6 addition / subtraction device 7 high speed multiplication / division device 8 low speed division device 9 data storage device

Claims (2)

[Claims] 1. A plurality of execution devices having different execution speeds for processing a plurality of same-type instructions, an instruction reading device for reading a plurality of instructions, and a plurality of instructions read by the instruction reading device temporarily. For temporarily storing an instruction, an instruction decoder for decoding an instruction stored in the instruction temporary storage, and a plurality of instructions stored in the instruction temporary storage for decoding by the instruction decoder An execution control unit that assigns the generated instructions to any of the plurality of execution units. 2. A processor comprising a plurality of execution units as claimed in claim 1 and a multiplication / division unit for performing multiplication or division and a division unit for division.