JPH0512436A - Image processor - Google Patents

Abstract

PURPOSE:To execute an image processing with the arbitrary edge sharpness of an operator by transforming attention picture element data and peripheral picture element data to be supplied by using a transformation coefficient, and adding the respective transformed pixel data. CONSTITUTION:The picture element data inputted to a flip-flop 10 are held for one clock, inputted to a transformation RAM 20 as image data ID00 and simultaneously inputted to a flip-flop 13 as well. In this case, transformation RAM 20-28 execute data transformation at the value of respectively written filtering coefficients according to a fixed rule, and image data ID00-ID22 inputted to the transformation RAM 20-28 are respectively outputted to and adder part 5 as transformed data CD00-CD22. The adder part 5 calculates the total of the inputted transformed data CD00-CD22 and outputs a filtering process signal ODAT to an output device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for various document images having different characteristics and performing optimum filtering processing on each image.

[0002]

2. Description of the Related Art Generally, when an image is digitally read by using a CCD sensor or the like, a filtering process is usually performed for the purpose of noise removal or edge sharpening. Here, the noise is various other than quantization noise when digitizing an image, such as stains adhered to a manuscript or a manuscript table, and varies depending on the manuscript. The sharpness of the image is also different in the printed document and the pencil manuscript, and is different depending on the manuscript as well as noise. As described above, with respect to the noise and the sharpness of the edge which are different depending on the original document, conventionally, only the processing by one type of filtering area or switching between several types of filtering areas is performed, so that the noise is sufficiently removed depending on the original. There was a problem that it was not done or the edge was not sharpened sufficiently.

[0003]

As described above, in general document manuscripts, the sharpness of the edges of characters and diagrams and the superimposed state of noise are different for each manuscript. Noise removal by simply applying a unique linear filtering process to these manuscripts,
The edges cannot be sharpened sufficiently. Further, since the sharpness of the edge in the unique linear filtering process is uniquely determined, there is a problem that the image cannot be processed to have the sharpness of the edge that the operator likes.

Therefore, it is an object of the present invention to provide an image processing apparatus capable of performing image processing with the sharpness of the edge arbitrarily specified by the operator.

[0005]

An image processing apparatus according to a first invention supplies target pixel data in an image to be processed and peripheral pixel data in a predetermined matrix area including the target pixel data. The supply means, the selection means for selecting the conversion coefficient for the pixel data of interest and the peripheral pixel data supplied by the supply means, and the conversion coefficient selected by the selection means are used to supply the attention from the supply means. It is provided with conversion means for converting pixel data and peripheral pixel data, and addition means for adding each pixel data converted by this conversion means.

An image processing apparatus according to a second aspect of the present invention includes a supply means for supplying the pixel data of interest in the image to be processed and peripheral pixel data in a predetermined matrix area containing the pixel data of interest, and the matrix. Selection means for selecting the size of the area, storage means for storing the conversion coefficient of each pixel unit in the matrix area selected by the selection means, and the storage for the matrix area selected by the selection means Conversion means for converting the pixel data of interest supplied from the supply means and peripheral pixel data using the conversion coefficient read from the supply means, and addition means for adding each pixel data converted by the conversion means. It is equipped with.

[0007]

According to the first aspect of the invention, the image processing apparatus supplies the target pixel data in the image to be processed and the peripheral pixel data in a predetermined matrix area including the target pixel data, and supplies the target pixel to be supplied. A conversion coefficient for the data and the peripheral pixel data is selected, the pixel data of interest and the peripheral pixel data supplied using the conversion coefficient are converted, and the converted respective pixel data are added. .

The image processing apparatus according to the second invention supplies the pixel data of interest in the image to be processed and the peripheral pixel data in a predetermined matrix region containing the pixel data of interest, and the size of the matrix region is increased. Selection, the conversion coefficient for each pixel for the selected matrix area is read from the storage unit, the pixel data of interest and the peripheral pixel data supplied using this conversion coefficient are converted, and each converted pixel is converted. The data is added.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

The image processing apparatus according to the present embodiment inputs the image information read by a reading device such as an image scanner as digital data of 8 bits per pixel, and linearly by a preset filtering coefficient. After filtering processing, gradation processing suitable for an output device such as a printer is performed and the result is output to the output device.

FIG. 2 shows a schematic configuration of an image processing apparatus according to one embodiment. That is, the image processing device
A CPU 1 that controls the entire control, a filtering coefficient instruction unit 2a that the operator instructs the filtering process, and a filtering region instruction unit 2b that the operator instructs to change the region that is the filtering process target due to small and large characters. A control program for controlling noise depending on the original or sharpness of an arbitrary edge, a plurality of filtering coefficient groups selected by the filtering coefficient instructing section 2a, and a filtering area instructing section 2b. RO storing a plurality of filtering coefficient groups in a matrix area
The filtering processing unit 4 is configured to perform a filtering process using M3, the pixel data of interest, and its surrounding pixel data. The matrix area stored in the ROM 3 includes the number of pixels of 3 × 3, 5 × 5, 7 × 7, etc., with the pixel of interest at the center.

FIG. 1 shows the configuration of the filtering processing unit 4, which includes flip-flops 10 to 18 and a conversion RA.
It is comprised from M20-28 and the addition part 5.

That is, ID0 is an image bus for inputting image data read by a scanner (not shown) in synchronization with a predetermined clock (not shown). ID1 is I
An image bus for inputting image data obtained by delaying the image data of D0 by one line with a line buffer (not shown). ID2 is
This is an image bus for inputting image data obtained by delaying image data of ID0 by two lines by a line buffer (not shown).

The flip-flops 10 to 18 hold image data for one clock in synchronization with a predetermined image clock. 1 out of 9 flip-flops 10-18
Nine image data held between clocks (ID22 to ID
00) is the image data to be filtered,
The spatial arrangement is as shown in FIG. Here, the pixel of interest is ID11, and ID11 is the target pixel to be filtered.

The nine conversion RAMs 20 to 28 perform data conversion of each of the nine image data (ID22 to ID00) according to a certain rule.

Conversion RAM 2 for converting the pixel ID 11 of interest
4 has a structure of 256 × 21 bits, and the data format is MSB (most significant bit: bit 2) as shown in FIG.
0) is a sign bit, lower 8 bits (bit 7 to bit 0) are decimal bits, and upper 11 bits (bit 19 to bit 8) are positive bits.

Conversion RAMs 20 to 23, 25 to 25 for neighboring pixels
28 has a structure of 256 × 17 bits and the data format is MSB (most significant bit: bit 1) as shown in FIG.
6) is a sign bit, the lower 8 bits (bit 7 to bit 0) are decimal bits, and the upper 8 bits (bit 15 to bit 8) are positive bits.

The data in the conversion RAMs 20 to 28 is written by a control unit (not shown) via a system bus (not shown).

The adder 5 calculates the total of nine pieces of conversion data (CD22 to CD00) converted by the conversion RAMs 20 to 28, and outputs the filtering processing signal ODAT to the output device.

FIG. 6 shows a schematic structure of the adder unit 5, which is composed of eight adders 40 to 47 and an overflow / underflow processing circuit (OUPU) 48 for processing overflow / underflow. ing. The adders 40 to 43 are 17-bit adders (ADDE
R), the adders 44 and 45 are 18-bit adders, the adder 46 is a 19-bit adder, and the adder 47 is a 21-bit adder.

The operation of the above arrangement will be described below.

First, the image data G read by a scanner (not shown) is input to the flip-flop 10 via the image bus ID0 in synchronization with a predetermined clock (not shown). Similarly, the image data G is delayed by one line in a line buffer (not shown) and input to the flip-flop 11 via the image bus ID1. Further, the image data G is delayed by two lines by a line buffer (not shown) and input to the flip-flop 12 via the image bus ID2.

The flip-flops 10-18 hold the image data G for one clock in synchronization with the clock K.

That is, the image data G input to the flip-flop 10 is held by the flip-flop 10 for one clock and converted as image data ID00 into the conversion RAM 2
It is input to 0 and is also input to the flip-flop 13. Image data I input to the flip-flop 13
D00 is the image data ID01 which is held for one clock.
Is input to the conversion RAM 23 and is also input to the flip-flop 16 at the same time. The image data ID01 input to the flip-flop 16 is held for one clock and input to the conversion RAM 26 as image data ID02.

Flip-flop 11 delayed by one line
The image data G input to the image data G is input to the image data ID10, ID from the flip-flops 11, 14, 17 as described above.
11 and ID12, respectively, and converted RAM2
1, 24, 27 are input.

The flip-flop 12 is delayed by two lines.
Similarly, the image data G input to the image data G from the flip-flops 12, 15, and 18 are image data ID20, ID21,
Output as ID22 and convert RAM22,2
5, 28 are input.

Here, in the conversion RAMs 20 to 28, the filtering coefficient is designated in advance by the operator. Specifically, when the operator gives an instruction from the filtering coefficient instructing section 2a of the operating section 2, the CPU 1 executes R according to the instruction content.
The values of the filtering coefficients stored in advance in the OM 3 are read out, and the conversion RAMs 20 to 2 of the filtering processing unit 4 are read.
8 is to be written.

That is, the conversion RAMs 20 to 28 are
The values of the filtering coefficients written in each are adapted to perform data conversion in accordance with a certain rule, and the image data (I
D22 to ID00 are conversion data (CD22).
~ CD00) is output to the addition unit 5.

The adder 5 receives the converted data (CD
22 to CD00) and the filtering processing signal ODAT is output to the output device.
That is, in FIG. 6, converted data CD00, CD0
1 is input to the adder 40, is added, and is input to the adder 44. The converted data CD02 and CD10 are added to the adder 41.
Is input to the adder 44 and added to
4 add each and output to the adder 46. Similarly, the conversion data are sequentially added two by two and input to the over / underflow processing circuit (OUPU) 48. When the total (ODAT) value of the input conversion data is "0 to 255", the OUPU 48 outputs the same as the filtering process signal ODAT to the output device.
Further, the OUPU 48 determines whether the total value (ODAT) of the input conversion data is “minus” or “256” or more, and if “minus”, the ODAT as the output value is forced. If it is processed to "0" and is "256" or more, the value of ODAT is forcibly processed to "255" and output to the output device as the filtering processing signal ODAT.

Next, the case of changing the area of the filtering processing range will be described.

FIG. 7 shows a (7 × 7) filtering area. In the figure, D00 to D66 are data values in the filtering area, and D33 is a pixel of interest. Also, K00 ~
K66 represents a filtering coefficient. The filtering process is expressed by the following formula.

D33 ′ = Kij × Dij dj · di Here, D33 ′ is the filtering result of the pixel of interest.

When changing the area, for example, changing (7 × 7) to (3 × 3), all the coefficients of the hatched area in the filtering area in the figure are set to “0”. To do. Specifically, all the values in the conversion RAM in the hatched area are set to "0" as described above. further,
By changing the area of the conversion RAM where "0" is written, (4
It is also possible to carry out a filtering process of (× 4) or (5 × 5). In this way, the filtering area can be freely changed by changing the value (coefficient) of the conversion RAM outside the filtering area. That is, the operator operates the filtering area instruction unit 2b of the operation unit 2.
The CPU 1 writes the value (coefficient) of the conversion RAM in the outer region of the filtering area according to the instruction content.

As described above, according to the above embodiment,
In the filtering process for the purpose of noise removal and edge sharpening, an arbitrary filtering coefficient can be selected, so that noise removal process and edge enhancement process according to the characteristics of each original can be performed. Further, even when the document is processed according to the operator's preference, an arbitrary filtering coefficient can be selected, so that finer filtering processing can be performed according to the operator's preference. In this way, it is possible to process the image to the sharpness of the edge that suits the operator's preference.

Since the filtering area can be selected according to the size of the character, proper edge enhancement can be performed.
When changing the area of the filtering processing range in this way, the filtering area can be freely changed by changing the value (coefficient) of the conversion RAM to be written.

In the enlargement process using the interpolation process, the image type (edge portion) is identified by the feature information in the local area of the image information, and the intermediate density is removed from the edge portion. Therefore, the resolution of the edge portion can be improved. As a result, it is possible to obtain a high-quality enlarged / reduced image, which is the basis of various image processing, and improve the processing efficiency.

In the present invention, the image data in the filtering is calculated based on the amount corresponding to the reflectance of the image signal read by the reading means, that is, the image information. Processing based on a value converted into the logarithm of a reciprocal number or a converted signal in consideration of human visual characteristics may be performed.

[0038]

As described above in detail, according to the present invention, it is possible to provide an image processing apparatus capable of performing image processing with the sharpness of the edge arbitrarily specified by the operator.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a filtering processing unit in an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an image processing apparatus.

FIG. 3 is a diagram showing a spatial arrangement of image data.

FIG. 4 is a diagram showing a data format of a pixel of interest after data conversion.

FIG. 5 is a diagram showing a data format of neighboring pixels after data conversion.

FIG. 6 is a diagram showing a configuration of an addition unit.

FIG. 7 is a diagram for explaining variable filtering regions.
・

[Explanation of symbols]

1 ... CPU, 2 ... Operation unit, 2a ... Filtering coefficient instruction unit 2a, 2b ... Filtering region instruction unit 2b, 3 ...
ROM, 4 ... Filtering processing unit, 5 ... Addition unit, 1
0, 11, 12, 13, 14, 15, 16, 17, 18
... flip-flops, 20, 21, 22, 23, 24,
25, 26, 27, 28 ... Data conversion RAM, 40, 4
1, 42, 43, 44, 45, 46, 47 ... Adder, 4
8 ... Overflow / underflow processing circuit.

Claims (2)

[Claims] 1. A supply means for supplying the pixel data of interest in an image to be processed and peripheral pixel data in a predetermined matrix area containing the pixel data of interest, and the pixel data of interest supplied by the supply means. Selecting means for selecting a conversion coefficient for the peripheral pixel data; and converting means for converting the pixel data of interest supplied from the supplying means and the peripheral pixel data using the conversion coefficient selected by the selecting means, An image processing apparatus comprising: an addition unit that adds each pixel data converted by the conversion unit. 2. A supply means for supplying pixel data of interest in an image to be processed and peripheral pixel data in a predetermined matrix area containing the pixel data of interest, and a selection means for selecting the size of the matrix area. Storage means for storing the conversion coefficient of each pixel unit in the matrix area selected by the selection means, and the conversion coefficient read from the storage means for the matrix area selected by the selection means. And a conversion means for converting the pixel data of interest and the peripheral pixel data supplied from the supply means, and an addition means for adding each pixel data converted by the conversion means. Image processing device.