JPH0512202A - Dtack signal generation device for data processor - Google Patents

Abstract

PURPOSE:To supply the DTACK signal generation device of a data processor which can easily be equipped with CPU that can be operated at higher speed at low cost. CONSTITUTION:The DTACK signal generation device 34 has CPU 31 which can be changed and memories 32 and 33 connected to CPU 31. The device 34 is provided with dip switches 42, and 43, wait decision parts 46-48, and a DTACK signal generation block 49. The wait decision parts 46-48 store DTACK signal generation conditions fitted to plural kinds of CPU which can be equipped with a printer. The dip switches 42 and 43 select the DTACK signal generation condition fitted to CPU 31 equipped with the printer from the DTACK signal generation conditions stored in the wait decision parts 46-48. The DTACK signal generation block 49 outputs a DTACK signal based on the selected DTACK signal generation condition to CPU 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DTACK signal generator, and more particularly to a DTACK signal generator for a data processing device having a replaceable process unit and a storage unit connected thereto.

[0002]

2. Description of the Related Art A laser printer (an example of a data processing apparatus) is provided with a control unit for controlling its image processing operation. The control unit includes a CPU, ROM, RAM
And the like is included in the microcomputer.

When performing an access operation (that is, a read operation or a write operation) from the CPU to the ROM or RAM, a DTACK signal (Data Transfer Acknowlegement signal) is used as means for recognizing the completion time of the access operation.
Is used. The generation timing of the DTACK signal can be changed according to the access time of the memory. If the access time is slow, the generation timing is set late, and if the access time is fast, the generation timing is set fast. As a result, the CPU recognizes that the access to the memory has been completed. In such a control unit, time is usually managed based on the system clock. Therefore, the generation timing of the DTACK signal is also determined by counting the number of system clock pulses.

[0004]

In the conventional control unit, the old CPU may be replaced with a faster CPU. For example, instead of a CPU operating with a system clock of 10 MHz, 12 MHz or 16M
A CPU operating with a system clock of Hz may be adopted. Thus, if a CPU that operates with a system clock with a higher frequency is adopted, the processing speed is improved, but on the other hand, there is a problem of consistency in access time between the memory and the CPU.

In such a case, conventionally, an overall design change is made to ensure consistency between the CPU and the memory. However, with this method, it is necessary to make a large design change when adopting a new CPU, and a CP of higher speed is required.
The additional cost of adopting U is high.

An object of the present invention is to provide a DTACK signal generating device for a data processing device, in which process parts having different operating speeds can be easily installed at low cost.

[0007]

DTACK according to the present invention
The signal generating device is a DTACK signal generating device of a data processing device having a replaceable process unit and a storage unit connected to the process unit. This DTACK signal generation device includes a DTACK signal generation condition storage means, a selection means, and a DTACK signal output means.

The DTACK signal generation condition storage means is
It is means for storing DTACK signal generation conditions suitable for a plurality of types of process units that can be installed in a data processing device. The selecting means selects the DTACK signal generation condition stored in the DTACK signal generation condition storage means based on the DTACK signal generation condition and is suitable for the process unit equipped in the data processing device.
It is a means for selecting a signal generation condition. The DTACK signal output means is means for outputting the DTACK signal to the process section based on the DTACK signal generation condition selected by the selection means.

[0009]

In the DTACK signal generator according to the present invention, D
The TACK signal generation condition storage means stores a DTACK signal generation condition suitable for a plurality of types of process units that can be installed in the data processing device.

When the data processing apparatus is newly equipped with a process unit, the selecting unit selects the DTACK signal generating condition suitable for the process unit from the DTACK signal generating conditions stored in the DTACK signal generating condition storage unit. .. Then, the DTACK signal output unit outputs the DTACK signal to the process unit based on the DTACK signal generation condition selected by the selection unit during the operation of the data processing device.

In this case, the DTACK signal generation conditions suitable for a plurality of process units that can be equipped are stored in the DTACK signal generation condition storage means, and the DTACK signal generation conditions suitable for the equipped process unit are selected. Since it is selected by the means, even when a new process unit is equipped, an appropriate DTACK signal generation timing can be obtained only by the selection by the selecting means without making a general design change. As a result, a new process unit can be easily installed at low cost.

[0012]

FIG. 1 shows a laser printer to which an embodiment of the present invention is applied. An imaging unit 2 is arranged substantially in the center of a device body 1 of this laser printer. An optical unit 3 is arranged above the imaging unit 2, and a conveyance mechanism 5 including a fixing device 4 is arranged below the imaging unit 2. A paper feed cassette 6 is arranged below the transport mechanism 5 at the bottom of the apparatus body 1. At the downstream end of the transport mechanism 5, on the left side of the apparatus main body 1 in the drawing,
A paper discharge tray 7 is provided. This paper discharge tray 7
It can be folded as shown by the chain double-dashed line. When the paper discharge tray 7 is folded, the paper placing portion 8 provided above the optical unit 3 works effectively.

The imaging unit 2 comprises a photoconductor drum 10 and a developing device, a corona discharger, etc. arranged around the photoconductor drum 10. The optical unit 3 has a rotary polygon mirror 11 and a lens for irradiating the photosensitive drum 10 with laser light from a laser oscillator (not shown).

Further, an IC card 20 as an example of an external device is inserted in the bottom portion on the right side of the apparatus body 1 in the figure. The IC card 20 is inserted into the IC card insertion portion 12 provided in the apparatus main body 1, and is connected to the connector 13 provided on the back upper wall of the IC card insertion portion 12.

This laser printer has a control unit 30 as shown in FIG. The control unit 30 has a CPU 31.
, ROM 32, RAM 33, DTACK signal generator 34, and I / O port 3 for connecting an external device
5 and mainly. ROM32, RAM33,
The DTACK signal generator 34 and the I / O port 35 are
CPU 3 via address bus 36 and data bus 37
It is connected to 1.

The DTACK signal generator 34 includes a CPU 3
An address decoder 40 for identifying which of the ROM 32 and the RAM 33 is selected by 1, a weight determining block 41 for determining the number of weights,
ON / OFF according to the type of CPU 31 equipped
A pair of DIP switches 42 and 43, and a gate 4 for outputting the ON / OFF state of the DIP switches 42 and 43 to the bus side or stopping the output.
4 and.

The address decoder 40 receives the address data from the CPU 31, and determines which of the ROM 32 and the RAM 33 is designated. The address decoder 40 also outputs a weight number selection signal SW to the weight determination block 41 and a frequency read signal RF to the gate 44.

The wait decision block 41 receives a wait number selection signal SW from the address decoder 40 and the CPU 3
1 and the clock signal from 1. In addition, the weight determination block 41 is a CPU determined by the ON / OFF state of the DIP switches 42 and 43 via the data bus 37.
It receives 31 frequency states. The weight determination block 41 determines the generation timing of the DTACK signal based on those input signals, and outputs the DTACK signal to the CPU 31 at the determined timing.

The weight determination block 41, as shown in FIG. 3, is a selector 4 for selecting a weight determination unit described later.
Have five. In addition, the weight determination block 41
Weight determining units 46, 47, 4 for determining the number of weights corresponding to a plurality of types of CPUs 31 that can be installed.
Have eight. The weight determining unit 46 is for a CPU whose system clock is 10 MHz. Weight determination unit 4
7 is for a CPU with a system clock of 12 MHz. The weight determination unit 48 has a system clock of 16M.
It is for CPU of Hz.

Each weight determining unit 46, 47, 48 has a
The output of the selector 45 and the system clock are input. Then, the weight determining units 46, 47, 48
A weight number signal is output to the TACK signal generation block 49. The DTACK signal generation block 49 generates a DTACK signal at a timing according to the input weight number. The generated DTACK signal is the CPU 31
(Fig. 2).

The gate 44 is opened when receiving the frequency read signal RF, and the dip switches 42 and 43 are turned on.
The frequency characteristic of the CPU 31 represented in the / OFF state is output to the data bus 37 side.

Next, a setting method in the DTACK signal generator 34 in this embodiment will be described. When the system clock of the CPU 31 is 10 MHz, the dip switches 42 and 43 are set to the open (OFF) state. Also, the system clock of the CPU 31 is 1
In case of 2MHz, DIP switch 42 opens,
The dip switch 43 is set to the closed (ON) state. Furthermore, the system clock of the CPU 31 is 1
In the case of 6 MHz, the dip switch 42 is set to the closed state and the dip switch 43 is set to the open state. In this way, the DIP switches 42 and 43 are set according to the frequency of the system clock of the CPU 31.

For example, the CPU 31 that was set at the beginning of the development of the laser printer operated at the system clock of 10 MHz, but later it was set at 12 MHz or 1.
When the CPU operating at 6 MHz becomes available, the CPU 31 is replaced and the dip switches 42 and 43 are set to ON / OFF according to the new system clock frequency. That is, when the CPU 31 is improved, the high-performance CPU 31 can be equipped only by changing the setting state of the dip switches 42 and 43.

Next, the operation of the DTACK signal generator 34 will be described. The CPU 31 operates to operate the address bus 36.
When the address data designating a certain address of the ROM 32 or the RAM 33 is output to, the address signal is input to the address decoder 40. The address decoder 40 decodes the address signal and determines whether the processing target is the ROM 32 or the RAM 33. Then, the determination result is output to the selector 45 of the weight determination block 41 as the weight number selection signal SW. The address decoder 40 also includes a gate 44
A frequency read signal RF is output to. As a result, the gate 44 is opened and the O of the dip switches 42 and 43
A 2-bit high / low signal corresponding to the N / OFF state is output to the selector 45 of the wait decision block 41 via the data bus 37.

In the selector 45, the weight number selection signal S
Based on W and the state of the DIP switches 42 and 43, a signal indicating which of the ROM 32 and the RAM 33 is the processing target is output to the corresponding one of the weight determining units 46, 47 and 48. To do. One selected from the weight determining units 46, 47, 48 receives the system clock signal and the signal from the selector 45, and outputs a signal relating to the optimum number of weights to the DTACK generation block 49. DTA that received the output
The CK generation block 49 outputs the DTACK signal to the CPU 31 at the designated generation timing according to the designated weight number.

Table 1 shows an example of the number of weights designated in the above operation.

[0027]

[Table 1]

In the example of Table 1, in the case of the CPU 31 of 10 MHz, both the DIP switches 42 and 43 are OFF.
Set to state. And in this case,
When the ROM 32 is the processing target, the number of weights is "1", and when the RAM 33 is the processing target, the number of weights is "0". Similarly, the CPU 31
Is for 12MHz, the dip switch 42 is O
In the FF state, the dip switch 43 is set to the ON state, and the number of weights is set to "2" for ROM and "1" for RAM. In addition, CPU31 is 16MH
In the case of z, the dip switch 42 is turned on,
The dip switch 43 is set to the OFF state, and the number of weights is “4” for ROM and “2” for RAM.
Is set.

FIG. 4 shows an example of a timing chart regarding the RAM when the CPU 31 of 10 MHz is installed,
RA when 12 MHz CPU 31 is installed in FIG.
An example of a timing chart regarding M is shown respectively.
In both figures, CLK is a system clock signal, AS is an address strobe signal, and DA is a DTACK signal. The address strobe signal AS is a signal indicating that the memory address is valid, and here, it is L
Means the state is valid. Further, the L state of the DTACK signal DA means the completion of access.

In FIG. 4, the address strobe signal AS falls when the second pulse rises in the bus cycle BC of the clock signal CLK. Then, at the falling timing T1 of the fourth pulse, DTACK
The state of the signal DA1 is referred to. Since the DTACK signal DA1 is already in the L state at the timing T1,
At timing T1, it is immediately confirmed that the memory access is completed. Specifically, at timing T1, the weight determination block 41 outputs the DTACK signal to the CPU 31. As described above, when the CPU 31 of 10 MHz is used to write to or read from the RAM 33, the processing is performed in a no wait cycle.

On the other hand, the CPU 31 of 12 MHz is used for R
When accessing the AM 33, since the frequency of the clock signal CLK is high as shown in FIG. 5, the access time is set to be almost the same as when the CPU 31 of 10 MHz is used. Processing is performed. That is, here, when the second pulse rises in the bus cycle BC of the clock signal CLK,
Although the address strobe signal AS falls, when the state of the DTACK signal DA2 is referred to at the falling timing T2 of the third pulse, the DTACK signal DA2
Is still in the H state. Therefore, the wait state A is entered from the timing T2. Then, when the DTACK signal DA2 is referred to at the timing T2, the DT
Since the ACK signal DA2 is in the L state, it is determined that the access to the RAM 33 is completed at this timing T3. Specifically, at timing T3,
The weight determination block 41 sends DTAC to the CPU 31.
Output K signal. Thus, here, 1 weight
The cycle processing is performed, and the processing according to the access time of the RAM 33 is executed even if the frequency of the clock signal CLK increases.

The process for the ROM 32 and 16M
Although the description of the processing when the CPU 31 of Hz is used is omitted here, it is performed in the same manner as the above processing. As described above, in this embodiment, even if the CPU 31 having a different system clock frequency is used,
Just change the settings of DIP switches 42 and 43,
You can easily achieve the best system performance.

[Other Embodiments] (a) In the above embodiment, the DIP switches 42 and 4 are used.
Although the output of No. 3 is input to the weight determination block 41 via the gate 44 and the data bus 37, the outputs of the DIP switches 42 and 43 may be directly input to the weight determination block 41.

(B) Jumper switches may be used instead of the DIP switches 42 and 43. Further, the nonvolatile memory may be configured to store data indicating the type of the CPU 31, and the stored content may be used to perform processing in the weight determination block 41. When a non-volatile memory is used, data corresponding to the type of CPU may be manually recorded in the non-volatile memory through a key panel (not shown) for operating the laser printer.

(C) The present invention is not limited to a printer, and the present invention may be implemented using, for example, a copying machine or a facsimile.

[0036]

The DTACK signal generator according to the present invention stores the DTACK signal generation conditions suitable for a plurality of types of process units that can be installed in the data processing device, and is suitable for the process unit installed in the weight processing device. Since it is possible to select a different DTACK signal generation condition and output the DTACK signal based on the selection, it becomes possible to easily equip the process units having different operation speeds at low cost.

[Brief description of drawings]

FIG. 1 is a schematic vertical sectional view of a laser printer to which an embodiment of the present invention is applied.

FIG. 2 is a schematic block diagram of a control unit thereof.

FIG. 3 is a schematic block diagram of the weight determination block.

FIG. 4 is a timing chart showing an example of the wait cycle.

FIG. 5 is a timing chart showing another example of the wait cycle.

[Explanation of symbols]

 30 control part 31 CPU 32 ROM 33 RAM 34 DTACK signal generation device 40 address decoder 41 weight determination block 42, 43 DIP switch 45 selector 46, 47, 48 weight determination part 49 DTACK signal generation block

Claims (1)

Claim: What is claimed is: 1. A DT of a data processing device having a replaceable process unit and a storage unit connected to the process unit.
An ACK signal generation device, which stores DTACK signal generation condition storage means for storing DTACK signal generation conditions suitable for a plurality of types of process units that can be installed in the data processing device, and stored in the DTACK signal generation condition storage device. Selection means for selecting a DTACK signal generation condition suitable for a process unit equipped in the data processing device from the DTACK signal generation conditions existing in the data processing device; and a TACK signal based on the DTACK signal generation condition selected by the selection means. DTA output to process unit
DTA of data processing device including CK signal output means
CK signal generator.