JPH05121729A - Semiconductor device having misfet controlled thyristor - Google Patents

Abstract

PURPOSE:To increase the controllable current value while avoiding latch and lowering ON resistance in a semiconductor device having MOS controlled thyristor. CONSTITUTION:A cathode layer 7 and a floating cathode layer 2 formed inside a p type base layer 3 are a shallow and a deep diffused layer, respectively, and a base electrode 12 is arranged on the p type base layer 3. In such a constitution, a thyristor is rapidly turned on by a hole current implanted from the base electrode 12 to lessen the on-resistance so that the hole current may be prevented from reaching the cathode layer 7 by the deep floating layer 2 thereby avoiding occurrence of latch up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to control of an electric motor,
The present invention relates to a power semiconductor device capable of controlling a large current under a high breakdown voltage used when switching an exchange or driving a flat panel display.

[0002]

2. Description of the Related Art A power semiconductor capable of controlling a large current under a high breakdown voltage consumes less power and can be integrated into an IC to reduce the number of parts such as a control device. Has merits. FIG. 13 shows an emitter-switched thyristor (EST) which is one of the voltage-driven MOS gate thyristors utilizing the electric field effect among such power semiconductors. Further, FIG. 14 shows an equivalent circuit of this thyristor. This thyristor has ap ⁺ type anode layer 5 in which an anode electrode 11 is connected to the back surface of an n ⁻ type base layer 4.
Is formed, and the p-type base layer 3 is formed on the surface of the n ⁻ -type base layer 4 facing the anode layer 5. An n ⁺ type cathode layer 7 and an n ⁺ type floating cathode layer 2 independent of the cathode layer 7 are formed in the p type base layer 3. A cathode electrode is connected from the cathode layer 7 to the p-type base layer 3, and a gate electrode 1 is provided from the cathode layer 7 to the floating cathode layer 2 with an insulating film 15 interposed therebetween. Therefore, the floating cathode layer 2 and the cathode layer 7 are connected by the n-channel MOS 21 having the p-type base layer 3 between these layers as a channel region.

In this device, as shown in FIG.
The anode layer 5, the n ⁻ type base layer 4, and the p type base layer 3 form a PNP transistor 31, and the n ⁻ type base layer 4, the p type base layer 3 and the floating cathode layer 2 are formed. Form an NPN transistor 32. Therefore, when the MOS 21 connecting the floating cathode layer 2 and the cathode layer 7 is turned on, the thyristor 41 is formed between the cathode layer 2 and the anode layer 5 by the transistors 31 and 32. The feature of this device is that the cathode layer 2 and the floating cathode layer 2 can be separated by lowering the gate potential Vg applied to the gate electrode 1, and the thyristor can be easily turned off. On the other hand, in order to turn on the thyristor 41, it is necessary to reduce the impurity concentration of the p-type base layer 3 and increase the resistance 26 at the connecting portion between the cathode electrode 10 and the p-type base layer 3. However, if the impurity concentration of the p-type base layer 3 is reduced, the breakdown voltage is reduced due to punch-through, so it is difficult to reduce the impurity concentration of the p-type base layer 3. Therefore, it is difficult to turn on the thyristor 41 in this device.

FIG. 15 shows the structure of a device having a thyristor which improves this point, and FIG. 16 shows its equivalent circuit. In addition to the device described with reference to FIG. 13, this device includes the floating cathode layer 2 to the p-type base layer 3
The second gate electrode 16 is provided via the insulating layer 15 to the n ⁻ type base layer 4 via the insulating layer 15. Since the gate potential Vg is applied to the second gate electrode 16 similarly to the gate electrode 1, the MOS 22 constituted by the gate electrode 16 is turned on at the same time as the MOS 21. Therefore, when the device is activated, an electron current flows from the cathode layer 7 to the n ⁻ type base layer 4 via the floating cathode layer 2. As a result, electrons are injected into the n ⁻ type base layer 4, and this triggers the main thyristor 42 to be easily turned on. Of course, this device also has an advantage that it can be easily turned off by lowering the gate potential Vg applied to the gate electrode 1 similarly to the device shown in FIG.

[0005]

A semiconductor device having such a MOS-controlled thyristor element has a low on-state voltage and can be easily turned off, so that high-speed switching is possible. Therefore, it is attracting attention as a power semiconductor. ing. And to further expand the range of application of this device, the controllable current value is increased and the on-voltage is lowered,
Further, it is necessary to improve the on-breakdown voltage and solve the problems such as realizing a high-side switch type.

First, in order to increase the controllable current value, latch-up in which the thyristor 43 parasitic on the main thyristors 41 and 42 of the device shown in FIGS. 13 and 15 is turned on is prevented. There is a need. The parasitic thyristor 43 includes the PNP transistor 36 including the anode layer 5, the n ⁻ -type base layer 4 and the p-type base layer 3 and the n ⁻ -type base layer 4, the p-type base layer 3 and the cathode layer 7. It is a thyristor composed of an NPN transistor 37. When the parasitic thyristor 43 is turned on, the latch-up state occurs, and the gate potential Vg
It is impossible to turn off the device even if the value is decreased. Therefore, the current value to be controlled is the parasitic thyristor 4
It must be stopped in the range where 3 is not turned on.

Further, in the device shown in FIG. 15, the on-resistance is low, but in the initial state, the electron current is n ^−.
Type base layer 4 is injected into the conductivity-modulated IGB
It is the T mode. When the current increases, the resistance 26
As a result, the transistor 32 is turned on and the mode shifts to a low resistance thyristor mode. Therefore, in order to further reduce the on-resistance, it is desirable to shift to the thyristor mode as early as possible.

When the thyristors 41 and 42 are turned on, a large amount of electrons flow in the curved end portion 17 of the p-type base layer 3 to which the maximum electric field is applied. These electrons are more likely to cause avalanche breakdown than holes, and the end portion 17
In addition to the electric field concentration, the breakdown voltage is lowered and the element is destroyed accordingly. Therefore, in order to improve the on-breakdown voltage of this device, it is necessary to relax the electric field concentration at the end portion 17.

Further, the MOS 21 for controlling the thyristors 41 and 42 is for applying a gate potential Vg of several volts to the cathode electrode 10 (low side switch type).
Is common. On the other hand, there may be a case where the potential of the anode electrode 11 is used as the reference potential of the gate potential Vg (high-side switch type), and in such a case, the conductivity type of each layer and the position of the electrode are reversed to deal with it. Is common. However, when a high-side switch type element is formed on a semiconductor substrate of the same conductivity type such as an IC, it is impossible to reverse the conductivity type of each layer and the positions of the electrodes, and thus the thyristors 41 and 42 cannot be reversed. It was not possible to use such a structure. Therefore, in order to expand the applicable range of the EST type thyristor element, it is necessary to realize a high side switch type element that can be formed on a semiconductor substrate of the same conductivity type.

Therefore, in the present invention, in view of the above problems, the controllable current value can be increased, the ON voltage can be reduced, and the ON breakdown voltage can be improved.
It is an object of the present invention to realize a semiconductor device having a thyristor element with a wide range of application that can form a high side switch type on a substrate of the same conductivity type.

[0011]

In order to solve the above problems, in the present invention, first, in order to prevent latch-up, a shallow cathode region and a deep floating cathode region are formed. That is, in the semiconductor device having the MISFET controlled thyristor according to the present invention, the first conductivity type is provided on the second conductivity type base region at a position facing the first conductivity type anode region to which the anode potential is applied. At least a second conductive type cathode region formed in the first conductive type base region and having a cathode potential applied together with the first conductive type base region. M of 1
A semiconductor device in which a floating cathode region of the second conductivity type connected by an ISFET is independently formed between a cathode region and an anode region in a base region of the first conductivity type, and the cathode region is the second conductivity type. Is a shallow diffusion layer formed on the surface of the base region of the second conductivity type, and the floating cathode region is a deep diffusion layer formed up to near the bottom of the second conductivity type base region.

Further, the base region of the first conductivity type is provided on the second conductivity type base region having a deep floating cathode region at a position facing the anode region of the first conductivity type to which the anode potential is applied. At least a second conductivity type floating cathode region;
A first conductive type second base region connected to the first conductive type base region by the conductive type base contact region, a cathode potential is applied together with the base contact region, and the floating cathode region is connected to the first MISFET. A MIS having a second conductivity type cathode region and a first base region sequentially stacked from the bottom.
It also includes a semiconductor device having a FET-controlled thyristor.

Further, at least a first-conductivity-type base region is provided on the second-conductivity-type base region at a position facing the first-conductivity-type anode region to which the anode potential is applied. A second conductivity type floating cathode region formed in the conductivity type base region; a first conductivity type second base region formed in the floating cathode region; and a second conductivity type floating cathode region formed in the second base region. Two
A semiconductor having a MISFET control type thyristor, which comprises at least a second conductivity type cathode region to which a cathode potential is applied together with a base region, and a first MISFET connecting the cathode region and the floating cathode region. Including equipment. Further, in these devices, it is desirable that the cathode region be covered with a first conductivity type guard layer formed of a high-concentration impurity diffusion layer.

Further, a semiconductor device having a high-side switch type MISFET control type thyristor device on a semiconductor substrate of the same conductivity type is a first conductivity type to which an anode potential is applied in a base region of the second conductivity type. At least a first conductivity type base region and a second conductivity type cathode region formed in the first conductivity type base region to which a cathode potential is applied. Realization by forming a first conductivity type floating anode region connected to the region by the first MISFET on a second conductivity type base region between the anode region and the first conductivity type base region. You can

In order to reduce the on-resistance, the second
On the conductive type base region, at a position facing the first conductive type anode region to which the anode potential is applied, a first conductive type base region, and a cathode formed in the first conductive type base region. At least a second conductivity type cathode region to which a potential is applied together with a first conductivity type base region, and a second conductivity type floating cathode region connected to this cathode region by the first MISFET is the first
In a semiconductor device having a MISFET control type thyristor independently formed between a cathode region and an anode region in a conductivity type base region, a floating cathode region on a first conductivity type base region is opposite to a cathode region. On the side, it is desirable to install a hole current injection means, and the MI having the above-mentioned floating cathode region.
The same applies to a semiconductor device having an SFET control type thyristor. Further, in the semiconductor device having the MISFET control type thyristor having the above floating anode region, it is effective to install the hole current injection means on the floating anode region side on the first conductivity type base region.

As the hole current injecting means, a base electrode connected on the first conductivity type base region can be used, and a gate potential applied to the gate electrode of the first MISFET is applied to this base electrode. It is desirable to apply.

It is also effective to use a second MISFET for injecting a hole current from the anode region to the first base region as the hole current injecting means.

In order to improve the on-state breakdown voltage, a buried layer of the first conductivity type is formed at least inside the second conductivity type base region below the end portion of the first conductivity type base region facing the anode region. Is preferably formed, and it is also effective to form an offset layer of a low-concentration impurity diffusion layer so as to surround at least the end portion of the first conductivity type base region facing the anode region.

[0019]

In the above, by forming a deep floating cathode region on the anode region side of the cathode region with respect to the shallow cathode region, it is possible to prevent the parasitic thyristor involved in the cathode region from turning on and prevent a controllable current value. It is possible to increase. That is, by making the floating cathode region deep, it is possible to prevent the hole current in the first-conductivity-type base region from reaching the vicinity of the cathode region, and by forming the cathode region shallow, the vicinity of this cathode region can be prevented. By substantially increasing the thickness of the first conductivity type base region, it is possible to prevent electrons from flowing out to the second conductivity type base region. Therefore, it is possible to prevent the parasitic thyristor having this cathode region as a cathode from being turned on. Therefore, the current can be controlled by the thyristor having the floating cathode region as the cathode, and the thyristor can be easily turned off by the first MISFET.

In addition, a second conductivity type floating cathode region is applied to the first conductivity type base region to which the cathode potential is applied via the base contact layer, and a first conductivity type to which the cathode potential is applied by the base contact region. The second conductive type base region, the base contact region, and the floating cathode region to which the cathode potential is applied and the second conductive type cathode region connected by the first MISFET may be sequentially stacked from below. In this case, in the ON state, the cathode region and the first MI are
A current (electron current) flows from the floating cathode region connected by the SFET, while a hole current flows in the first conductivity type base region below the floating cathode region. Therefore, the second base region in which the cathode region is formed is connected to the first conductivity type base region only by the base contact region having a small contact area, and a hole current almost flows through the second base region. Absent. Therefore, the potential of the second base region is fixed, the parasitic thyristor having the cathode region as the cathode does not turn on, and latch-up does not occur.

A second conductivity type floating cathode region is formed in the first conductivity type base region, a first conductivity type second base region is further formed in the floating cathode region, and the second conductivity type floating cathode region is formed. It is possible to separate the second base region and the first conductivity type base region by forming the second conductivity type cathode region to which the cathode potential is applied in the two base regions. Therefore, in the device having such a configuration, the hole current does not flow in the second base region, the parasitic thyristor does not turn on, and latch-up can be prevented.

Further, by covering the cathode region with the first conductive type guard layer formed of the high-concentration impurity diffusion layer, the flow of electrons from the cathode region can be prevented. On the other hand, by providing the guard layer around the cathode region, the periphery of the floating cathode region through which the electron current flows can be the base region of the impurity diffusion layer having a relatively low concentration, so that the on-resistance can be reduced.

Further, a first conductivity type anode region is formed on the second conductivity type base region at a position where the second conductivity type cathode region faces the first conductivity type base region formed in the region. By forming the first conductive type floating anode region connected to the anode region by the first MISFET, a high-side switch type MISFET controlled thyristor can be realized on a semiconductor substrate of the same conductive type. In this thyristor, the thyristor is configured with the floating anode region as an anode, and the first MISFET can easily turn off the thyristor. That is, this first
In the MISFET, the thyristor can be easily turned off by raising the gate potential above the anode potential.

Further, by providing the hole current injecting means on the base region of the first conductivity type, the thyristor having the floating cathode region as a cathode can be turned on at an early stage to reduce the on-resistance. .. That is, by injecting a hole current, an electron current flows from the floating cathode region in response to this.
Since the thyristor is turned on, the hole current triggers and the thyristor can be turned on early. By disposing this hole current injection means on the side opposite to the cathode region with respect to the floating cathode region on the first conductivity type base region, the hole current reaching the vicinity of the cathode region is reduced and the parasitic thyristor is turned on. It is also possible to prevent the situation.

As the hole current injecting means, a base electrode connected to the first conductivity type base region can be used. By applying a high potential with respect to the cathode potential to this base electrode, the hole current can be injected. Can be injected. Further, as the potential applied to the base electrode, it is also possible to use the gate potential applied to the gate electrode of the first MISFET which is held at a potential higher than the cathode potential when the thyristor is in the ON state, and the control circuit Can be simplified. When the gate potential is applied to the base electrode, it is desirable to connect the base electrode via a resistor in order to prevent the gate potential from decreasing.

On the other hand, as a hole current injection means, a second MI is formed so as to connect the anode region to the first base region.
It is also possible to inject a hole current from the anode region by forming an SFET and turning on this second MISFET. The second MISFET may directly connect the first base region from the anode region, or may connect the first base region via the floating anode region. Further, by forming the second MISFET so as to be connected to the floating cathode region of the first base region on the side opposite to the cathode region, an increase in hole current in the vicinity of the cathode region is suppressed, and the parasitic thyristor is prevented. It is also possible to prevent it from turning on.

Further, when the thyristor is turned on, an electric field is concentrated on the end portion of the first conductivity type base layer. On the other hand, at least inside the second conductive type base region, which is below at least the end of the first conductive type base region facing the anode region,
By forming the buried layer of the first conductivity type, the depletion layer extending from the base region of the first conductivity type is formed along the buried layer to increase the curvature of the equipotential line at the end, and It is possible to reduce the concentration of the electric field. Therefore, it is possible to improve the withstand voltage performance at the time of turning on.

As a means for relaxing the concentration of the electric field, it is also effective to form an offset layer of a low-concentration impurity diffusion layer in contact with at least the end of the first conductivity type base region facing the anode region. In this case, the concentration of the electric field can be relaxed by spreading the depletion layer in the offset layer having a low concentration.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows an MO according to the first embodiment.
1 shows a cross section of a semiconductor device having an S-controlled thyristor element. The device of the present example has substantially the same configuration as the semiconductor device having the conventional thyristor element described above with reference to FIGS. 13 and 15, and the p ^- type semiconductor device having the anode electrode 11 connected to the back surface of the n ⁻ -type base layer 4. ⁺ Type anode layer 5, n ⁻
P-type base layer 3 formed on the surface of the mold-type base layer 4,
The n ⁺ type cathode layer 7 formed in the p type base layer 3, and the p type base layer 3 independent of the cathode layer 7.
An n ⁺ type floating cathode layer 2 formed inside,
And an n-channel MOS 21 that connects the cathode layer 7 and the floating cathode layer 2 to each other. And
In the device of this example, the p ⁺ type anode layer 5 to which the anode electrode 11 is connected is also formed on the surface of the n ⁻ type base layer 4. The respective configurations are the same as those of the conventional thyristor described above, and the same reference numerals are given to omit the description.

A point to be noted in the device of this example is that the cathode layer 7 is a shallow diffusion layer and the floating cathode layer 2 is a deep diffusion layer. Further, the base electrode 12 is provided on the p-type base layer 3, and the base electrode 12 is connected to the gate electrode 1 via the resistor 27.

In the device of this example, when the gate potential Vg is applied to the gate electrode 1 with a bias voltage applied between the cathode electrode 10 and the anode electrode 11, the cathode layer 7 and the floating cathode layer 2 are brought into conduction. Become. At the same time, a hole current is injected from the base electrode 12 to which the gate potential Vg is connected via the resistor 27, electrons flow out from the floating cathode layer 2 in the floating state, and the thyristor using this as a cathode is turned on. To do. This thyristor includes a PNP transistor including an anode layer 5, an n ⁻ -type base layer 4 and a p-type base layer 3, and an NPN transistor including an n ⁻ -type base layer 4, a p-type base layer 3 and a floating cathode layer 2. This is a main thyristor, and by injecting a hole current into the vicinity of the floating cathode layer 2 by the base electrode 12, the main thyristor is turned on early.

On the other hand, in order to prevent latch-up,
PNP transistor with anode layer 5, n ⁻ -type base layer 4 and p-type base layer 3, and NPN with n ⁻ -type base layer 4, p-type base layer 3 and cathode layer 7.
It is necessary to prevent the parasitic thyristor formed by the transistor from being turned on. For this reason, in this example, the base electrode 12 is provided on the side of the anode layer 5 opposite to the cathode layer 7 with respect to the floating cathode layer 2, and the cathode layer 7 and the base electrode 12 as well as the cathode layer 7 and the anode layer 5 are provided. Secure a distance to the cathode layer 7
It suppresses the hole current that reaches. Furthermore, by forming the floating cathode layer 2 by a deep diffusion layer, the cross-sectional area of the p-type base layer 3 reaching the cathode layer 7 from the base electrode 12 is narrowed, and the hole current flowing in the vicinity of the cathode layer 7 is reduced. It's suppressed.

In addition, by forming the cathode layer 7 with a shallow diffusion layer, an effective p-type base layer thickness is secured and electrons are prevented from flowing out to the n ⁻ -type base layer 4. There is. Therefore, in the device of this example, it is difficult for the parasitic thyristor to turn on, the occurrence of latch-up is suppressed, and the controllable current value can be increased.

The base electrode 12 is connected via the resistor 27 in order to simplify the control circuit by applying the gate potential Vg and injecting the hole current from the base electrode 12 at the same time. The resistor 27 is inserted in order to prevent the gate potential Vg from rapidly decreasing due to the flow of current.

In the device of this example, the MOS 21 can be turned off by lowering the gate potential to about the cathode potential, so that the thyristor can be easily turned off. Therefore, the device of this example can realize a semiconductor device which can be easily turned off, has a small on-resistance, and further has a MOS control type thyristor having a large controllable current value.

[Second Embodiment] FIG. 2 shows an MO according to the second embodiment.
1 shows a cross section of a semiconductor device having an S-controlled thyristor element. The device of this example is similar to that of the first embodiment in that the n ⁻ type base layer 4, the p ⁺ type anode layer 5, the p type base layer 3,
A semiconductor device having a thyristor element composed of an n ⁺ -type cathode layer 7, an n ⁺ -type floating cathode layer 2, an n-channel MOS 21 connecting the cathode layer 7 and the floating cathode layer 2, and the like. The same components are designated by the same reference numerals and the description thereof will be omitted.

A point to be noted in this example is that a p ⁺ type guard layer 18 having a high impurity concentration is formed around the cathode layer 7. Therefore, the NPN transistor forming the parasitic thyristor is formed by the n ⁻ type base layer 4, the p ⁺ type guard layer 18 and the cathode layer 7. Therefore, the resistance between the cathode electrode 10 and the p ⁺ -type guard layer 18 can be reduced, and it is difficult to turn on the parasitic thyristor. Further, the p ⁺ type guard layer 18 can further suppress the outflow of electrons from the cathode layer 7 and prevent the parasitic thyristor from being turned on. On the other hand, by forming the p ⁺ -type guard layer 18, the impurity concentration of the p-type base layer 3 can be lowered, so that the on-resistance of the main thyristor can be further reduced and turned on more easily. The device can be realized.

[Third Embodiment] FIG. 3 shows an MO according to the third embodiment.
The structure of a semiconductor device having an S-controlled thyristor is shown. Also in the device of this example, as in Example 1, an n ⁻ -type base layer 4, ap ⁺ -type anode layer 5, a p-type base layer 3, an n ⁺ -type cathode layer 7, and an n ⁺ -type floating cathode layer 2, The semiconductor device has a thyristor element composed of an n-channel MOS 21 or the like that connects the cathode layer 7 and the floating cathode layer 2, and the same components as those in the first embodiment will be designated by the same reference numerals and description thereof will be omitted. ..

A point to be noted in the device of this example is that a MOS 23 for injecting a hole current is formed instead of the base electrode 12 in the first and second embodiments.
The MOS 23 includes the anode layer 5 and the anode electrode 1
1 is a MOS formed by connecting a buffer layer 9 which is an n type diffusion layer formed around the anode layer 5 and an n ⁻ type base layer 4 as a channel forming region. This M
The gate electrode 6 of the OS 23 is provided via the insulating film 15 from the p ⁻ type offset layer 13 formed around the p type base layer 3 to the anode layer 5. This MO
S23 is a p-channel type MOS, which conducts when a potential lower than the anode potential is applied to the gate electrode 6, and the hole current flows from the anode layer 5 to the p-type base layer 3 through the offset layer 13. Injected. Therefore, MO
When S21 is in the on state, an electron current flows out in response to the hole current injected from the floating cathode layer 2, and the main thyristor is turned on. In this device, the hole current injected by the MOS 23 triggers to turn on the thyristor, so that a device having low on-resistance can be realized.

Further, also in this device, the cathode layer 7 is formed by the shallow diffusion layer and the floating cathode layer 2 is formed by the deep diffusion layer as in the first and second embodiments, so that the latch-up is prevented. Has been planned. Further, the MOS 23 also has a floating cathode layer 2
On the other hand, since it is connected to the side opposite to the cathode layer 7, the hole current reaching the cathode region 7 is suppressed.
In this way, since the occurrence of latch-up is also prevented in the device of this example, the controllable current value can be increased. The device of this example can be easily turned off by lowering the gate potential Vg to about the cathode potential as in the first and second embodiments.

[Fourth Embodiment] FIG. 4 shows an MO according to a fourth embodiment.
1 shows a cross section of a semiconductor device having an S-controlled thyristor element. The device of the present example has the same configuration as that of the third embodiment, and the common components are designated by the same reference numerals and the description thereof will be omitted.

The point to be noted in this example is that the p ⁺ type guard layer 18 having a high impurity concentration is formed around the cathode layer 7 as in the second embodiment. Therefore, it is difficult to turn on the parasitic thyristor because the resistance between the cathode electrode 10 and the p ⁺ -type guard layer 18 can be reduced, and the p ⁺ -type guard layer 18 further suppresses the outflow of electrons from the cathode layer 7. Therefore, the occurrence of latch-up can be prevented.

Further, since the p ⁺ type guard layer 18 is formed, the impurity concentration of the p type base layer 3 can be lowered, so that the on-resistance of the main thyristor can be further reduced and turned on more easily. It is possible to realize a device that can.

[Fifth Embodiment] FIG. 5 shows a MOS according to the fifth embodiment.
1 shows the configuration of a semiconductor device having a control type thyristor. The device of this example is a vertical device like the conventional semiconductor device having a thyristor element, and the p ⁺ type anode layer 5 connected to the anode electrode 11 is formed on the back surface of the n ⁻ type base layer 4. The p-type first base layer 3 is formed on the surface of the n ⁻ -type base layer 4 facing the anode layer 5. Then, in the first base layer 3, n
^{The +} type floating cathode layer 2, the p ⁺ type second base layer 19, and the n ⁺ type cathode layer 7 are sequentially stacked. One end of each of the first base layer 3, the floating cathode layer 2, and the second base layer 19 is connected to the p ⁺ -type base contact layer 14 to which the cathode electrode 10 is connected together with the cathode layer 7, and the other end is a semiconductor. It is formed of a layered diffusion layer that reaches the surface of the device. The cathode layer 7 formed in the second base layer 19 is formed of a shallow diffusion layer on the semiconductor surface. In addition, an insulating film is formed from the cathode layer 7 to the second base layer 19, one end of which reaches the surface of the semiconductor device, the floating cathode layer 2, the first base layer 3, and the n ⁻ -type base layer 4. The gate electrode 1 is installed separately. Therefore, when the gate potential Vg applied to the gate electrode 1 is made higher than the cathode potential in the state where the bias potential is applied between the cathode electrode 10 and the anode electrode 5, the cathode layer 7 and the floating cathode layer 2 are electrically connected. The first MOS 21 is turned on. At the same time, the second MOS 22 that electrically connects the floating cathode layer 2 and the n ⁻ type base layer 4 is also turned on, so that electrons are injected from the floating cathode layer 2 through the MOS 22. In response to this, the hole current from the anode layer 5 flows into the first base layer 3. As a result, electrons flow out from the floating cathode layer 2, and the thyristor is turned on by using this as a cathode.

In the device of this example, the second base layer 19 on which the cathode layer 7 is formed is separated from the first base layer 3 by the floating cathode layer 2, and a hole current is generated from the first base layer 3. The structure is such that it hardly flows into the second base layer 19. Therefore, it is difficult to turn on the parasitic thyristor having the cathode layer 7 as a cathode, and latch-up is prevented.

Further, the device of this embodiment can be easily turned off by lowering the gate potential Vg to about the cathode potential. Furthermore, in order to reliably and rapidly turn off, the gate potential is set to be equal to or lower than the cathode potential and conduction is performed by using the p-channel type MOS 24 formed between the first base layer 3 and the second base layer 19. Is desirable. With this MOS 24, the hole current in the first base layer 3 can be discharged through the second base layer 19 and turned off early.

In this example, the second MOS 22
The thyristor is turned on by injecting electrons into the n ⁻ -type base layer 4 by using, and by injecting a hole current into the first base layer 3 as in the first to fourth embodiments. Of course, the thyristor can be turned on.

[Sixth Embodiment] FIG. 6 shows a MOS according to the sixth embodiment.
1 shows the configuration of a semiconductor device having a control type thyristor. Apparatus of this embodiment, n ^- is the type horizontal apparatus anode layer 5 of connected p ⁺ -type anode electrode 11 is formed on the surface of the base layer 4, n facing the anode layer 5 ^- type The p-type first base layer 3 is formed on the base layer 4. The configuration of the thyristor in the device of this example is the same as that of the fifth embodiment.
The same reference numerals are given to common components, and description thereof will be omitted.

In the device of this example, both ends of the floating cathode layer 7 and the p ⁺ -type second base layer 19 which are sequentially stacked in the first base layer 3 reach the surface of the semiconductor device.

The second base layer 19 has a 2
One cathode layer 7a, 7b is formed, and the cathode electrode 10 is connected to the surface of the two cathode layers 7a, 7b and the second base layer 19 sandwiched between these layers. Further, the second cathode electrode 10 a connected to the cathode electrode 10 is connected to the first base layer 3.

On the surfaces of these semiconductors, a gate electrode 1 is provided from the cathode layers 7a and 7b to the floating cathode layer 2 with an insulating film 15 interposed therebetween, and from the floating cathode layer 2 to the n ⁻ -type base layer 4. The gate electrode 16 is installed over the entire area. Therefore, these gate electrodes 1 and 16 form the MOS 21 and the MOS 22 as in the fifth embodiment.
The cathode layer 2, the floating cathode layer 2, n
^The main type thyristor is turned on by the conduction of the negative type base layer 4.

In the device of this example, the cathode layer 7a,
Since the second base layer 19 on which 7b is formed is completely separated from the first base layer 3 by the floating cathode layer 2, a hole current does not flow into the second base layer 19 and the cathode layer 7a, The parasitic thyristor whose cathode is 7b does not turn on. Therefore, the device of this example is prevented from latching up, and the current value controlled by this device can be greatly increased.

Although the gate electrodes 1 and 16 are used in this example, one gate electrode is provided from the cathode layer 7, the second base layer 19, the floating cathode layer 2 and the first electrode as in the fifth embodiment. It is also possible to install it on the n ⁻ -type base layer 4 via the base layer 3. Further, instead of the second cathode electrode 10a and the gate electrode 16,
The thyristor can be turned on by injecting a hole current into the first base layer 3 as in the first to fourth embodiments. Further, the device of this example can be easily turned off as in the case of Example 5, and the first base layer 3 and the second base layer 3 can be turned off when the device is turned off.
By making the base layer 19 conductive, it can be turned off reliably and at high speed.

[Embodiment 7] FIGS. 7 and 8 show the structure of a semiconductor device having a MOS control thyristor according to Embodiment 2. The semiconductor device shown in FIG. 7 has substantially the same configuration as the semiconductor device described with reference to FIG. 15, and the semiconductor device shown in FIG.
Since the semiconductor device has substantially the same configuration as that of the semiconductor device, the common parts are denoted by the same reference numerals and the description thereof will be omitted.

[0056] It should be noted in the apparatus of the present embodiment, p ^-
A n ^- type base layer 4 epitaxially grown on the n ^- type semiconductor substrate 28 to form a thyristor element,
At this time, in that the p ⁺ -type buried layer 29 is formed so as to surround the bottom of the p ⁺ -type base layer 3 of the end portion 17. In the devices of FIGS. 7 and 8, a bias potential is applied between the cathode electrode and the anode electrode to electrically connect the floating cathode layer 2 and the cathode layer 7, and n ⁻
The thyristor is turned on by the electron current injected into the p-type base layer 4 or the hole current injected into the p ⁺ -type base layer 3 as a trigger. At this time, p
^A depletion layer extends mainly from the junction surface between the ⁺ type base layer 3 and the n ⁻ type base layer 4 toward the n ⁻ type base layer 4. In this case, the electric field is concentrated at the end portion 17, and the ON breakdown voltage of the device is determined by the breakdown voltage in this portion.

In this device, since the p ⁺ type buried layer 29 is formed so as to surround under the end portion 17, the depletion layer extending from the p ⁺ type base layer 3 enters this buried layer 29. Instead, it extends along the buried layer 29. Therefore, the curvature of the equipotential line in the vicinity of the end portion 17 becomes large, the electric field is dispersed, and the concentration is relieved, so that the breakdown voltage of this portion can be improved. Therefore, it is possible to improve the ON breakdown voltage of the device of this example.

Needless to say, the ON breakdown voltage can be improved by the buried layer 29 not only in the second embodiment but also in all the embodiments.

[Embodiment 8] FIGS. 9 and 10 show the structure of a semiconductor device having a MOS-controlled thyristor according to Embodiment 8. The device shown in this example also has substantially the same configuration as the semiconductor device described with reference to FIG. 15, and the semiconductor device shown in FIG.
Since the semiconductor device has substantially the same configuration as that of the semiconductor device, the common parts are denoted by the same reference numerals and the description thereof will be omitted.

The point to be noted in the apparatus of this example is p ⁺
That is, the p ⁻ type offset layer 13 is formed so as to surround the mold base layer 3. Therefore, in the device of this example, the depletion layer due to the bias potential described in Example 7 spreads to the offset layer 13 and the curvature of the equipotential line at the end 17 becomes large, so that the concentration of the electric field is relaxed. Then, the on-breakdown voltage can be improved.

As with the seventh embodiment, it is needless to say that the ON breakdown voltage can be improved by the offset layer 13 not only in the second embodiment but also in all the embodiments. Also,
It is also possible to use it together with a buried layer.

[Ninth Embodiment] FIG. 11 shows an MO according to the ninth embodiment.
An example of a semiconductor device having an S-controlled thyristor is shown. The semiconductor device of this example is a high-side switch type device that can be controlled with reference to the anode potential.

In the device of this example, first, the n ^-- type base layer 4
P-type base layer 3 in which the base electrode 12 is connected to the surface of the
And the n ⁺ type cathode layer 7 to which the cathode electrode 10 is connected is formed in the p type base layer 3. A p ⁺ -type anode layer 5 is formed on the surface of an n ⁻ -type base layer 4 facing these, and an n ^- type buffer layer 9 is formed around this anode layer 5, and together with the anode layer 5, an anode is formed. The electrode 11 is connected. A p ⁺ type floating anode layer 20 is formed between the anode layer 5 and the p type base layer 3 so as to sandwich the buffer layer 9. On the buffer layer 9, the gate electrode 1 is provided across the insulating film 15 from the anode layer 5 to the floating anode layer 20 to form a p-channel type MOS 25.

In the device of this example, the cathode electrode 10
When a potential Vg applied to the gate electrode 1 is set to be equal to or lower than the anode potential in a state where a bias potential is applied between the anode electrode 11 and the anode electrode 11, the anode layer 5 and the floating anode layer 20 are brought into conduction and are in a floating state. Holes flow out from the floating anode layer 20, and the thyristor using this as an anode is turned on. At the same time,
By injecting a hole current from the base electrode 12 into the p-type base layer 3, the thyristor can be turned on early. Then, by connecting the base electrode 12 to the gate electrode 1 through the resistor 27, the control circuit can be simplified as in the first embodiment. Further, when the gate potential Vg is raised to the anode potential, the floating anode layer 20 and the anode layer 5 are separated, and the thyristor can be easily turned off. As described above, the device of this example is a high-side switch type device that can be controlled based on the anode potential, and the thyristor is configured using the same diffusion layer configuration as the devices of the other examples. ing. Therefore, a switch element which can be formed on a semiconductor substrate together with an integrated circuit such as an IC has been realized.

In the present embodiment, the anode layer 5 is set farther from the p-type base layer 3 in order to prevent latch-up due to the turning on of the parasitic thyristor having the anode layer 5 as the anode. Further, the anode layer 5 is formed in the buffer layer 9 to prevent holes from flowing out.

[Embodiment 10] FIG. 12 shows an example of a semiconductor device having a MOS control thyristor according to Embodiment 10. The configuration of the device of this example is substantially the same as the configuration of the device according to the ninth embodiment, and common portions are denoted by the same reference numerals and description thereof is omitted.

A point to be noted in the device of this example is that a MOS 23 for injecting a hole current is formed instead of the base electrode 12 in the device of the ninth embodiment. This MOS 23 is connected to the floating anode layer 20 from n ^−.
The gate electrode 6 is provided on the p ⁻ type offset layer 13 formed around the p type base layer 3 via the insulating film 15 via the type base layer 4. Therefore, by applying the potential Vg applied to the gate electrode 1 forming the MOS 25 to the gate electrode 6, the floating anode layer 20 is electrically connected to the anode layer 5 and holes flow out, and at the same time, the hole current is changed to p. It can be injected into the base layer 3 of the mold via the offset layer 13 and the main thyristor can be turned on early.

Also in the device of this example, the anode layer 5 is set farther from the base layer 3 so that the parasitic thyristor having the anode layer 5 as the anode does not turn on, and the anode layer 5 is set to the buffer layer 9. It is formed inside to prevent the outflow of holes.

Although the gate electrode 6 and the gate electrode 1 are provided in this example, one gate electrode is provided from the anode layer 5 to the buffer layer 9, the floating anode layer 20, and the n ⁻ type base layer 4. You may install over.
It is also possible to turn on the thyristor by injecting electrons from the cathode layer 7 into the n ⁻ type base layer 4.

It is needless to say that the thyristor having the structure described in this example and the above-described first to tenth embodiments can be realized in both the vertical type and the horizontal type. Further, although one element is described, it is needless to say that two or more elements can be formed in one semiconductor device, and that an element and a circuit can be formed in one semiconductor device. It is possible to exert the same action and effect as described in.

[0071]

As described above, in the semiconductor device having the MISFET control type thyristor according to the present invention, some problems which have been problems in expanding the application range of this device can be solved. IC
It is possible to realize a semiconductor device having a wide range of applications as a high breakdown voltage and high speed power semiconductor that can be formed on a semiconductor substrate similar to the above.

First, by adopting the floating cathode region formed by the deep diffusion layer, it is possible to prevent latch-up and increase the controllable current value.

By separating the first-conductivity-type base region in which the cathode region is formed by the floating cathode region, it is possible to further prevent latch-up and control a higher current value. Becomes

By injecting a hole current into the first-conductivity-type base region, the thyristor mode can be realized at an early stage and the on-voltage can be reduced. The hole current injection means can be realized by a simple structure such as employing a base electrode connected to the first conductivity type base region or a MISFET connecting the anode region and the first conductivity type base region. it can.

Further, by adopting the buried layer or the offset layer, the electric field concentrated at the end of the first conductivity type base region can be relaxed, and the on-breakdown voltage can be improved. ..

By forming the floating anode region, it is possible to realize a high side switch type that can be controlled with the anode potential as a reference and can be formed on the same substrate as an IC or the like. it can.

As described above, in the semiconductor device having the MISFET control type thyristor according to the present invention, the controllable current value increase, the on-resistance decrease, the on-breakdown voltage improvement, which are problems in the conventional device, A high-side switch type thyristor element that can be formed on a substrate of the same conductivity type has been realized, and it is possible to greatly expand the applicable range.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a MOS control thyristor element according to a first embodiment.

FIG. 2 is a sectional view showing a configuration of a MOS control type thyristor element according to a second embodiment.

FIG. 3 is a sectional view showing a configuration of a MOS control type thyristor element according to a third embodiment.

FIG. 4 is a sectional view showing a configuration of a MOS control thyristor element according to a fourth embodiment.

FIG. 5 is a sectional view showing a configuration of a MOS control thyristor element according to a fifth embodiment.

FIG. 6 is a sectional view showing a configuration of a MOS control type thyristor element according to Example 6;

FIG. 7 is a sectional view showing a configuration of a MOS control type thyristor element according to Example 7.

FIG. 8 is a sectional view showing a configuration of a MOS control type thyristor element according to Example 7.

FIG. 9 is a cross-sectional view showing the structure of a MOS control type thyristor element according to Example 8.

FIG. 10 is a cross-sectional view showing the configuration of a MOS control type thyristor element according to Example 8.

FIG. 11 is a sectional view showing the structure of a MOS control type thyristor element according to Example 9;

FIG. 12 is a sectional view showing the structure of a MOS control type thyristor element according to Example 10;

FIG. 13 is a cross-sectional view showing the structure of a conventional MOS control type thyristor element.

FIG. 14 is a circuit diagram showing an equivalent circuit of the element shown in FIG.

FIG. 15 is a cross-sectional view showing the configuration of a MOS control type thyristor element different from the conventional one shown in FIG.

16 is a circuit diagram showing an equivalent circuit of the device shown in FIG.

[Explanation of symbols]

1 ... gate electrode 2... N ⁺ -type floating cathode layer 3 ... p-type base layer 4, ... n ^- -type base layer 5 ... p ⁺ -type anode layer 6 ... Gate electrode 7 ... N ⁺ type cathode layer 9 ... Buffer layer 10 ... Cathode electrode 11 ... Anode electrode 12 ... Base electrode 13 ... Offset layer 14 ... Base contact layer 15・ ・ ・ Insulating film 16 ・ ・ ・ Gate electrode 17 ・ ・ ・ End of base layer 18 ・ ・ ・ Guard layer 19 ・ ・ ・ Second p ⁺ type base layer 21 to 25 ・ ・ ・ MOS 26, 27 ・ ・ ・・ Resistance

Claims (15)

[Claims] 1. A base region of the first conductivity type and a base region of the first conductivity type at a position on the base region of the second conductivity type facing the anode region of the first conductivity type to which an anode potential is applied. At least a second conductivity type cathode region formed in the base region and having a cathode potential applied thereto together with the first conductivity type base region, and the cathode region and the first M type cathode region.
A semiconductor device having a MISFET control type thyristor in which a second conductivity type floating cathode region connected by an ISFET is independently formed between the cathode region and the anode region in the first conductivity type base region. Wherein the cathode region is a shallow diffusion layer formed on the surface of the second conductivity type base region, and the floating cathode region is a deep diffusion layer formed up to near the bottom of the second conductivity type base region. MIS characterized by
A semiconductor device having a FET-controlled thyristor. 2. A second conductive type base region having at least a first conductive type base region at a position facing the first conductive type anode region to which an anode potential is applied, on the second conductive type base region. Type floating cathode region, first
A first conductivity type second base region connected to the first conductivity type base region by a conductivity type base contact region, a cathode potential is applied together with the base contact region, and the floating cathode region and the first MIS.
A semiconductor device having a MISFET control type thyristor, characterized in that a cathode region of a second conductivity type connected by an FET is sequentially stacked in the first base region from below. 3. A base region of the first conductivity type is provided at least in a position on the base region of the second conductivity type facing the anode region of the first conductivity type to which the anode potential is applied. A second conductivity type floating cathode region formed in the conductivity type base region, a first conductivity type second base region formed in the floating cathode region, and a second conductivity type floating cathode region formed in the second base region. At least a second conductive type cathode region to which the cathode potential is applied together with a second base region, and a first MISFET connecting the cathode region and the floating cathode region are provided. Semiconductor device having a thyristor. 4. The method according to any one of claims 1 to 3,
A semiconductor device having a MISFET control type thyristor, wherein the cathode region is covered with a first conductive type guard layer formed of a high concentration impurity diffusion layer. 5. A base region of the first conductivity type and a base region of the first conductivity type at a position on the base region of the second conductivity type facing the anode region of the first conductivity type to which the anode potential is applied. A first conductive type cathode region which is formed in the base region and to which a cathode potential is applied, and which is connected to the anode region by a first MISFET
A semiconductor having a MISFET controlled thyristor, wherein a conductive type floating anode region is formed on the second conductive type base region between the anode region and the first conductive type base region. apparatus. 6. A base region of the first conductivity type and a base region of the first conductivity type at a position on the base region of the second conductivity type facing the anode region of the first conductivity type to which the anode potential is applied. At least a second conductivity type cathode region formed in the base region and having a cathode potential applied thereto together with the first conductivity type base region, and the cathode region and the first M type cathode region.
A semiconductor device having a MISFET control type thyristor in which a second conductivity type floating cathode region connected by an ISFET is independently formed between the cathode region and the anode region in the first conductivity type base region. A hole current injecting means is installed on the side of the floating cathode region on the first conductivity type base region opposite to the cathode region.
A semiconductor device having a T-controlled thyristor. 7. The method according to any one of claims 1 to 4,
MISFE, in which hole current injection means is installed on the side of the floating cathode region on the first conductivity type base region opposite to the cathode region.
A semiconductor device having a T-controlled thyristor. 8. A MISFET control type thyristor according to claim 5, wherein a hole current injection means is provided on a side of the first conductivity type base region facing the floating anode region. Semiconductor device having. 9. The method according to claim 6, wherein
The hole current injection means is a base electrode connected to the first conductivity type base region. MI.
A semiconductor device having an SFET controlled thyristor. 10. The MISFET according to claim 9, wherein a gate potential applied to the gate electrode of the first MISFET is applied to the base electrode.
Semiconductor device having a controlled thyristor. 11. The second MIS according to claim 6, wherein the hole current injection means injects a hole current from the anode region to the first base region.
A semiconductor device having a MISFET control type thyristor, which is a FET. 12. A base region of the first conductivity type and a base region of the first conductivity type at a position on the base region of the second conductivity type facing the anode region of the first conductivity type to which the anode potential is applied. A second conductivity type having at least a second conductivity type cathode region formed in the base region and having a cathode potential applied together with the first conductivity type base region, the second conductivity type being connected to the cathode region by the first MISFET. Is a semiconductor device having a MISFET control type thyristor in which the floating cathode region of the first conductivity type base region is independently formed between the cathode region and the anode region of the first conductivity type base region. A buried layer of the first conductivity type is formed inside the second conductivity type base region at least below the end of the base region facing the anode region. A semiconductor device having a MISFET controlled thyristor according to claim. 13. The first conductive type according to claim 1, wherein the first conductive type base region is located at least below an end of the second conductive type base region facing the anode region. A semiconductor device having a MISFET control type thyristor, in which a buried type layer is formed. 14. A base region of the first conductivity type and a base region of the first conductivity type at a position on the base region of the second conductivity type facing the anode region of the first conductivity type to which the anode potential is applied. A second conductivity type having at least a second conductivity type cathode region formed in the base region and having a cathode potential applied together with the first conductivity type base region, the second conductivity type being connected to the cathode region by the first MISFET. Is a semiconductor device having a MISFET control type thyristor in which the floating cathode region of the first conductivity type base region is independently formed between the cathode region and the anode region of the first conductivity type base region. An MI, characterized in that an offset layer of a low-concentration impurity diffusion layer is formed so as to surround at least an end portion of the base region facing the anode region.
A semiconductor device having an SFET controlled thyristor. 15. The offset layer according to claim 1, wherein a low-concentration impurity diffusion layer surrounds at least an end of the first conductivity type base region facing the anode region. A semiconductor device having a MISFET control type thyristor.