JPH05121697A - Manufacture of semiconductor storage device - Google Patents

Manufacture of semiconductor storage device

Info

Publication number
JPH05121697A
JPH05121697A JP3279951A JP27995191A JPH05121697A JP H05121697 A JPH05121697 A JP H05121697A JP 3279951 A JP3279951 A JP 3279951A JP 27995191 A JP27995191 A JP 27995191A JP H05121697 A JPH05121697 A JP H05121697A
Authority
JP
Japan
Prior art keywords
mask rom
protective film
film layer
wiring layer
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3279951A
Other languages
Japanese (ja)
Inventor
Masahisa Uramoto
正久 浦本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP3279951A priority Critical patent/JPH05121697A/en
Publication of JPH05121697A publication Critical patent/JPH05121697A/en
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To manufacture a mask ROM which can be supplied in a short delivery time, by performing ion implantation after a final protective film layer is formed, when data of memory contents are written on the mask ROM. CONSTITUTION:Data of memory contents are written on a mask ROM as follows. High melting point metal or similar heat resistant conducting material is used as a metal wiring layer 5 of the mask ROM. After a final protective film layer 6 is formed, photo resist 7 corresponding with memory contents is formed. By ion implantation using the photo resist 7 as a mask, data can be written on the mask ROM.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体記憶装置の製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device.

【0002】[0002]

【従来の技術】従来の半導体記憶装置の製造方法は、図
2(a)〜(d)に示す方法により行っていた。図2
(a)は、基板1上に所望の形状に形成されたフォトレ
ジスト7をマスクに不純物を注入し記憶素子への情報の
有無を記録するための不純物層8を形成したものであ
る。図2(b)は、図2(a)上にゲート電極2を形成
したものである。図2(c)は、図2(b)に拡散配線
層3を形成したものである。図2(d)は、図2(c)
上に絶縁膜層4、金属配線層5及び保護膜層6を形成し
たものである。
2. Description of the Related Art A conventional method of manufacturing a semiconductor memory device has been performed by the method shown in FIGS. Figure 2
In FIG. 1A, an impurity layer 8 for recording the presence or absence of information in a memory element is formed by implanting impurities using a photoresist 7 formed in a desired shape as a mask on the substrate 1. FIG. 2B shows the gate electrode 2 formed on the structure of FIG. FIG. 2C shows the diffusion wiring layer 3 formed in FIG. 2B. 2 (d) is shown in FIG. 2 (c).
The insulating film layer 4, the metal wiring layer 5, and the protective film layer 6 are formed on the top.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来のような
半導体記憶装置の製造方法では顧客より記録情報データ
を入手後、半導体記憶装置の完成までの期間が長くなる
という課題を有していた。
However, the conventional method of manufacturing a semiconductor memory device has a problem that it takes a long time to complete the semiconductor memory device after obtaining the record information data from the customer.

【0004】[0004]

【課題を解決するための手段】上記の課題を解決するた
めに、この発明においては、金属配線層を高融点金属に
変更することにより、記憶素子への情報の有無を記録す
るための不純物注入工程を保護膜形成後に行えるように
なった。
In order to solve the above problems, according to the present invention, a metal wiring layer is changed to a refractory metal so that an impurity is injected to record the presence or absence of information in a memory element. The process can be performed after forming the protective film.

【0005】[0005]

【作用】上記のような方法により、半導体記憶装置の記
憶素子への情報の有無を記録する不純物注入工程を従来
のゲート配線形成前より保護膜形成後に変更することが
できる。
According to the method as described above, the impurity injection step for recording the presence / absence of information in the memory element of the semiconductor memory device can be changed after the protective film is formed, before the conventional gate wiring is formed.

【0006】[0006]

【実施例】以下にこの発明の実施例を図に基づき説明す
る。図1(a)〜(d)は、この発明の半導体記憶装置
の製造方法を示す工程順断面図である。図1(a)は、
基板1上にゲート電極2を形成したものである。この時
点ではまだ、情報の有無は記録されていない。図1
(b)は、図1(a)に拡散配線層3を形成したもので
ある。図1(c)は、図1(b)上に絶縁膜層4、金属
配線層5及び保護膜層6を形成したものである。この発
明では、金属配線層5に、融点900℃以上の導電性材
料(例えば、シリサイド ポリサイド 高融点金属単
独)又は起電導物質等で形成する。図1(d)は、図1
(c)上に所望の形状に形成されたフォトレジスト7を
マスクに不純物を注入し、記憶素子への情報の有無を記
録するための不純物層8を形成したものである。この不
純物注入は、高電圧イオン注入装置を使用すれば容易に
行えるものであり、技術的には何ら問題はない。又、従
来の半導体記憶素子では、金属配線層5にアルミニウム
を使用しているため、この発明と同様な工程順にて不純
物注入を行っても不純物の活性化処理がアルミニウム融
点以下では行えないため、金属配線形成以後に不純物注
入工程を変更することは不可能である。この発明によ
り、通常顧客より記録情報データを入手後半導体記憶装
置の完成まで2〜8マスクの工程が必要であったもの
が、1マスクのみの工程で完成し大幅に納期の短縮が行
われる。
Embodiments of the present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views in order of the steps, showing a method for manufacturing a semiconductor memory device of the present invention. Figure 1 (a)
The gate electrode 2 is formed on the substrate 1. The presence or absence of information has not yet been recorded at this point. Figure 1
FIG. 1B shows the diffusion wiring layer 3 formed in FIG. FIG. 1C shows an insulating film layer 4, a metal wiring layer 5, and a protective film layer 6 formed on the structure shown in FIG. In the present invention, the metal wiring layer 5 is formed of a conductive material having a melting point of 900 ° C. or higher (for example, silicide polycide refractory metal alone) or an electroconductive material. FIG. 1D is the same as FIG.
(C) Impurities are implanted using a photoresist 7 formed in a desired shape as a mask, and an impurity layer 8 for recording the presence / absence of information in a memory element is formed thereon. This impurity implantation can be easily performed by using a high-voltage ion implantation device, and there is no technical problem. Further, in the conventional semiconductor memory element, since aluminum is used for the metal wiring layer 5, the impurity activation process cannot be performed below the aluminum melting point even if the impurity implantation is performed in the same process order as in the present invention. It is impossible to change the impurity implantation process after forming the metal wiring. According to the present invention, although the process of 2 to 8 masks is normally required until the semiconductor memory device is completed after the record information data is obtained from the customer, the process is completed with only one mask, and the delivery time is greatly shortened.

【0007】[0007]

【発明の効果】この発明は、以上説明したように記憶素
子への情報を記録する為の不純物注入工程を、ゲート電
極形成前から、保護膜形成後に変更することにより短納
期で半導体記憶装置の供給を行うことができるようにな
る。
As described above, according to the present invention, the impurity injection process for recording information in the memory element is changed from before the gate electrode is formed to after the protective film is formed, so that the semiconductor memory device can be delivered in a short time. You will be able to supply.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(d)は本発明の半導体記憶装置の製
造方法を示す工程順断面図である。
1A to 1D are cross-sectional views in order of the steps, showing a method for manufacturing a semiconductor memory device of the present invention.

【図2】(a)〜(d)は従来の半導体記憶装置の製造
方法を示す工程順断面図である。
2A to 2D are cross-sectional views in order of the steps, showing a conventional method for manufacturing a semiconductor memory device.

【符号の説明】[Explanation of symbols]

1 基板 2 ゲート電極 3 拡散配線層 4 絶縁膜層 5 金属配線層 6 保護膜層 7 フォトレジスト 8 不純物層 1 substrate 2 gate electrode 3 diffusion wiring layer 4 insulating film layer 5 metal wiring layer 6 protective film layer 7 photoresist 8 impurity layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 金属配線層を高融点金属で形成する工程
と、前記金属配線層上に所望の形状に窓あけされた保護
膜層を形成する工程と、前記保護膜層上に記録する情報
にしたがって加工されたフォトレジストを形成する工程
と、前記フォトレジストをマスクとして情報を記録する
ための不純物注入を行う工程とからなる半導体記憶装置
の製造方法。
1. A step of forming a metal wiring layer with a refractory metal, a step of forming a protective film layer having a window formed in a desired shape on the metal wiring layer, and information recorded on the protective film layer. A method of manufacturing a semiconductor memory device, comprising: a step of forming a photoresist processed according to the above method; and a step of implanting impurities for recording information using the photoresist as a mask.
JP3279951A 1991-10-25 1991-10-25 Manufacture of semiconductor storage device Pending JPH05121697A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3279951A JPH05121697A (en) 1991-10-25 1991-10-25 Manufacture of semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3279951A JPH05121697A (en) 1991-10-25 1991-10-25 Manufacture of semiconductor storage device

Publications (1)

Publication Number Publication Date
JPH05121697A true JPH05121697A (en) 1993-05-18

Family

ID=17618202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3279951A Pending JPH05121697A (en) 1991-10-25 1991-10-25 Manufacture of semiconductor storage device

Country Status (1)

Country Link
JP (1) JPH05121697A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665995A (en) * 1993-10-22 1997-09-09 United Microelectronics Corporation Post passivation programmed mask ROM
US5744394A (en) * 1996-08-26 1998-04-28 Sharp Kabushiki Kaisha Method for fabricating a semiconductor device having copper layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665995A (en) * 1993-10-22 1997-09-09 United Microelectronics Corporation Post passivation programmed mask ROM
US5744394A (en) * 1996-08-26 1998-04-28 Sharp Kabushiki Kaisha Method for fabricating a semiconductor device having copper layer

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