JPH05121433A - Method for forming ldd construction for mos transistor - Google Patents

Abstract

PURPOSE:To form an LDD construction with good controllability in a simple process by driving impurities of a high concentration by ion implantation method in the vertical direction of a substrate and driving impurities of a low concentration in a diagonal direction by the ion implantation method while rotating the substrate after the formation of a gate electrode. CONSTITUTION:After forming a gate electrode 22 on a substrate 21, it is kept in level state, impurities 23 of a high concentration are driven from vertical direction by ion implantation method using a gate electrode 22 as mask. Then, it is tilted about 30 deg. to 45 deg. from the vertical, and further impurities 24 of a low concentration are driven by the ion implantation method from vertical direction using the gate electrode 22 as mask while turning it and maintaining that angle of tilt. Then, the impurities 24 are driven into the substrate 21 in a diagonal direction and also the substrate 21 is turning, so that it becomes possible to drive the impurities 24 to the lower portion at the ends on both the sides of the gate electrode 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an LDD (Lightly Doped Drain) structure of a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, an LDD structure of a MOS transistor is formed as shown in FIG. First, Fig. 3
Forming a gate electrode 2 on the substrate 1 as shown in FIG.
Using the gate electrode 2 as a mask, a low concentration impurity 3 is implanted into the substrate 1 by an ion implantation method. Next, substrate 1
A film such as SiO ₂ (here, a SiO ₂ film) 4 is formed on the upper surface by CVD (Camical Vapor Deposition) method.
It is formed as shown in FIG. The SiO ₂ film 4 is RI
The entire surface is etched by an anisotropic etching method such as E (Reactive Ion Etch) method, and the SiO ₂ film 4 is left only on the side wall of the gate electrode 2 as shown in FIG. Using the remaining SiO ₂ film 4 and the gate electrode 2 as a mask, a high concentration impurity 5 is implanted into the substrate 1 by an ion implantation method as shown in FIG. Finally, by annealing, the low concentration diffusion region 6 is formed in the substrate 1 as shown in FIG.
And a high concentration diffusion region 7 is formed.

FIG. 4 shows a method for forming the above LDD structure in a CM.
This is the case when applied to an OS transistor. Figure 4
After forming the element isolation oxide film 8 and the gate electrode 2 on the substrate 1 as shown in FIG.
After covering the side with the resist pattern 10, the low-concentration impurities 3a are formed in the substrate 1 in the NMOS transistor formation region 11.
Is implanted by ion implantation using the gate electrode 2 as a mask. Next, as shown in FIG. 4B, after covering the NMOS transistor formation region 11 side with a resist pattern 12,
A low-concentration impurity 3b is implanted into the substrate 1 in the PMOS transistor formation region 9 by ion implantation using the gate electrode 2 as a mask. After that, an SiO ₂ film 4 is formed on the entire surface of the substrate 1 as shown in FIG. 4C, and the entire surface of the SiO ₂ film 4 is etched by an anisotropic etching method to obtain the structure shown in FIG.
As shown in (d), SiO is formed only on the side wall of the gate electrode 2.
₂ Leave the film 4. After that, as shown in FIG.
After covering the S transistor formation region 9 side with a resist pattern 13, a high concentration impurity 5a is added to the gate electrode 2 and the SiO 2 in the substrate 1 of the NMOS transistor formation region 11.
₂ Ion implantation is performed using the film 4 as a mask. Then, as shown in FIG. 4F, after covering the NMOS transistor formation region 11 side with a resist pattern 14, PM
A high-concentration impurity 5b is implanted into the substrate 1 in the OS transistor formation region 9 by the ion implantation method using the gate electrode 2 and the SiO ₂ film 4 as a mask. Finally, by annealing, as shown in FIG. 4 (g), the low concentration diffusion region 6a and the high concentration diffusion region 7a of the NMOS transistor and the low concentration diffusion region 6b and the high concentration diffusion region 7b of the PMOS transistor are formed in the substrate 1. Form.

[0004]

However, in the conventional forming method as described above, in order to form the LDD structure (low concentration and high concentration diffusion regions), taking a CMOS transistor as an example, a resist pattern is formed. The photolithography process for formation requires four times, the ion implantation process requires four times, and the SiO ₂ film forming / etching process requires one time each, which is a drawback that the process becomes complicated. Further, SiO ₂ gate electrode side wall portions formed by forming etching of SiO ₂ film
It is difficult to control the film shape and the LDD structure varies.

The present invention has been made in view of the above points, and an object thereof is to provide a method for forming an LDD structure of a MOS transistor capable of forming an LDD structure with good controllability in a simple process.

[0006]

According to the present invention, in a method for forming an LDD structure of a MOS transistor, after forming a gate electrode, a step of implanting an impurity having a higher concentration than a vertical direction of the substrate by an ion implantation method and rotating the substrate. While letting
The step of implanting a low concentration impurity from the oblique direction by an ion implantation method is performed.

[0007]

When a low-concentration impurity is implanted obliquely while rotating the substrate, it is possible to implant a low-concentration impurity under the both side ends of the gate electrode. It becomes possible to form a low-concentration impurity region (low-concentration diffusion region) by protruding from the (high-concentration diffusion region) to the inside of the gate electrode, and an LDD structure is obtained. Further, according to this method, the step of forming the SiO ₂ film on the side wall of the gate electrode becomes unnecessary. Also,
When applied to a CMOS transistor, high-concentration and low-concentration ion implantation on the other side can be continuously performed with one side covered with a resist pattern, so that the photolithography process only needs to be performed twice. When implanting impurities, the element isolation oxide film prevents implantation of impurities on the two sides of the entire outer circumference of the gate electrode, which are perpendicular to both ends. Therefore, the impurities are implanted only on both side ends of the gate electrode as described in the above-mentioned implantation condition of the low-concentration impurities, so that a diffusion region as a pair of left and right source / drain is formed.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention, which is a basic example of the present invention. First, as shown in FIG. 1A, after forming a gate electrode 22 on a substrate 21, the substrate 21 is kept in a horizontal state, and a high-concentration impurity 23 is added to the substrate 21 in a vertical direction with respect to the gate electrode 22. Ion implantation is used as a mask. Next, as shown in FIG. 1B, the substrate 21 is tilted from the horizontal state in the vertical direction by about 30 ° to 45 °, and further, while rotating the substrate 21 while maintaining the tilt angle, A low-concentration impurity 24 is vertically implanted into the substrate 21 by ion implantation using the gate electrode 22 as a mask. Then, the impurities 24 are removed from the substrate 21.
Since the substrate 21 is rotated obliquely with respect to the gate electrode 22, the impurities 24 can be implanted into the lower portions of both side ends of the gate electrode 22. Therefore, when annealing is performed next, as shown in FIG. 1C, in the substrate 21, the low-concentration impurity 2 is projected from the high-concentration diffusion region 25 of the high-concentration impurity 23 to the inside of the gate electrode.
4, the low-concentration diffusion region 26 is formed, and the LDD structure is obtained. When the impurities 23 and 24 are implanted, the element isolation oxide film (not shown) prevents implantation of impurities on the two sides of the entire outer periphery of the gate electrode 22 which are perpendicular to both ends. . Therefore, the impurities 23,
24 is implanted only on both side ends of the gate electrode 22 as described for the low concentration impurity, and as shown in FIG.
26 is formed. In addition, a gate insulating film is actually interposed between the gate electrode 22 and the substrate 21.

FIG. 2 shows a second embodiment of the present invention in which the present invention is applied to a CMOS transistor. First, as shown in FIG. 2A, a device isolation oxide film 32 is formed on a substrate 31.
After forming the gate electrode 33 and the gate electrode 33, the PMOS transistor formation region 34 side is covered with a resist pattern 35. Then, with the substrate 31 in a horizontal state, the NMO is
A high-concentration impurity 37 is implanted into the substrate 31 in the S-transistor formation region 36 by ion implantation using the gate electrode 33 as a mask. Next, as shown in FIG.
Is tilted, and while the substrate 31 is rotated while maintaining the tilt angle, a low concentration impurity 38 is vertically implanted into the substrate 31 in the NMOS transistor forming region 36 by using the gate electrode 33 as a mask. The low-concentration impurities 38 are obliquely implanted into the substrate 31. Next, the resist pattern 35 is removed, and this time, as shown in FIG. 2C, the NMOS of the substrate 31 is removed.
The transistor formation region 36 side is covered with a resist pattern 39, the substrate 31 is made horizontal, and in that state, a high concentration impurity 40 is ion-deposited in the substrate 31 of the PMOS transistor formation region 34 from the vertical direction using the gate electrode 33 as a mask. Drive by injection method. Next, as shown in FIG. 2D, the substrate 31 is tilted, and while the tilt angle is maintained and the substrate 31 is rotated, impurities of a low concentration are vertically introduced into the substrate 31 in the PMOS transistor formation region 34 from the vertical direction. 41
Is implanted by ion implantation using the gate electrode 33 as a mask. The low-concentration impurities 41 are obliquely implanted into the substrate 31. Finally, annealing is performed. As a result of this annealing, as shown in FIG. 2E, a pair of left and right high-concentration diffusion regions 42 and low-concentration diffusion regions 43 are formed in the substrate 31 of the PMOS transistor formation region 34 and in the substrate 31 of the NMOS transistor formation region 36, respectively.・
Formed as a drain. Moreover, since the low-concentration impurities 38 and 41 are implanted obliquely while the substrate 31 is rotated, the low-concentration diffusion region 43 is located inside the gate electrode 33 with respect to the high-concentration diffusion region 42 (below both side ends of the gate electrode 33). The LDD structure is obtained as a result of the protruding shape.

[0010]

As described above in detail, according to the present invention, after the gate electrode is formed, a step of ion-implanting a high concentration impurity from the vertical direction of the substrate, and a step of lowering the impurity concentration from the oblique direction while rotating the substrate. Since the LDD structure is formed by performing the step of ion-implanting impurities of a high concentration, for example, in a CMOS transistor, the photolithography step for forming a resist pattern can be performed twice and the SiO 2 on the side wall of the gate electrode can be formed. _{The number} of steps for forming the _two films can be reduced, and the steps can be simplified. Further, since the number of steps of forming the SiO ₂ film on the side wall of the gate electrode can be reduced, it is possible to reduce the factor of process variation and obtain an LDD structure with good reproducibility.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a second embodiment of the present invention.

3A to 3D are process cross-sectional views showing a conventional forming method.

FIG. 4 is a process cross-sectional view showing an application example of a CMOS transistor of a conventional method.

[Explanation of symbols]

 21, 31 Substrate 22, 33 Gate electrode 23, 37, 40 High concentration impurity 24, 38, 41 Low concentration impurity 25, 42 High concentration diffusion region 26, 43 Low concentration diffusion region

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 8617-4M H01L 21/265 F 8617-4ML

Claims (1)

[Claims] 1. A method of forming an LDD structure of a MOS transistor, comprising: (a) implanting an impurity having a higher concentration than a vertical direction of a substrate by an ion implantation method after forming a gate electrode; and (b) rotating the substrate. A method of forming an LDD structure of a MOS transistor, which comprises performing a step of implanting a low concentration impurity from an oblique direction by an ion implantation method.