JPH05120801A - Synchronizing position deviation compensating circuit - Google Patents

Abstract

PURPOSE:To compensate the deviation of synchronization between the head of input data and a gate signal by inserting the number of bits corresponding to the deviation between a synchronizing pattern and the gate signal before the synchronizing pattern. CONSTITUTION:A detecting means 111 detects a prescribed synchronizing bit pattern from input data to send the detection signal. A counting means 112 performs the counting operation synchronously with input of input data in accordance with the detection signal and the gate signal indicating an effective range of input data and counts the number of bits corresponding to the timing deviation between input of the gate signal and the input of the synchronizing bit pattern. In accordance with the counted result, a correction data generating means 113 generates correction data where the number of bits corresponding to the timing deviation are inserted before the synchronizing bit pattern of input data. A switching means 114 switches data, which is sent in accordance with input of the detection signal, from input data to correction data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides input data into M bits, and divides N bits into G bits (Grou (Grou)).
(p Coded Recording) The present invention relates to a synchronization position deviation compensating circuit when recording on a recording medium after converting to coded data.

In recent years, the capacity of magnetic recording devices has increased and the recording density has increased, and along with this, as a recording / reproducing system for magnetic recording media, the above-mentioned GCR has been adopted.
A modulation / demodulation method using a code has been generalized.

For example, 1 / 7R which is a kind of GCR code
The LLC (Run Length Limited Code) method divides the input data into 2 bits, and refers to the last bit of the conversion result of the previous section and the following 2 bits to convert the 2 bits to be converted.
Bits are converted into 3-bit codes to obtain coded data in which the continuous length of bits having the same value is limited to 1 to 7.

[0004]

2. Description of the Related Art FIG. 5 shows an example of a conversion table used for the above-mentioned 1/7 RLLC modulation. In this conversion table, the column indicated by the symbol "Y3 '" indicates the last bit of the conversion result of the preceding delimiter, the column indicated by the symbols "D1, D2" indicates the data to be converted, and the symbol "D3, D4" ] Indicates the subsequent data, and the columns indicated by the symbols “Y1, Y2, Y3” indicate the code data after conversion. Further, in the “D3, D4” column of this conversion table, the symbol “X” indicates that the corresponding bit may be either logical “0” or logical “1”, and the symbol “*” indicates It indicates that the 2-bit combination to be performed is not "00".

Conventionally, the modulation circuit recognizes the range of the write data according to the write gate signal WGT output from the disk controller side, and performs the conversion process based on the conversion table described above. Therefore, the bit at the rising edge of the write gate signal WGT described above is used as the leading bit to determine the bit delimiter for the conversion process.

[0006]

By the way, as a method of evaluating the recording / reproducing ability of a magnetic disk device, the worst pattern, which is generally difficult to read, is written on a magnetic disk, and the amplitude is attenuated when this is read. There is also a method of evaluating the margin size allowed for the phase shift.

In this case, the test device generates write data which is converted into the above-mentioned worst pattern by the conversion process to the GCR code, and the write data is input to the magnetic disk device to perform the write process. After that, the recorded data is read while changing the reading condition to check whether the original write data is reproduced.

On the other hand, in the above-described conventional modulation circuit, the bit delimiter position at the time of conversion into the GCR code changes due to the deviation of the input timing between the write gate signal WGT and the write data, and therefore the same. The same GCR code string is not always obtained according to the input of the write data.

For example, if the write gate signal WGT rises at different timings as shown in FIGS. 6B and 6D when the write data shown in FIG. Since the delimiter position changes, the GCR code strings are converted into different GCR code strings, as shown in FIGS. 6 (c) and 6 (e).

However, when demodulating the data recorded on the magnetic disk, the same bit division as that used at the time of modulation is used. Therefore, reading corresponding to the conversion results shown in FIGS. 6C and 6E, respectively. Since the same data is demodulated from both data, there is no problem in normal use of this magnetic disk device.

However, even if a bit pattern that should correspond to the worst pattern is input as the write data, the worst pattern may not be obtained depending on the timing of the write gate signal WGT. Could not be evaluated accurately.

Here, the above-mentioned timing deviation between the write data and the write gate signal WGT is caused by a delay time due to a circuit element or a cable constituting the disk control device (or the test device for performance evaluation) and the magnetic disk device. The optimum timing of the write data and the write gate signal WGT differs depending on the configuration of the modulation circuit. Therefore, it is difficult to compensate the above-mentioned timing deviation by defining the timing between the performance evaluation test apparatus and the modulation circuit of the magnetic disk apparatus.

It is an object of the present invention to provide a synchronization position deviation compensating circuit for compensating for the synchronization between the head of input data and a gate signal.

[0014]

FIG. 1 is a block diagram showing the principle of the present invention. According to the present invention, a detection unit 111 that detects a predetermined synchronization bit pattern from input data that is sequentially input bit by bit and sends a detection signal indicating that the synchronization bit pattern has been detected, and a range of valid input data are provided. Counting means 112 for counting the number of bits corresponding to the timing difference between the input of the gate signal and the input of the synchronous bit pattern by performing the counting operation in synchronization with the input of the input data according to the gate signal and the detection signal shown. , Correction data generating means 113 for generating correction data in which a corresponding number of bits are inserted before the synchronization bit pattern of the input data according to the counting result by the counting means 112, and for outputting in response to the input of the detection signal. And a switching means 114 for switching the data from the input data to the correction data.

[0015]

According to the present invention, the counting means 112 counts the number of bits of input data from the input of the gate signal to the input of the detection signal from the detection means 111.
Deviation of input timing between gate signal and sync pattern,
That is, it is possible to evaluate the magnitude of the synchronization deviation between the gate signal and the beginning of the input data. That is, as the count value of the counting means 112 at the time when the detection signal is input, the above-mentioned synchronization deviation between the gate signal and the beginning of the input data can be obtained.

Therefore, according to the counting result by the counting means 112, the correction data generating means 113 inserts an appropriate number of bits before the synchronization pattern of the input data, so that the synchronization with the gate signal is compensated. The correction data can be obtained, and this correction data is used as the switching means 11.
4, the data is sent to a device at a subsequent stage such as a modulation circuit of the magnetic recording device.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 shows the configuration of an embodiment of the synchronization position deviation compensating circuit of the present invention.

Here, as shown in FIG. 3, the normal magnetic disk format is a variable frequency oscillator VF for generating a read clock following a gap separating each sector.
Clock sync pattern for synchronizing O VFO SYNC.
And a synchronous byte SB for data synchronization and a data area or an identification information (ID) area.

According to this format, the write data to the magnetic disk is the clock synchronization pattern VFO described above.
SYNC. (For example, hexadecimal number "00") and synchronous byte SB (for example, hexadecimal number "19") are followed by data (for example, hexadecimal number "AA ...") or identification information. ..

The disk controller (not shown) is
The write gate signal corresponding to the gate signal shown in FIG. 1 is almost synchronized with the output of the clock synchronization pattern VFO SYNC.
WGT is set to logic "1" and set to logic "0" at the end of data to indicate the range of valid write data.

Such write data is serially input as input data to the shift register 201 having an 8-bit capacity shown in FIG. 2 in synchronization with the write clock signal WCLK.

Further, the above-mentioned write gate signal WGT is inverted and input to the clear terminal of the shift register 201, and the shift synchronized with the write clock signal WCLK is generated in response to the rising of the write gate signal WGT. It is configured to start the operation and convert serial input data into 8-bit parallel data.

Further, in FIG. 2, eight bit determination circuits (indicated by the symbol "&" in FIG. 2) 211 _{1 to} 21 ₁
Each bit of the synchronous byte SB is set in advance in each of 1 ₈ and these bit determination circuits 211
_{1 to} 21 ₁₈ are each bit of the parallel data held in the shift register 201 and the synchronous byte
The configuration is such that each match with the corresponding bit of SB is determined.

Further, these bit decision circuits 211 ₁ ...
The output of 211 ₈ is sent to JK via AND gate 212.
Information that the JK type flip-flop 213 has detected the synchronous byte SB until it is input to the input terminal J of the type flip-flop 213 and is cleared by the write gate signal WGT inverted and input to the clear terminal. Is configured to hold.

That is, the shift register 201, the bit determination circuits 211 _{1 to} 211 ₈ , the AND gate 212, and J.
By the K-type flip-flop 213, the detection means 11
The function 1 has been realized, and the above-mentioned synchronous byte SB is detected as a synchronization pattern.

The JK type flip-flop 2 described above is also used.
The inverted output IQ of 13 is inputted to the two input terminals J and K of the JK type flip-flop 221. This JK type flip-flop 221 is synchronized by the detecting means 111 described above from the rising of the write gate signal WGT. Until the NAS byte SB is detected, the output inversion operation is performed in synchronization with the write clock signal WCLK.

That is, this JK type flip-flop 2
21 operates as a 1-bit counter and is configured to count the number of bits from the rising of the write gate signal WGT corresponding to the gate signal to the detection of the synchronous byte SB. Has been realized. Here, the synchronous byte from the beginning of the input data
Since the position of the bit delimiter in the 1 / 7RLLC method is determined depending on whether the number of bits up to SB is an even number or an odd number, in this case, the input data and the gate are determined by the counting result by the JK flip-flop 221. The synchronization deviation with the signal can be evaluated.

The most significant bit of the output of the shift register 201 described above is input to the D-type flip-flop 231a and is synchronized with the write clock signal WCLK in the D of the next stage.
The configuration is transmitted to the type flip-flop 231b.

The output of the D-type flip-flop 231a is the inverted output of the JK-type flip-flop 221 described above.
It is input to the AND gate 232a together with IQ, and the output of the D-type flip-flop 231b is output together with the output Q of the JK-type flip-flop 221 to the AND gate 232.
It is input to 32b.

That is, the JK type flip-flop 221
When the inversion output IQ of is a logic "1" and the synchronization deviation is an even number bit, the D-type flip-flop 231
On the other hand, the output of the D-type flip-flop 231b is validated and is output via the OR gate 233 when the output of a is valid, and conversely, when the synchronization shift is an odd bit.

Since the output of the D-type flip-flop 231b is the output of the D-type flip-flop 231a delayed by one clock, the output of the synchronization shift is an odd number of bits. From the output of the D-type flip-flop 231a to the D-type flip-flop 231b
Synchronous byte by switching the output of
1-bit data is inserted before SB.

In this way, the two D-type flip-flops 231a and 231b and the two AND gates 232.
With a and 232b and the OR gate 233, it is possible to insert the bit corresponding to the synchronization deviation obtained by the counting means 112 to generate the correction data and perform the function of the correction data generating means 113.

Further, in FIG. 2, the switching means 114 is
Two AND gates 241a and 241b and an OR gate 2
The OR gate 242 obtains the logical sum of the outputs of the two AND gates 241a and 241b and sends it as write data to a modulation circuit (not shown).

These AND gates 241a and 241b
The output of the OR gate 233 and the output of the D-type flip-flop 231a described above are input to one of the input terminals of the JK type flip-flop 2 and the other, respectively.
The output Q of 13 and the inverted output IQ are input.

Therefore, until the detecting means 111 detects the synchronous byte SB, the output of the D-type flip-flop 231a input to the AND gate 241a is valid and is sent as it is to the modulation circuit as write data. It On the other hand, after the synchronous byte SB is detected, the above-mentioned JK flip-flop 213 holds information to that effect, so that the correction data obtained by the correction data generating means 113 is valid and It is sent to the modulation circuit as embedded data.

Here, instead of the most significant bit of the output of the shift register 201, the D-type flip-flop 231a.
By inputting the output of 1 to the switching means 114, the delay of 1 bit by the JK type flip-flop 213 is corrected.

In this way, 1 bit is inserted before the synchronous byte SB depending on whether the shift of the synchronization position between the head of the input data and the write gate signal WGT is an even bit or an odd bit. It is possible to compensate for the above-mentioned synchronization deviation.

Thus, the write data and the write gate signal
Regardless of the input timing with WGT, the number of consecutive logical "0" bits before the synchronous byte SB corresponding to the synchronization pattern can be unified to an even number.

Therefore, by applying the synchronous position deviation compensating circuit of the present invention to the modulating circuit of the magnetic disk device, it is possible to prevent the fluctuation of the bit delimiter position in the modulating circuit and input the conversion result by this modulating circuit. It can be unique to the write data. In this case, if the bit pattern corresponding to the worst pattern is input through the synchronization position deviation compensating circuit, the modulating circuit can surely obtain the worst pattern, and the performance of the magnetic disk device can be accurately evaluated. You can

By the way, in order to prevent the fluctuation of the bit delimiter position in the modulation circuit, it is sufficient that the number of consecutive bits of logic "0" before the synchronization pattern is even or odd. The circuit may have a configuration in which the number of bits is unified to an odd number.

In this case, in the correction data generating means 113, the output of the D-type flip-flop 231a is input to the AND gate 232b, and the D-type flip-flop 231 is input.
The output of b may be input to the AND gate 232a, and when the number of bits before the synchronous byte SB is an even number, one bit may be inserted before the synchronous byte SB.

When the synchronous position deviation compensating circuit shown in FIG. 2 is applied, in order to detect the synchronous pattern and hold the detection result in the JK type flip-flop 213,
Since the write data sent to the modulation circuit is delayed by 9 bits as compared with the original write data, the format efficiency may decrease.

In order to minimize such delay,
The first bit of the synchronous byte SB may be set to logic "1", and the detecting means 111 may detect the first bit as a synchronization pattern.

For example, as shown in FIG. 4, a D-type flip-flop 202 which is a 1-bit shift register is provided in place of the 8-bit shift register 201 shown in FIG. May be input to the input terminal J of the JK type flip-flop 213 and the D type flip-flop 231a of the correction data generating means 113 as it is.

In this case, the D-type flip-flop 202
Since the output of is the detection result of the bit having the logic "1" as it is, the D-type flip-flop 202 and the JK-type flip-flop 213 can perform the function of the detecting means 111 and detect the synchronization pattern. Therefore, the delay of the write data caused by this can be suppressed to 2 bits.

Since the synchronous byte SB can be freely set at the time of performance evaluation of the magnetic disk device, as described above, the synchronous byte SB having the first 1 bit as a logical "1" can also be set. There is no problem at all when the write data is input to the modulation circuit via the synchronization position deviation compensating circuit shown in FIG. 2 or 4.

Further, as shown in FIG. 4, the selector 251
Is provided, and one of the output of the switching means 114 and the original write data is selected according to the test signal indicating whether or not the performance is being evaluated, and the selected write data is sent to the modulation circuit. Good.

In this case, except when performing performance evaluation,
It is possible to directly input the write data to the modulation circuit by disconnecting the synchronization position deviation compensation circuit. As a result, even if the synchronous byte SB actually used in the state of being delivered to the customer cannot be specified, the detection means 111 determines that the synchronization pattern is not detected,
It is possible to prevent the write data from being sent to the modulation circuit forever.

The synchronous position deviation compensating circuit of the present invention is
Not limited to the 1/7 RLLC method described above, write data
The present invention can be applied to a modulation circuit using a GCR code that is coded by dividing each bit.

In this case, the counting means 112 may be constructed using the counter 222 capable of counting up to the numerical value "m". In addition, the correction data generating means 113 connects m D-type flip-flops in series to sequentially transmit the input data to the next stage, and the selector outputs these Ds in accordance with the counting result by the counter 222 described above. The configuration may be such that any one of the outputs of the flip flops is selected.

[0051]

As described above, according to the present invention, by inserting the number of bits according to the shift between the sync pattern and the gate signal before the sync pattern, the synchronization between the head of the input data and the gate signal is achieved. The deviation can be compensated. Therefore, by applying the modulation circuit of the magnetic disk device using the GCR code, it is possible to prevent the variation of the bit delimiter position and to make the modulation pattern corresponding to the write data unique, and the worst pattern is used. It is possible to accurately evaluate the performance.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a synchronization position deviation compensating circuit of the present invention.

FIG. 3 is a diagram showing an example of a format configuration of a magnetic disk.

FIG. 4 is a block diagram of another embodiment of the synchronization position deviation compensating circuit of the present invention.

FIG. 5 is a diagram showing an example of a conversion table used for 1/7 RLLC modulation.

FIG. 6 is a diagram showing an example of a result of modulation by a conventional modulation circuit.

[Explanation of symbols]

 111 detection means 112 counting means 113 correction data generation means 114 switching means 201 shift register 211 bit determination circuit (&) 212,232,241 AND gate 213,221 JK type flip-flop 202,231 D type flip-flop 233,242 OR gate 251 selector

Claims (1)

[Claims] 1. A detection means (111) for detecting a predetermined sync bit pattern from input data sequentially input bit by bit and sending a detection signal indicating that the sync bit pattern has been detected, and a valid input. A bit corresponding to a timing shift between the input of the gate signal and the input of the synchronous bit pattern by performing a counting operation in synchronization with the input of the input data according to a gate signal indicating a range of data and the detection signal. Counting means (112) for counting the number, and correction data generation for generating correction data in which a corresponding number of bits are inserted before the synchronization bit pattern of the input data according to the counting result by the counting means (112). Means (113), and switching means (1) for switching the data to be transmitted from the input data to the correction data in response to the input of the detection signal.
14) A synchronous position deviation compensating circuit comprising: