JPH05120321A - Method for operating matrix calculation - Google Patents

Abstract

PURPOSE:To operate matrix calculation by using parallel processors in an SIMD system. CONSTITUTION:Circuits composed of at least one memory 100 and one processor element (operation processing circuit) 200 are parallelly arranged. The respective processor elements 200 can receive data from both adjacent memories as well in addition to the input/output of the correspondent memory 100. Thus, the data stored in the adjacent memories can be operated as well. By using these circuits, the matrix calculation is operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix calculation method particularly effective in video signal processing.

[0002]

2. Description of the Related Art A plurality of unit arithmetic circuits are controlled by a single control signal (SIMD = single Install).
A parallel processor of the section multiple data) system is a circuit in which a plurality of processor elements are arranged in parallel, a common instruction (control) signal is given to all the processor elements, and each processor element performs the same arithmetic processing. is there.

A circuit configuration of a typical SIMD parallel processor is shown in FIGS. In FIG. 1, a circuit including one memory 100 and one processor element (arithmetic processing circuit) 200 is arranged in parallel. In each processor element (arithmetic processing circuit), in addition to input / output to / from the corresponding memory, data can be received from the memories on both sides. As a result, the data stored in the adjacent memory can be processed.

A detailed view of the processor element (arithmetic processing circuit) in FIG. 1 is shown in FIG. In FIG. 2, the data from the output M of the corresponding memory (the m-th memory for the m-th processor element (arithmetic processing circuit)), the data from the output L of the memory (m-1th memory) on the left side, And the output R of the memory next to the right (m + 1st memory)
The data from is input to the multiplier 20 and the 2-input selector (the other input is 0) 30 via the data bus 10.
The multiplier 20 multiplies the coefficient read from the coefficient memory 40.

The 2-input selector 30 receives a value from the data bus 10 when it is 1 and 0 when it is 0 according to the selection signal (0, 1) read from the addition input selector memory 50.
Is supplied to the adder 60.

Therefore, if the signal read from the addition input selector memory 50 is 1, (data read from the mth memory, the m-1th memory, or the m + 1th memory) .times. (From the coefficient memory) (Read coefficient) + (data read from the mth memory, or the m-1th memory, or the m + 1th memory) is calculated, and the input M of the mth memory is input via the data bus 10. By inputting into, the above-mentioned multiplication and addition result can be stored in the m-th memory.

If the signal read from the addition input selector memory 50 is 0, (data read from the mth memory, the m-1th memory, or the m + 1th memory) * (from the coefficient memory) By calculating the read coefficient) and inputting it to the input M of the mth memory via the data bus 10, the above multiplication result can be stored in the mth memory.

In FIG. 2, address control of the coefficient memory 40, address control of the addition input selector memory 50, control of which memory is input to the multiplier 20 (via the data bus), and Data input from any memory (via data bus) 2
Control of whether to input to the input selector 30 is performed by a common control signal (arithmetic processing control signal of FIG. 1) in all the processor elements (arithmetic processing circuits) 200.

In FIG. 1, address control of the memory 100 (that is, designation of an address in which data to be output to the output M is stored, designation of an address to store data to be input to the input M, data to be output to the output L). The designation of the stored address and the designation of the stored address of the data to be output to the output R) are performed by a common control signal (address control signal) in all the processor elements (arithmetic processing circuits) 200.

The memory 100 of FIG. 1 and the coefficient memory 4 of FIG.
There is also a configuration in which 0 and the addition input selector memory 50 are integrated into one memory. In addition, as hardware, there is one in which only the adder 60 is built in the processor element (arithmetic processing circuit) 200. In this case, in order to perform the multiplication, the partial product (logical sum of the multiplier and the multiplicand) is cumulatively added by the adder 60, which has a disadvantage that the number of operation cycles becomes long. The same operation as the circuit shown in can be performed.

In video signal processing, since the same arithmetic processing is often performed on all pixels, the SIMD method can be sufficiently applied and there is no inconvenience. In the SIMD system, since the instructions (the arithmetic processing control signal and the address control signal in FIG. 1) are common, there is an advantage that only one control circuit needs to give the instruction and the circuit scale can be reduced.

However, in the video signal processing, some pixels may not perform the same arithmetic processing. That is, a series of four sets of input pixel data

[Equation 1] 4 × 4 constant matrix

[Equation 2] And each multiply

[Equation 3] There is also a process to perform. .

As an example of image processing in which such a series of pixels is divided into a plurality of sets, and pixel data in each set is regarded as one vector and multiplication with a fixed coefficient matrix is performed, a discrete cosine transform (DCT) is used. = Discrete C
osine Transform).

However, regarding such matrix calculation, a calculation method for easily performing this has not been known.

[0015]

A problem to be solved by the present invention is that an arithmetic method for easily performing matrix calculation by using a parallel processor of a system which conventionally controls a plurality of unit arithmetic circuits with a single control signal. Was not known.

[0016]

SUMMARY OF THE INVENTION The present invention comprises at least one
A plurality of unit arithmetic circuits each including one memory and one processor element capable of performing one multiplication and addition are arranged in parallel. In each of the above processor elements, in addition to the input / output to / from the corresponding memory, both adjacent memory Also has a configuration capable of receiving data, and stores a series of input data in a corresponding memory sequentially for a parallel processor of a method of controlling the plurality of unit arithmetic circuits with a single control signal. , This series of input data is divided into k sets, the input data in each set is regarded as one k-order vector, and multiplication with a k × k constant matrix [L i, j] is performed. First, nk + m (n and m are 0
In the (k-1 natural number) th processor element, an instruction m for sequentially multiplying [L (i + m) mod (k), 1] by the input data (Ank + m) stored in the corresponding memory
py (i) (i = 0 to k−1) is sequentially given to the parallel processors to be calculated, and secondly, (data stored in the corresponding memory (hth memory)) + Vh × (adjacent memory) (Data stored in h-1 or h + 1th memory) (however, if hmod (k) = 0, Vh = 0, otherwise, Vh = 1) Thirdly, Wh × (data stored in the corresponding memory (hth memory)) + Yh × (adjacent memory (h + 1, or h−1) opposite to the above add1 is calculated by the processor. Data stored in the second memory) (however, when hmod (k) = k−1, Wh = 1,
Yh = 0, otherwise Wh = 0, Yh = 1) The instruction add2 is given to the parallel processor multiple times for calculation, and fourth, the instruction add1 is given to the parallel processor for calculation. This is a calculation method.

[0017]

According to this, by using a parallel processor of a system for controlling a plurality of unit arithmetic circuits with a single control signal,
The matrix calculation can be easily performed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS For example, a plurality of circuits each including one memory and one processor element (arithmetic processing circuit) capable of performing multiplication and addition are arranged in parallel, and each processor element (arithmetic processing circuit) corresponds to each circuit. In addition to the input / output to / from the memory, a SIMD type parallel processor having a structure capable of receiving data from the memories on both sides is provided.

In this parallel processor, a series of input data ... An-1, Bn-1, Cn-1, Dn-1, An, Bn, Cn, Dn, An +.
1, Bn + 1, Cn + 1, Dn + 1, ..., 4 (n-1) th memory, 4 (n-1) + 1th memory, 4 (n-
1) + 2nd memory, 4 (n-1) + 3rd memory, 4nth memory, 4n + 1th memory, 4n +
2nd memory, 4n + 3rd memory, 4 (n + 1)
Th memory, 4 (n + 1) + 1th memory, 4 (n
+1) + 2nd memory, 4 (n + 1) + 3rd memory ,.

This stored series of input data is converted into 4 (=
k) split into sets, and the input data in each set is a quaternary vector

[Equation 4] And a 4 × 4 constant matrix

[Equation 5] Multiplication with

[Equation 6] I do.

That is, in the 4, 8, 12, 16 ... Processor elements (arithmetic processing circuits), L i, 0
(E 0 when i = 0, F 0 when i = 1, G 0 when i = 2,
When i = 3, H 0) is multiplied by the input data A 4, A 8, A 12, A 16 ...
i, 0 × A 4, L i, 0 × A 8, L i, 0 × A 12, L i, 0 × A
16 ...)

At the same time, 5, 9, 13, 17 ...
In the th processor element (arithmetic processing circuit), L
(i + 1) mod (4), 1 (F 1 when i = 0, G 1 when i = 1, i
= 2, H 1 when i = 3, E 1) when i = 3, and the input data A5, A9, A13, A17 ...
・ Multiply with (L (i + 1) mod (4), 1 × A 5, L (i + 1) mod
(4), 1 × A 9, L (i + 1) mod (4), 1 × A 13, L (i + 1) mod
(4), 1 × A17 ...)

At the same time, 6, 10, 14, 18 ...
-In the th processor element (arithmetic processing circuit),
L (i + 2) mod (4), 2 (G 2 when i = 0, H 2 when i = 1,
E 2 when i = 2, F 2 when i = 3), and the input data A 6, A 10, A 14, A 18 stored in the corresponding memory.
..Multiplication with (L (i + 2) mod (4), 2 × A 6, L (i + 2) mod
(4), 2 × A10, L (i + 2) mod (4), 2 × A14, L (i + 2) mod
(4), 2 × A18 ...)

At the same time, 7, 11, 15, 1
9th, ... th processor element (arithmetic processing circuit)
Then, L (i + 3) mod (4), 3 (H 3 when i = 0, E 3 when i = 1, F 3 when i = 2, G 3 when i = 3) correspond to Input data A 7, A 11, A 15, stored in the memory
Multiplying with A19 ... (L (i + 3) mod (4), 3 × A 7, L (i +
3) mod (4), 3 × A11, L (i + 3) mod (4), 3 × A15, L (i + 3)
An instruction mpy (i) (i =) for performing mod (4), 3 × A19 ...
0 to 3) are sequentially given to a parallel processor to be calculated.

Next, (data stored in the h-th memory) + V h × (data stored in the (h−1) -th memory) (however, when hmod (4) = 0, V h = 0, In the other cases, the instruction add1 for performing Vh = 1) is given to the parallel processor three times to perform calculation.

Then, W h × (data stored in the h-th memory) + Y h × (data stored in the h + 1-th memory) (however, when hmod (4) = 3, W h =
1, Y h = 0, otherwise Wh = 0, Y h = 1) The instruction add2 is given to the parallel processor three times for calculation. Finally, the instruction add1 is given to the parallel processor once to be calculated.

As a result, multiplication with a 4 × 4 constant matrix is performed, and according to this calculation method, the number of calculation cycles can be reduced as compared with the conventional method.

The case of k = 4 will be specifically described below. That is, a series of input data ... An-1, Bn-1, Cn-
1, Dn-1, An, Bn, Cn, Dn, An + 1, Bn + 1, Cn + 1, Dn + 1, ...
.., ... 4 (n-1) th memory, 4 (n-)
1) + 1st memory, 4 (n-1) + 2nd memory, 4 (n-1) + 3rd memory, 4nth memory, 4n + 1th memory, 4n + 2nd memory, 4
n + 3rd memory, 4 (n + 1) th memory, 4
(N + 1) + 1th memory, 4 (n + 1) + 2nd memory, 4 (n + 1) + 3rd memory ...

This stored series of input data is converted into 4 (=
k) split into sets, and the input data in each set is a quaternary vector

[Equation 7] And a 4 × 4 constant matrix

[Equation 8] Multiplication with

[Equation 9] The case of performing will be described.

In this case, the memory 100 of FIG. 1 may be a memory having a size of 5 words (addresses 0 to 4). The coefficient memory 40 of FIG. 2 may be a memory having a size of 6 words (addresses 0 to 5). The addition input selector memory 50 has 3 words (0 to 2
A memory with the size of the address is sufficient. For the description, the circuit diagram 3 that embodies FIG. 2 will be used. That is, FIG.
A case will be described in which the parallel processor using FIG. 3 as the processor element (arithmetic processing circuit) 200 performs arithmetic. The L / R selector control signal, the address designating signal of the coefficient memory, and the address designating signal of the addition input selector memory in FIG. 3 are the arithmetic processing control signals referred to in FIG.

The coefficient memory 40 and the addition input selector memory 50 of the 4th, 8th, 12th, ... Processor elements (arithmetic processing circuits) are set in advance as shown in FIG. 5,9,13 ... th, 6,10,14 ...
The seventh, seventh, eleventh, fifteenth, ... Processor element (arithmetic processing circuit) 200 is similarly set as shown in FIGS. 5, 6, and 7.

A series of input data ... An-1, Bn-1, Cn-
1, Dn-1, An, Bn, Cn, Dn, An + 1, Bn + 1, Cn + 1, Dn + 1, ...
.. is the 4 (n-1) th memory, 4 (n-)
1) + 1st memory, 4 (n-1) + 2nd memory, 4 (n-1) + 3rd memory, 4nth memory, 4n + 1th memory, 4n + 2nd memory, 4
n + 3rd memory, 4 (n + 1) th memory, 4
(N + 1) + 1st memory, 4 (n + 1) + 2nd memory, 4 (n + 1) + 3rd memory, ...

Therefore, the 4nth memory in FIG.
The contents of the first memory, 4n + 2nd memory, and 4n + 3th memory are as shown in Table 2 of FIG. However,
In Table 2 and the following description, An, Bn, Cn,
Let Dn be A, B, C and D. Also, 4n to 4n +
The contents of the memories other than the third one are the same as in Table 2. In the following description, the 4n to 4n + third part will be described, but the other parts are also the same.

In the first cycle, the signals shown in the first cycle of Table 1 of FIG. 8 are given as the control signals (address control signal and arithmetic processing control signal of FIG. 1) from the control circuit (not shown). Therefore, in the 4nth processor element (arithmetic processing circuit), (4nth coefficient memory 0 address value) × (4nth memory 0 address value) + 0 = E0
× A is calculated and stored in the 1st address of the 4nth memory. The same applies to the 4n + 1 to 4n + third, and 1
At the end of the cycle, the table shown in FIG.

In the 2nd to 4th cycles, the signals shown in the 2nd to 4th cycles of Table 1 are given from the control circuit, and at the end of each cycle, the 4th to 6th tables of FIGS. 11 to 13 are obtained. At the 5th cycle, the control circuit gives the signal shown at the 5th cycle of Table 1. Therefore, in the 4n-th processor element (arithmetic processing circuit), (value of 4n-th coefficient memory address 4) × (value of 4n-th memory address 2) + 0 = H 0 ×
A is calculated and stored in the 2nd address of the 4nth memory.

In the 4n + 1th processor element (arithmetic processing circuit), (4n + 1th coefficient memory 4th address value) × (4n + 1th memory 2nd address value) + (4n
The value of the 1st memory address 1) = E 0 × A + E 1 × B is calculated and stored in the memory address 2 of 4n + 1. 4n +
The same applies to the 2nd, 4n + 3rd, and Table 7 in FIG. 14 is obtained at the end of the fifth cycle.

Also in the 6th and 7th cycles, the signals shown in the 6th and 7th cycles of Table 1 are given from the control circuit, and at the end of each cycle, the tables shown in FIGS. Table 10 in FIG. 17 shows the contents of the memory in which unused data is replaced with X in the eighth and subsequent cycles.

At the 8th cycle, the control circuit gives the signal shown at the 8th cycle of Table 1. Therefore, in the 4n + 3rd processor element (arithmetic processing circuit), (4n +
Value of third coefficient memory 5) × (4n + value of third memory 3) + 0 = F 1 × B + F 2 × C + F 3 × D
Is calculated and stored in the 4n + 3rd memory address 3.

In the 4n + 2nd processor element (arithmetic processing circuit), (4n + value of 5th coefficient memory address 5) × (4n + value of 2nd memory address 3) + (4n
+ Value of third memory address 4) = 0 × (4n + value of second memory address 3) + (4n + value of third memory address 4) = E 0 × A + E 1 × B + E 2 × C + E 3 × D is calculated. 4n + 2 is stored in the third memory address. Four
The same applies to the nth, 4n + 1th, and the end of the eighth cycle results in Table 11 in FIG.

In the 9th and 10th cycles, the signals shown in the 9th and 10th cycles of Table 1 are given from the control circuit, so that the 12th and 13th tables of FIGS. 19 and 20 are obtained at the end of each cycle. The contents of the memory obtained by replacing the unused data in the 11th cycle with X are shown in Table 14 of FIG.

In the 11th cycle, the control circuit outputs 1 in Table 1
The signal shown in the first cycle is given. Therefore, in the 4nth processor element (arithmetic processing circuit), (value of 4nth coefficient memory address 4) × (value of 4nth memory address 1) + 0 = E 0 × A + E 1 × B + E 2 × C + E 3 ×
D is calculated and stored in the 0th address of the 4nth memory.

In the 4n + 1th processor element (arithmetic processing circuit), (4n + 1th coefficient memory 4th address value) × (4n + 1th memory 1st address value) + (4n
Value of the 4th memory) = F 0 × A + F 1 × B + F 2
× C + F 3 × D is calculated and stored in the memory address 0 of 4n + 1. The same applies to the 4n + 2, 4n + 3th, and when the 11th cycle ends, the table shown in FIG.

Therefore, after completion of the 11th cycle, the data at address 0 of each memory is taken out from the output terminal not shown in FIG.

[Equation 10] Can be taken out.

Thus, according to the above method, the matrix calculation can be easily performed by using the parallel processor of the method of controlling a plurality of unit arithmetic circuits with a single control signal.

In the circuit configuration shown in FIG. 3, the instruction mpy (i) (i = 0 to k-1) and the instruction add1 are set to 1
You can also do it every time. For example, in the above example (when k = 4), the coefficient memory and the addition input selector memory are set in advance as shown in FIGS. 4 to 7 as described above. By applying the signals shown in Table 16 of FIG. 23 in each cycle, at the end of each cycle, as shown in FIG.
As shown in Tables 17 to 27 of FIG. 34, the operation can be performed in 8 cycles. That is, in this example, the fourth
The instruction mpy (i) (i = 0 to k-1) in Tables to Table 6 and the instruction add1 in Tables 7 to 9 are performed at one time as shown in Tables 19 to 21. ..

As described above, also in this method, the matrix calculation can be easily performed by using the parallel processor of the method of controlling the plurality of unit arithmetic circuits by the single control signal.

In the above description, the image data has been described as an example, but other data may be used.

[0048]

According to the present invention, it becomes possible to easily perform matrix calculation by using a parallel processor which controls a plurality of unit arithmetic circuits by a single control signal. ..

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a parallel processor that implements a calculation method for matrix calculation according to the present invention.

FIG. 2 is a configuration diagram of an example of the processor element.

FIG. 3 is an explanatory diagram of an example of the memory setting.

FIG. 4 is an explanatory diagram of an example of the memory setting.

FIG. 5 is an explanatory diagram of an example of the memory setting.

FIG. 6 is an explanatory diagram of an example of the memory setting.

FIG. 7 is an explanatory diagram of an example of the memory setting.

FIG. 8 is a table in Table 1 for explaining the operation.

FIG. 9 is a second table showing a state in the middle of the process.

FIG. 10 is a diagram of Table 3 showing a state in the middle of the process.

FIG. 11 is a diagram of a fourth table showing an intermediate state.

FIG. 12 is a diagram of Table 5 showing a state in the middle of the process.

FIG. 13 is a diagram of Table 6 showing a state in the middle of the process.

FIG. 14 is a diagram of Table 7 showing a state in the middle of the process.

FIG. 15 is a diagram of Table 8 showing a state in the middle of the process.

FIG. 16 is a diagram of Table 9 showing a state in the middle of the process.

FIG. 17 is a diagram of Table 10 showing a state in the middle of the process.

FIG. 18 is a diagram of Table 11 showing a state in the middle of the process.

FIG. 19 is a diagram of Table 12 showing an intermediate state.

FIG. 20 is a diagram of Table 13 showing a state in the middle of the process.

FIG. 21 is a diagram of Table 14 showing an intermediate state.

FIG. 22 is a diagram of Table 15 showing a state in the middle of the process.

FIG. 23 is a table in Table 16 explaining the operation.

FIG. 24 is a diagram of Table 17 showing a state in the middle of the process.

FIG. 25 is a diagram of Table 18 showing a state in the middle of the process.

FIG. 26 is a chart of Table 19 showing a state in the middle of the process.

FIG. 27 is a diagram of Table 20 showing a state in the middle of the process.

FIG. 28 is a diagram of Table 21 showing an intermediate state.

FIG. 29 is a diagram of Table 22 showing a state in the middle of the process.

FIG. 30 is a table of Table 23 showing a state in the middle of the process.

FIG. 31 is a diagram of Table 24 showing an intermediate state.

FIG. 32 is a diagram of Table 25 showing an intermediate state.

FIG. 33 is a table of Table 26 showing a state in the middle of the process.

FIG. 34 is a diagram of Table 27 showing a state in the middle of the process.

[Explanation of symbols]

 100 memory 200 processor element (arithmetic processing circuit) 10 data bus 20 multiplier 30 2 input selector 40 coefficient memory 50 addition input selector memory 60 adder 60

Claims (1)

[Claims] 1. A plurality of unit arithmetic circuits each including at least one memory and one processor element capable of performing multiplication and addition are arranged in parallel, and each of the processor elements has an input / output circuit to and from a corresponding memory. In addition, it has a structure that can receive data from the memory on both sides, and outputs a series of input data to a parallel processor that controls a plurality of unit arithmetic circuits with a single control signal. While storing in a corresponding memory, this series of input data is divided into k sets, and the input data in each set is regarded as one k-order vector and multiplied by a k × k constant matrix [L i, j]. In the calculation method of the matrix calculation for performing the following, first, in the memory element corresponding to [L (i + m) mod (k), 1] in the nk + m (n, m is a natural number of 0 to k−1) processor element. Stored Input data (Ank +
instruction mpy (i) (i = 0 to k) for sequentially performing multiplication with m)
−1) is sequentially given to the parallel processors to be calculated, and secondly, (data stored in the corresponding memory (hth memory)) + Vh × (adjacent memory (h−1 or h + 1th memory) Data stored in))
(However, when hmod (k) = 0, Vh = 0; otherwise, Vh
The instruction add1 for executing h = 1) is given to the parallel processor a plurality of times to be calculated, and thirdly, Wh × (data stored in the corresponding memory (hth memory)) + Yh × (opposite to the above add1. Data stored in the adjacent memory (h + 1 or h-1th memory) on the side (however, hmod (k) = k-
When 1, Wh = 1, Yh = 0, otherwise Wh = 0,
The operation method of matrix calculation in which the instruction add2 for performing Yh = 1) is given to the parallel processor a plurality of times for calculation, and fourthly, the instruction add1 is given to the parallel processor for calculation.