JPH05120028A - Micro computer device - Google Patents

Abstract

PURPOSE:To generate an object including the high speed operation of a variable and to generate a compact object. CONSTITUTION:In a micro computer device having a specified memory area where data can be read and written at high speed, inputting and analyzing source program information and outputting object information, a means 107 generating function relation information on the call of respective sub-routines in source program information, a means 108 detecting the number of appearing times of all variables used in source program information and generating appearing times information and a means 109 generating variable allocation information as to the variable used in source program information from correlation information and information on the number of the appearing times of the variables are provided. The variables used in source program information are sequentially allocated to a high speed data accessible area from the large number of the appearing times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used to execute a language processing program for a microcomputer having a specific memory area (hereinafter referred to as high speed access memory) in which data can be called or written at high speed by an instruction. To do. The present invention relates to a microcomputer device capable of generating compact objects.

[0002]

2. Description of the Related Art A source input by a language processing program is translated, and a file generated as a result is called an object module (hereinafter referred to as an object).

In a microcomputer, particularly in a single-chip microcomputer, there is a limitation in performance when trying to reduce the cost. Therefore, in the language processing program, it is desired that the object that is the result of the language processing be executed quickly and that the size of the object be small.

Generally, in a microcomputer,
It is common to have a memory area that can be accessed by a short instruction code, and this is called a high-speed access memory.
Since it can be accessed by a short instruction code, the number of instruction bytes can be reduced, and the instruction execution time can be shortened because the instruction fetch and instruction decode can be performed at high speed.

In the conventional language processing program execution method, even if the microcomputer has a high-speed access memory, the high-speed access memory has a smaller memory size than a normal memory, and the allocation to the memory is not considered. , All variables were allocated in normal memory.

[0006]

In the above-described conventional language processing program execution method, since variables are assigned to the normal memory, reading of data from the normal memory,
The speed of writing is much slower than the speed of reading and writing data from the high-speed access memory, and the conventional language processing program execution method cannot generate objects including high-speed variable operations. Furthermore, the object code for reading and writing normal memory data is
It was not possible to generate a compact object because the number of bytes was larger than the written object code.

The present invention solves such a problem. Instead of allocating variables to a normal memory, variables are allocated to a high-speed access memory in descending order of the number of occurrences, and an object including a high-speed variable operation is generated. An object of the present invention is to provide a device that can generate a more compact object.

[0008]

The present invention has a memory area for high-speed reading and writing of data, an input section and an output section, inputs source program information, analyzes it, and outputs object information. In a microcomputer device provided with language processing program executing means, in the language processing program executing means, a correlation information generating section for generating correlation information for calling each subroutine in the source program information, and in the source program information Variable occurrence count information generator that detects the occurrence count of all variables used and generates appearance count information, and variable allocation for variables used in the source program information from the generated correlation information and variable appearance count information It is equipped with a parser that includes a variable allocation information generator that generates information. The features.

[0009]

Operation: Correlation information of each subroutine call in the source program information and appearance frequency information by detecting the appearance frequency of all variables used in the source program information are generated, and the generated correlation information and the variables are generated. Variable allocation information about variables used in the source program information is generated from the appearance frequency information, and variables used in the source program information are allocated to the high-speed data accessible area in descending order of appearance frequency.

As a result, even if all variables cannot be assigned to the high-speed access memory, it is possible to generate an object including a variable operation that is faster than the conventional processing by the language processing program execution method, and it is compact. Objects can be created. Further, since frequently accessed variables are preferentially allocated to the high speed access memory, the execution speed can be improved.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

The embodiment of the present invention has a memory area 100 capable of high-speed reading and writing of data, an input unit 103 and an output unit 105, and is a language for inputting and analyzing source program information and outputting object information. The language processing program executing means 102 is provided with a processing program executing means 102, and in the language processing program executing means 102, a correlation information generating part 107 for generating the correlation information of the call of each subroutine in the source program information, and all the information used in the source program information. A variable appearance number information generation unit 108 for detecting the number of appearances of variables and generating appearance number information, and variable allocation information for variables used in source program information from the generated correlation information and appearance number information of variables. And a syntax analysis unit 104 including a variable allocation information generation unit 109 That.

Next, the operation of the embodiment of the present invention thus constructed will be described.

In the present embodiment, in order to clarify the point of the present invention, it is assumed that there is no recursive call in the routine call in each subroutine, and the variables handled are only the variables in the subroutine.

The processing of the correlation information generation unit 107 and the processing of the variable appearance number information generation unit 108 can be realized by the information generated by the syntax analysis unit of the existing language processing program.

FIG. 2 is an image diagram of bidirectional correlation information for calling each subroutine generated by the correlation information generating unit in the embodiment of the present invention. Name mai
n, [outer 1], etc. are subroutine names.

[0017]

[Outer 1] In this embodiment, the correlation information generation unit 107, the variable appearance count information generation unit 108, and the variable allocation information generation unit 10
A record number indicates a location where the information generated by 9 is stored. The record numbers are assigned sequentially from (1), and (0) indicates that nothing is assigned. Furthermore, the side that calls a routine is called a parent, the called side is called a child, and a routine that does not call a routine is called a leaf function. In the case of FIG. 2, [outer 2] is a child of main and is a parent of [outer 3]. [Outer 3] is a leaf function.

[0018]

[Outside 2]

[0019]

[Outside 3] FIG. 3 is a diagram showing bidirectional correlation information of each subroutine generated from the correlation information generating unit in the embodiment of the present invention. The correlation information includes a subroutine name, variable allocation address information in the subroutine, a parent record number sequence, a child record number sequence, and information of each variable in the subroutine.

FIG. 4 is a diagram showing variable information generated by the variable appearance number information generation unit in the embodiment of the present invention. The information of this variable includes the variable name, the size of the variable, the number of appearances, the record number of the next variable, and the allocation address, and the information of each variable in the subroutine included in the correlation information of the subroutine shown in FIG. Equivalent to. Also,
The allocation address information included in the correlation information of the subroutine is information generated from the allocation address included in the variable information.

FIG. 5 shows the correlation information of the subroutine generated by the correlation information generation unit and the variable appearance number information generation unit when the source program having the correlation information of the contents shown in FIG. 2 is input to the syntax analysis unit. It is a figure which shows the information of each variable in a subroutine.

Looking at the correlation information of the subroutine main stored in the record number (1) to the record number (4), since the sequence of the parent record numbers is (0), it has no parents and children. Since the sequence of record numbers of (5), (11), (15), (20), and (24) is, the subroutines [outer 1], [outer 4], [outer 5], [outer 2], and [outer 3] ] As a child, and variables a, b, and c in the subroutine main, and the sizes of the variables are 2, 2, and 2, and the number of occurrences of each is 4, 3, and 9. Variable size is in bytes.

[0023]

[Outside 4]

[0024]

[Outside 5] First variable record number storage area 501 (hereinafter referred to as "hea")
In d), the record number (21) of the information of the variable having the largest number of appearances is stored. Record number (2
Variable f in the subroutine [outside 2] stored in 1)
The record number of the next variable in the information 11 is the variable f1.
The record number (2
3) is stored.

By referring to the record number of the next variable in the information of each variable, it is possible to refer to each variable in descending order of appearance frequency. Variables with the same number of appearances can be referenced in the order of appearance. The assigned address information in the correlation information of the subroutine and the assigned address in the information of each variable are 0x0000 and 0 as initial values.
x00 is set. Numbers starting with 0x are hexadecimal numbers.

FIG. 6 is a flow chart showing the flow of processing in the variable allocation information generating section of the language processing program executing means of the embodiment of the present invention.

In this embodiment, the correlation information of the subroutine having the contents shown in FIG. 5 and the information of each variable in the subroutine are used as the input information of the variable allocation information generating unit 109.

The variable allocation information generator 109 processes the variables in each subroutine in descending order of the number of appearances, and when determining the allocation address, it starts from the routine including the variable being processed, and the routine main and the leaf function are processed. Processes recursively up to the end.

The correlation information of the subroutine and the information of each variable in the subroutine generated from the correlation information generation unit 107 and the variable appearance number information generation unit 108 are processed by the variable allocation information generation unit 109 in the following procedure. ..

Variable record number initialization processing step 6
01 is a memory area 100 (hereinafter referred to as [outer 6]) that stores the record number of the variable next to the variable being processed.
Initialize with the contents of ad.

[0031]

[Outside 6] In the variable record number determination processing step 602, it is determined whether [outer 6] is (0). The following process
This is done for all variables in each subroutine.

Allocation address information initialization processing step 60
3 initializes a memory area 100 (hereinafter, referred to as "address") that stores the allocation address information of each variable with the allocation address information of each variable in the routine being processed.

In the parent variable allocation address information detection processing step 604, the parent variable allocation address information of the routine being processed is recursively detected and set to address.
(Hereinafter, parent variable allocation address information detection processing step 6
The processing routine name of 04 is [External 7])

[0034]

[Outside 7]

[0035]

[Outside 8] Variable allocation address information detection processing step 605 of child
Automatically recursively detects the variable allocation address information of the child of the routine being processed and sets it to address. (Less than,
The processing routine name of the variable allocation address information detection processing step 605 of the child is [external 8]) The variable allocation address setting processing step 606 is add.
In the addresses that are not allocated by ress, the smallest address to which the size of the variable being processed can be allocated is set as the allocated address of the variable being processed.

Allocation address information setting processing step 607
Adds information corresponding to the allocation address of the variable being processed to the allocation address information of the routine being processed.

Variable record number setting processing step 60
8 sets the record number of the variable next to the variable being processed to [external 6].

Further, in the processing routine [outer 7], the processing is recursively performed up to the routine main in the following procedure.

Parent record number initialization processing step 60
Reference numeral 9 initializes a memory area (hereinafter referred to as “record”) for storing the record number of the parent or child of the routine being processed with the first element of the sequence of record numbers of the parent of the routine being processed.

Parent record number determination processing step 610
Determines whether record is (0). If record is not (0), the process proceeds to the allocation address information detection processing step 611. Otherwise, it is determined that the processing has been completed for all parents of the routine being processed, and the routine proceeds to the processing routine [outer 8].

Allocation address information detection processing step 611
Sets the logical sum of the assigned address information of the address and the record address in the address.

The parent variable allocation address information detecting step 612 recursively calls the processing routine [outer 7] in order to detect the parent variable allocation address information of the routine being processed.

Parent record number setting processing step 613
Sets the next element in the list of parent record numbers of the routine being processed to record.

The processing routine [outer 8] is recursively processed up to the leaf function in the same procedure as the processing routine [outer 7].

Hereinafter, a process of inputting the correlation information of the subroutine having the contents shown in FIG. 5 and the information of each variable in the subroutine to the variable allocation information generation unit 109 and obtaining the allocation address of the variable in each subroutine will be described. To do.
In this embodiment, the memory size of the high speed access memory is set to 1
6 bytes, the allocation address is 0x40 or later, 0 bit of allocation address information of each subroutine is 0x40 of allocation address, 1 bit corresponds to 0x41 of allocation address, and similarly, 15 bits corresponds to 0x4f of allocation address. ..

First, the allocation address of the variable f11 in the routine [outer 2] stored in the record number (21) which is the contents of the head is obtained.

First, the address routine is executed [outer 2].
Is initialized with the allocation address information of, and as the first level, addr is added to the main that is the parent of the routine [outside 2].
The logical sum of the allocation address information of ess and the routine main is set in address.

As a second level, the value of address does not change because there is no parent in the routine main. The same process is performed on the child in the routine [outer 2].

As a result of the processing for the variable f11, addr
The value of ess is 0x0000. Since the size of the variable f11 is 2, the assigned address is 0x40. The assigned address information of the routine [outside 2] is 0x40 address and 0
The 0 bit and the 1 bit, which are the information corresponding to the x41 address, are set to 1 to be 0x0003.

Next, the allocation address of the variable f13 in the routine [outer 2] stored in the record number (23) of the variable next to the variable f11 is obtained. By performing the same processing as the variable, the value of address is 0x0003.
Becomes Since the size of the variable f13 is 2, the assigned address is 0x42. The allocation address information of the routine [outer 2] is 0x00 in which 2 bits and 3 bits which are information corresponding to addresses 0x42 and 0x43 are set to 1.
It becomes 0f.

Thereafter, the same processing is performed for the record number (10).
The results obtained up to this point are the correlation information of the subroutine shown in FIG. 7 and the information of each variable in the subroutine.

Next, the allocation address of the variable p32 in the routine [outer 4] stored in the record number (13) of the variable next to the variable p21 is obtained. By performing the same process as the above variable, the value of address is 0x0031.
Becomes Since the size of the variable p32 is 4, the assigned address is 0x46 instead of 0x41. The assigned address information of the rout [outer 4] is 0x46, 0x47, 0
6 which is the information corresponding to the address x48 and the address 0x49
It becomes 0x03c0 in which 1 bit is set to 7 bit, 7 bit, 8 bit and 9 bit.

Next, the allocation address of the variable p33 in the routine [outer 4] stored in the record number (14) of the variable next to the variable p32 is obtained. By performing the same process as the above variable, the value of address is 0x03f1.
Becomes Since the size of the variable p33 is 2, the assigned address is 0x41. The assigned address information of the routine [outer 4] is 0x03 in which 1 bit and 2 bits which are information corresponding to the 0x41 address and the 0x42 address are set to 1.
It becomes c6.

Thereafter, similar processing is performed up to the record number (2).

Next, the allocation address of the variable b in the routine main stored in the record number (3) of the variable next to the variable a is obtained. By performing the same process as the variable, the value of address becomes 0xffff.
Since the size of the variable b is 2, the variable b cannot be assigned to the high speed access memory. The assigned address information of the routine main remains 0x8030.

Below, the same result is obtained up to the record number (16) in which the information of the last variable is stored, and the final result is the correlation information of the subroutine shown in FIG. 8 and the information of each variable in the subroutine.

From FIG. 8, it can be seen that all variables except the variable b in the routine main, the variable p11 in the routine [outer 1] and the variable p41 in the routine [outer 5] are assigned to the high speed access memory. ..

[0058]

As described above, according to the present invention, even if all variables cannot be assigned to the high speed access memory, the variables are assigned to the high speed access memory in the descending order of the number of occurrences, so that the conventional language processing can be performed. It is possible to generate objects including variable operations that are faster than the program execution method, and compact objects. Furthermore, by allocating variables to the high-speed access memory in the descending order of the number of occurrences rather than in the variable processing order, variables that are frequently accessed are preferentially allocated to the high-speed access memory, further improving execution speed. There is an effect that can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an image of bidirectional correlation information for calling each subroutine, which is generated from a correlation information generation unit in the embodiment of the present invention.

FIG. 3 is a diagram showing bidirectional correlation information of each subroutine generated from a correlation information generation unit in the embodiment of the present invention.

FIG. 4 is a diagram showing variable information generated by a variable appearance number information generation unit in the embodiment of the present invention.

5 is a diagram showing correlation information of a subroutine of the source program having the correlation information having the content shown in FIG. 2 and information of each variable in the subroutine.

FIG. 6 is a flowchart showing the flow of processing in the variable allocation information generation unit of the language processing program execution means of the exemplary embodiment of the present invention.

7 is a diagram showing correlation information of a subroutine performed up to setting of variable allocation addresses stored in the record number (10) shown in FIG. 5 and information of each variable in the subroutine.

FIG. 8 is a diagram showing correlation information of a subroutine in which allocation addresses of all variables shown in FIG. 5 are set and information of each variable in the subroutine.

[Explanation of symbols]

100 memory area 101 input file 102 language processing program execution means 103 input section 104 syntax analysis section 105 output section 106 output file 107 correlation information generation section 108 variable appearance count information generation section 109 variable allocation information generation section 501 record number of the first variable Storage area 601 Variable record number initialization processing step 602 Variable record number determination processing step 603 Allocation address information initialization processing step 604, 612 Parent variable allocation address information detection processing step 605, 617 Child variable allocation address information detection processing Step 606 Variable allocation address setting processing step 607 Allocation address information setting processing step 608 Variable record number setting processing step 609 Parent record number initialization processing step 610 Parent Record number determination processing steps 611,616 allocation address information detection processing step 613 the parent of the record number setting processing step 614 child record number initializing processing step 615 children record number determination processing step 618 child record number setting process step

Claims (1)

[Claims] 1. A language processing program executing means for inputting and analyzing source program information and outputting object information, comprising a memory area capable of high-speed reading and writing of data, an input section and an output section. In the microcomputer device, in the language processing program execution means, a correlation information generation unit that generates correlation information of the call of each subroutine in the source program information, and the number of appearances of all variables used in the source program information. Variable occurrence count information generation unit that detects occurrences and generates appearance count information, and variable allocation information generation that generates variable allocation information for variables used in source program information from the generated correlation information and variable appearance count information And a parsing section including a section Computer equipment.