JPH0511753A - Automatic music player device - Google Patents

Abstract

PURPOSE:To reproduce performance data at a constant tempo by correcting time intervals, among pieces of musical time pattern operation timing, so as to become mutually equivalent with a correction means for performance data, and rectifying performance timing for the performance data memorized in a performance data memory means. CONSTITUTION:ON and OFF conditions in a keyboard KB after starting a memory mode, together with the key codes KC1-KC3 of a key and event interval data, are memorized as performance data in a performance data memory PDM. A tap event in a foot switch 12 is detected, and a time interval, between first and second times after starting a record mode, is set as a standard tap event interval BT. Then interval data among tap events after the second time are corrected, that is, lengthened or shortened so as to become equivalent to the standard tap event interval BT. Event interval data after the second tap event are corrected according to a correction factor for interval data among corresponding tap events.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic musical instrument used in an electronic musical instrument or the like, and more particularly to musical performance data generated by a manual musical performance at a tempo that is not constant and having irregular timing. However, the present invention relates to a device that can be easily corrected so that the performance timing becomes constant and that the performance data can be recorded as automatic performance data that can be reproduced at a constant tempo.

[0002]

2. Description of the Related Art As an automatic performance apparatus, for example, performance data generated by manually playing (manually) playing a keyboard of an electronic musical instrument is stored in a memory as automatic performance data, and the stored automatic performance data is stored. There is a device which produces a performance sound by sequentially reproducing. By the way, the performance for generating performance data to be stored in the automatic performance device is a measure or a beat.
It is necessary to perform at a constant tempo according to a constant timing such as. This is because performance data that is generated by a performance with a non-constant tempo and that is stored with uneven performance timing causes a serious obstacle to later editing such as copying or deleting. Because it brings.

[0003]

However, when the performer is inexperienced, it is difficult to perform at a constant tempo in accordance with a constant timing, which causes unevenness in the performance timing. In addition, if the player tries to play at a certain timing, he cannot concentrate on the performance, which not only causes unevenness in the performance timing but also causes a performance error. In such a case, the performance must be repeated.

In order to solve the above problems, a certain tempo is set on the basis of a performance part that is the most difficult to play, and therefore the performance tempo tends to be slower than other parts, It may be possible to perform at the set tempo, but in this case, with respect to a performance part that is not difficult, there is an inconvenience that it is not possible to grasp a realistic performance feeling at the normal tempo. The present invention has been made in view of the above points, and even if the performance data generated by a manual performance at a tempo that is not constant and having uneven performance timing, the performance timing can be easily fixed. It is an object of the present invention to provide an automatic performance device that can be modified so that the performance data can be recorded as automatic performance data that can be reproduced at a constant tempo.

[0005]

In order to solve the above-mentioned problems, an automatic performance device according to the present invention has a performance means for generating performance data in accordance with a performance operation by a performer, and a performer for taking a beat. Operating means operated by: and performance data storage means for storing the performance data generated from the performance means at a performance timing.
The time between each beat operation timing is stored so that the time interval between the beat operation timing storage means for storing the beat operation timing by the operation means and each beat operation timing stored in the beat operation timing storage means becomes equal. And a performance data correction means for correcting the performance timing of the performance data stored in the performance data storage means at each time interval operation timing according to the modification. ..

[0006]

The performance means generates performance data in response to a performance operation by the player, and can be constituted by, for example, a keyboard of an electronic musical instrument. The operating means is operated by the player in order to beat at a predetermined timing in accordance with the performance tempo of the playing means, and may be constituted by, for example, a foot switch or the like which is turned on and off by a foot. it can. The performance data storage means stores the performance data generated from the performance means so as to be sequentially readable in correspondence with the performance timing. The time signature operation timing storage means stores the time signature operation timing by the operation means so as to be sequentially readable corresponding to the reading of the performance data. The performance data correcting means corrects the time intervals between the respective beat operation timings so that the time intervals between the respective beat operation timings stored in the beat operation timing storage means are equal to each other, that is, are constant. For each time signature operation timing interval thus modified, the performance timing of the performance data stored in the performance data storage means is modified in accordance with the modification of the corresponding time signature operation timing interval.

As described above, the time signature operation timing intervals are corrected equally, and the performance timing of the corresponding performance data is modified according to the modification of each time signature operation timing interval. Becomes constant, and therefore, is synchronized with the bar and beat timing. Therefore, for example, even performance data obtained by playing the performance means at a tempo that is not constant and having uneven performance timing can be recorded as automatic performance data that can be reproduced at a constant tempo. ..

As a concrete method for correcting the time intervals between the time signature operation timings to be equal to each other, a specific time signature operation timing interval is set as a reference timing interval and is adjusted to the reference timing interval. And other beat operation timing intervals may be corrected, or each beat operation timing interval may be averaged. Further, as a concrete method for correcting the performance timing of the performance data in accordance with the modification of the time signature operation timing interval, the modification rate of each time signature operation timing interval is obtained, and the modification rate is set to the performance timing of the corresponding performance data. A method of multiplying is possible.

Further, the operation of the operating means, that is, the operation of storing the time signature operation timing in the time signature operation timing storage means stores performance data generated from the performance means as the performance means performs the performance. May be performed in parallel (that is, in real time), or may be performed while playing the stored performance data.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram of a hardware configuration showing an embodiment of an electronic musical instrument to which an automatic musical instrument according to the present invention is applied. In this example, a CPU 1 and a program RO
Various processes are executed under the control of a microcomputer including M2, data and working RAM3. In this microcomputer, a key press / release key detection circuit 5, a panel operation detection circuit 6, a tap operation detection circuit 7, R are provided via a data and address bus BS.
A performance data memory PDM and a tap data memory TDM made of AM and a tone generator circuit TG are connected.

The key-release key detection circuit 5 is a performance means having a plurality of keys for designating the pitch of a musical tone to be generated.
It is provided corresponding to the keyboard KB and includes a key switch circuit corresponding to each key of the keyboard KB. The key release key detection circuit 5 detects a change in the keyboard KB from a key release to a key press and outputs a key-on event signal, and detects a change from a key press to a key release and outputs a key-off event signal. In addition, a key code indicating a key associated with each of the key events is output.

The panel operation detection circuit 6 is provided corresponding to each operator provided on the operation panel 8 and outputs operation data according to the operation status of each operator.
The operators of the operation panel 8 include a normal performance operator group 9 for selecting, setting, and controlling the tone color, volume, pitch, effect, etc. of a musical sound to be generated, and an automatic performance operator 10.
It includes groups and the like.

In the figure, only the mode selection switch 10a, the start switch 10b and the stop switch 10c of the automatic performance operator group 10 are shown individually. The mode selection switch 10a is a push button type switch, and each time the mode selection switch 10a is turned on, the operation mode of the electronic musical instrument can be switched to a recording mode or a reproduction mode.

In this recording mode, the performance data such as key event data and key code generated by the performance operation of the keyboard KB is sequentially stored in the performance data memory PDM so as to be sequentially readable at the performance timing of the keyboard KB. That is, this is an operation mode for recording. In the reproduction mode, the performance data recorded in this way is stored in the memory PD.
This is an operation mode for generating a performance sound by reading from M and reproducing. The start switch 10b and the stop switch 10c are switches for starting and stopping the recording mode or the reproduction mode selected by the mode selection switch 10a when turned on.

The foot switch 12 is operated by a player's foot in order to obtain a time signature in accordance with the performance tempo of the keyboard KB when the performance data of the keyboard KB is recorded in the performance data memory PDM in the recording mode. It is a switch that can be turned on and off. Hereinafter, an operation on the foot switch 12 will be referred to as a tap operation.

The tap operation detection circuit 13 detects a tap operation on the foot switch 12 and outputs a tap event signal. In this embodiment, when the performance data of the performance on the keyboard KB is recorded in the performance data memory PDM, tap data indicating the timing of the tap event in the foot switch 12 is recorded and the tap data is used to perform the performance. By correcting the unevenness of the performance timing in the data, the performance data can be recorded as automatic performance data that can be reproduced at a constant tempo.

FIG. 2 is a diagram for schematically explaining an example of the operation for correcting the performance timing of the performance data in this embodiment. That is, when the recording mode is running, as shown in (a), data indicating a key-on event and a key-off event on the keyboard KB after the recording mode is started (indicated by "ON" and "OFF" in the figure).
Is stored as performance data in the performance data memory PDM together with the key code of each key event (indicated by "KC1" ... "KC3" in the figure) and the event interval data. Here, the event interval data is data indicating a time interval between events, which is a key event and a tap event, and a time interval between a recording mode start time point or a recording mode end time point and the event. .. Separately from this, a tap event on the foot switch 12 (“TAP” in the figure)
Is detected, and the time interval between the first tap event and the second tap event after the start of the recording mode is set as the reference tap event interval BT. Next, as shown in (b), each interval data between the second and subsequent tap events is corrected to be equal to the reference tap event interval BT, that is, expanded or shortened. Then, the event timing data after the second tap event is modified according to the modification rate of the interval data between the corresponding tap events, so that the performance timing is modified. Therefore, the event interval data before the second tap event is not modified at all. In addition, in this embodiment, the event interval and the tap event interval are indicated by numerical values counted in units of 1/24 beats.

Explaining with the example shown in FIG. 2A, since the reference tap event interval BT is set to 16, for example, event interval data “8” between the second tap event and the third tap event. "Is doubled so as to be equal to the reference tap event interval BT, and accordingly, event interval data" 4 "between the second tap event and the key off event immediately thereafter, and the key off event. The event interval data “4” between the third tap event TAP and the third tap event TAP is also corrected to be doubled. The tap event interval data between the tap events after the third time and the corresponding event interval data will be similarly corrected.

Since the performance timing of the performance data stored in the performance data memory PDM can be modified in this way, the performance performed by the keyboard KB in the above-described recording mode is synchronized with the timing of a bar or a beat. It does not have to be performed at a fixed tempo, and can be performed at a tempo of your choice depending on the difficulty level of the performance. In other words, it is possible to perform at a normal tempo for the part that is not difficult to perform and at a slow tempo for the part that is difficult to perform.

FIGS. 3A and 3B respectively show memory formats of the tap data memory TDM and the performance data memory PDM used for correcting the performance timing of the performance data in the example of FIG. .. Further, the performance data memory PDM stores the performance data after the performance timing correction as final automatic performance data. FIG. 3C shows the performance data after the performance timing correction. The memory format of the performance data memory PDM for storing is shown. More specifically, in the recording mode, with the performance of the keyboard KB, the performance data memory PDM stores an event interval instruction code (indicated by "interval instruction code" in the figure) indicating that the stored content of the next address is an event interval. Show)
And the event interval data corresponding to this, and a key-on event instruction code or a key-off event instruction code indicating that the stored content of the next address is a key code related to a key-on event or a key-off event (hereinafter,
These two chords are collectively referred to as a key event instruction code) and the corresponding key code are stored in four consecutive addresses as one unit of performance data. Further, in the tap data memory TDM, there are a tap address that specifies the timing of occurrence of the second and subsequent tap events with an address corresponding to the address of the performance data memory PDM, and a corresponding tap event and next tap event. The tap event interval data indicating the time interval between the two will be stored in two consecutive addresses as one unit of tap data.

In this embodiment, of the event interval data stored in the performance data memory PDM, the event interval data stored in a state of being divided by the tap event is corrected as necessary, and After being added to one, the final event interval data is stored in the performance data memory PDM. For example, the event interval data stored in the address 13 and the address 14 of the performance data memory PDM will be described. Corresponding to the event interval data “4” of the address 13 which is not modified because it is the data before the second tap event. The event event data of address 14 corrected from “4” to “8” by being multiplied by the correction rate of tap event interval data of 16/8 = 2 is added to obtain the final event. The interval data "12" is stored in the performance data memory PDM.

The clock counter 14 counts time intervals such as the event interval and tap event interval, and generates a tempo clock pulse for setting the tempo of automatic performance. The tempo clock pulse is It is given as an interrupt signal to the CPU 1. By the interruption processing based on this interruption signal, the CPU 1 stores the performance data in the performance data memory PDM in the recording mode, and sequentially reads and reproduces the stored contents of the performance data memory PDM in the reproduction mode.

The tone generator circuit TG is adapted to generate a tone signal in each of a plurality of tone generating channels based on a key event, a key code and various other data inputted via the data and the address bus BS. .. The tone signal generated by this tone generator circuit TG is D / A
After conversion, it is acoustically pronounced via the sound system SS.

Further, in the predetermined area of the data and working RAM 3, the following registers used in various processes described later are prepared. KC: A key code register that stores a key code related to a key-on event or a key-off event. RP: A mode flag that stores "1" when the recording mode is selected by the mode selection switch 10a of the operation panel 8 and "0" when the reproduction mode is selected. RUN: A traveling flag that stores "1" when the start switch 10b of the operation panel 8 is turned on and the recording mode or the reproduction mode is traveling, and stores "0" when the stop switch 10c is turned on. PDP: Performance data memory A performance data memory pointer that specifies the address of the PDM. TP: A tap data memory pointer that specifies the address of the tap data memory TDM. EV: A register that stores the type of event. KI: An event interval counter that counts event intervals in the recording mode. TN: A tap event number counter that counts the number of tap events. TI: A tap event interval counter that counts the time interval from the previous tap event to the current tap event in the recording mode. TIM: A tap event interval register that stores the tap event interval read from the tap data memory TDM. BTM: Reference tap event interval register that stores the reference tap event interval BT for modifying the tap vent interval.

Next, an example of various processes executed by the microcomputer will be described with reference to the flow charts shown in FIGS. 4 to 11. FIG. 4 shows an example of the main routine. First, after performing a predetermined initialization process, the key press / release key detection circuit 5, the tap operation detection circuit 13 and the panel operation detection circuit 6 are scanned to determine the presence or absence of each event. Is detected, and if there is an event, the processing corresponding to each event is repeated. That is, when a key event is detected as a result of scanning the key release key detection circuit 5, the key event process shown in FIG. 6 is performed. When a tap event is detected as a result of scanning the tap operation detection circuit 13, tap event processing, an example of which is shown in FIG. 7, is performed. In addition, as a result of scanning the panel operation detection circuit 6, particularly when a switch event of the mode selection switch 10a, the start switch 10b, and the stop switch 10c is detected, FIG.
The switch event processing shown in FIG.

When the performance data of the keyboard KB is recorded in the performance data memory PDM or the performance data recorded as the automatic performance data is to be reproduced, the user sets the operation mode of the electronic musical instrument to the recording mode. Therefore, either the mode selection switch 10a or the start switch 10b on the operation panel 8 is appropriately turned on. The micro computer performs the switch event processing of FIG. 5 by detecting the switch event.

In this switch event process, first, it is detected which switch has an on event (step 30). When the on event of the mode selection switch 10a is detected, the mode flag RP is inverted to set the operation mode. After changing from the reproduction mode to the recording mode or from the recording mode to the reproduction mode, the process returns to the main routine (step 31). Further, when the operation of the start switch 10b is detected, the traveling flag RUN is set to "1".
(Step 32) and the performance data memory pointer PDP is set to "0" (step 33). Next, it is checked whether or not the mode flag RP is "0" (step 34).

Description of the storage mode Here, when the recording mode is selected by the mode selection switch 10a in order to record the performance data by the manual performance of the keyboard KB, the result is NO, and in this case, Of the tap data memory pointer TP and the event interval counter K.
After setting I, the tap event interval counter TI and the tap event number counter TN to "0", the process returns to the main routine. In this way, the event interval counter KI and the tap event interval counter TI start counting the time from the recording mode start point. After the recording mode is started in this way, the performance of the keyboard KB is started, and when any key event is detected, the key event processing of FIG. 6 is executed.
First, it is determined whether the detected key event is a key-on event (step 36). When it is a key-on event, the key code of the key relating to the key-on event is stored in the key code register KC (step 37), and a predetermined key-on event process such as sending the key-on event and the key code to the tone generator circuit TG is performed (step 37). Step 38). Next, it is confirmed whether the mode flag is "1" and the traveling flag RUN is "1" (step 39). If the confirmation result is YES, the process proceeds to the next step 40, and if NO, the process immediately returns.

In step 40, first, the pointer PDP
The event interval instruction code is stored at the address of the performance data memory PDM designated by (indicated by PDM (PDP)). This event interval instruction code stores event interval data indicating the time interval from the previous event (at the time of the start after the start of the recording mode, if the event is the start event) to this event at the next address PDP + 1. It is an identification code that indicates that it has been done. Next, the address PDP + 1 obtained by adding 1 to the value of the pointer PDP is designated as the write address of the performance data memory PDM (this is indicated by PDM (PDP + 1)), and the event interval data counted by the event interval counter TI is stored therein. Store. Furthermore, the pointer P
The address PDP + 2 obtained by adding 2 to the value of DP is specified as the write address of the performance data memory PDM (this is P
DM (PDP + 2)), in which a key-on event instruction code indicating that the current key event is a key-on event is stored, and the next address PDM (PDP +
In 3), the key code of the register KC, that is, the key code related to the current key-on event is stored.

When the processing of step 40 is completed, step 4
Go to 1, set the value of the event interval counter to "0", advance the pointer PDP by 4, and return.

On the other hand, when the detected key event is a key-off event, substantially the same processing is performed. That is, the key code of the key relating to the key off event is stored in the key code register KC (step 42), and a predetermined key off event process such as sending the key off event and the key code to the tone generator circuit TG is performed (step 4).
3). Next, the mode flag is "1" and the traveling flag R
It is confirmed whether UN is "1" (step 44). If the confirmation result is YES, the process proceeds to the next step 45, and if NO, the process immediately returns. Step 45
Then, in the address PDM (PDP) of the performance data memory PDM designated by the pointer PDP, the stored content of the next address PDM (PPDP + 1) is the time interval from the last key event after the start of the recording mode to the current key-off event. The event interval identification code indicating that is stored. And the address PDM
The event interval data counted by the event interval counter TI is stored in (PPDP + 1). Further, a key-off event identification code indicating that this key event is a key-off event is stored in the next address PDM (PDP + 2), and the next address PDM (P
The key code set in the key code register KC in step 42, that is, the key code related to the current key-off event is stored in DP + 3). Step 45
When the processing of (1) is completed, the processing of step 41 is performed and the processing returns.

By such key event processing, every time there is a key event, as shown in FIG. 3A, the performance data related to the key event is stored in the performance data memory PD.
It will be stored in four consecutive addresses of M.

Further, as described above, the performance data memory PD
When performance data is stored in M, a tap operation is performed by the foot switch 12 in accordance with the performance tempo, and when the tap event is detected, the tap event processing of FIG. 7 is performed.

In this tap event processing, first, the mode flag RP is "1" and the traveling flag RUN is "1".
Is checked (step 46). In this case, the mode selection switch 10a and the start switch 10b
Since the recording mode is running by the operation of, the result is YES, the process proceeds to the next step 47, and the tap event number counter TN is incremented by 1. If NO, return immediately. When the process of step 47 ends, it is checked whether the value of the tap event number counter TN is "1" (step 48). If the result is YES, it means that the tap event is the first tap event after the start of the recording mode, so the value of the tap interval counter TI is set to 0 (step 49), and the process is returned without any other processing. To do. In this way, the tap event interval counter TI starts counting the time interval from the first tap event after the start of the recording mode.

On the other hand, the result in step 48 is NO,
That is, when the value of the tap event counter TN is not "1", it is further checked whether or not the value of the tap event counter TN is "2" (step 49). When the tap event is the second tap event after the start of the recording mode, the result of step 49 is YES, the process proceeds to the next step 50, and the content of the tap event interval counter TI is set in the reference tap event interval register BTM. .. In this way, the reference tap interval register BTM is set with the reference tap event interval data BT, which is the time interval data between the first tap event and the second tap event after the start of the recording mode. When the process of step 50 is completed, the process goes to step 51, where the event interval instruction code is stored in the address PDM (PDP) of the performance data memory PDM designated by the pointer PDP, and the event interval counter is stored in the next address PDM (PDP + 1). The contents of KI are stored. As a result, the event interval data between the second tap event and the key event immediately before the second tap event is stored in the address PDM (PDP + 1). Next, the PDP is advanced by 2 (step 52), and the value of the pointer PDP advanced by 2 is stored in the tap data memory TDM (step 53). This step 53
As a result, the tap address for specifying the occurrence timing of the second tap event is stored in the head address of the tap data memory TDM. For example, in the example of FIG. 3B, the storage data “14” of the address “0” in the tap data memory TDM is the tap address that specifies the timing of the second tap event occurrence. When the tap address has been stored in this way, in step 54, the pointer TP is advanced by 1, the event interval counter KI is set to 0, and thereafter,
In step 49, tap event interval counter TI
Is set to 0 and the process returns to the main routine.

On the other hand, when the tap event is the third tap event after the start of the recording mode, the result of step 49 is NO. In this case, in the next step 55, the tap event interval counter T
The content of I is stored in the address TDM (TP) of the tap data memory TDM designated by the pointer TP. As a result, tap event interval data indicating the time interval between the second tap event and the third tap event is stored in the address TDM (TP).
For example, in the example of FIG. 3B, the storage data “8” of the address “1” is the tap event interval data indicating the time interval between the second tap event and the third tap event. Become. Next, in step 56, the value of the data memory pointer TP is incremented by 1, and then the processes of steps after step 51 are performed and the process returns.
It should be noted that the same processing as in the third tap vent is performed for the fourth and subsequent tap events.

By such tap event processing, 2
The timing of each tap event after the first time is sequentially stored in the tap data memory TDM so that it can be specified by the tap address corresponding to the address of the performance data memory PDM.

Description of Reproduction Mode When the start switch 10b is turned on while the reproduction mode is selected by the operation of the mode selection switch 10a, the mode flag RP is "1". Step 34 in the process
The result is YES. In this case, the value of the event interval counter KI is set to 0 (step 58) and the "reading process" subroutine is executed in the next step 59. In this "reading process" subroutine, the reading process for starting the stepping of the clock counter CL and reading and reproducing the automatic performance data stored in the performance data memory PDM, for example, as shown in (c) of FIG. Run.

FIG. 8 shows an example of this "reading process" subroutine. Here, first, the pointer PD
It is checked whether the stored content of the address PDM (PDP) of the performance data memory PDM designated by P is an end code (step 60). What is an end code?
As will be described later, this is a code stored in the performance data memory PDM and the tap data memory TDM when the recording mode changes from the running state to the stop state. In this case, the end of the automatic performance data stored in the performance data memory PDM. Is shown. If it is an end code, the contents of the address PDM (PDP), that is, the end code is set in the event register EV (step 61),
To return. When the result of step 60 is NO,
Further, it is checked whether the stored content of the address PDM (PDP) is an event interval instruction code (step 62). If it is an event interval instruction code, the next address PDM (PDP +) of the performance data memory PDM
A value obtained by subtracting 1 from the value of the event interval data stored in 1) is set in the event interval counter KI (step 63), and the pointer PDP is further advanced by 2 (step 64). On the other hand, the address PDM (P
When the stored content of DP) is the key-on event instruction code or the key-off event instruction code, the result of step 62 is NO. In this case, the process proceeds to step 65, and the key-on event instruction which is the stored content of the address PDM (PDP). The chord or key-off event instruction code is stored in the event register EV, and the next address PDM (P
The key code stored in the (DP + 1) address is stored in the key code register KCD. When the process of step 65 ends, the process returns to step 64.

In the "readout process" subroutine in such a switch event process, a predetermined process for starting the reproduction performance is performed according to the current value of the winter PDP. The subsequent reproduction processing of the automatic performance data is executed as an interrupt processing as shown in FIG. 9 based on the interrupt signal given from the clock counter CL at the timing of 1 / 24th beat.

In FIG. 9, first, the traveling flag is "1".
It is checked whether or not (step 66). In this case, since the start switch 10b is turned on, the result is Y
It becomes ES and goes to the next step 67. In step 67, it is checked whether or not the mode flag RP is "0". In this case, since the playback mode is selected, the result is Y.
When ES is reached, the process goes to the next step 68, and it is checked whether or not the content of the event interval counter KI is larger than zero. If the result of step 68 is YES, it means that the read timing has not come yet, so the value of the event interval counter KI is decremented by 1 (step 69), and the routine returns. If the result is NO, that is, 0, it means that the read timing has come.
At step 70, the reading process of FIG. 8 is performed. next,
It is checked whether the content stored in the event register EV is an end code (step 71). If it is end code, it returns immediately, and if it is not end code,
It is checked whether the stored content is the event interval instruction code (step 72). If it is an event interval instruction code, it immediately returns. When it is neither the end code nor the event interval instruction code, the process further goes to the next step 73 to check whether it is the key-on event instruction code. When it is a key-on event instruction code,
In step 74, the key-on signal and the key code stored in the address PDM (PDP) of the performance data memory PDM designated by the pointer PDP are output to the tone generator circuit TG. In this way, the tone generator circuit T
In G, the generation of the tone signal having the pitch corresponding to the given key code is started in response to the key-on signal. On the other hand, when the result of step 73 is NO, it means that it is a key-off event instruction code. In this case, therefore, go to step 75, and the key-off signal and the address PDM of the performance data memory PDM designated by the pointer PDP. The key code stored in (PDP) is output to the tone generator circuit TG. In this way, in the tone generator circuit TG, the tone generation of the tone signal in the channel to which the key code is assigned is attenuated according to the key-off signal.

The interrupt processing is executed not only when the reproduction mode is running but also when the recording mode is running. When the vehicle is traveling in the recording mode, the result of step 67 is NO, and in this case, 1 is added to each of the event interval counter KI and the tap event interval counter TI (step 76), and the process returns.

Description of correction of performance data When the user wants to stop the recording of the performance data and the tap data in the recording mode or the reproduction of the automatic performance data in the reproduction mode, the user must stop switch 1
0c is turned on. In this case, the microcomputer detects the switch event of the stop switch 10c in step 30 of the switch processing of FIG. 5 and sets the traveling flag RUN to "0" (step 77). Then, in the next step 78, it is checked whether or not the mode flag RP is "0". Stop switch 10 when playing automatic performance data in playback mode
When c is turned on, the result of step 78 is "0". In this case, a muffling process is performed to mute the reproduced sound of the automatic performance data (step 79), and the process returns.

On the other hand, when the stop switch 10c is turned on while recording performance data and tap data in the recording mode, the result of step 78 is NO. In this case, the process proceeds to step 80 to perform. Data memory PDM and tap data memory TDM
An end code indicating the end of the recording mode is stored in each of. When the processing of step 80 ends, step 81
To the performance data memory P when running in the recording mode.
A correction process for correcting the unevenness of the performance timing in the performance data recorded in the DM is performed based on the tap event.

FIG. 10 shows an example of this correction processing. First, at step 82, it is checked whether the value of the tap event number register TN is 2 or more. If the result of this step is NO, it means that there was no tap event or only once when the performance data of the performance of the keyboard KB was recorded in the performance data memory PDM. Return without processing. On the other hand, when the result of this step is YES, the routine proceeds to step 83, where it is checked whether or not the value of the tap event number register TN is 2. When the value of the register TN is 2, it means that there were only two tap events when the performance data of the performance of the keyboard KB was recorded in the performance data memory PDM, and therefore the correction processing of the performance data should be performed. Instead, the "data packing process" subroutine is executed (step 84). This "data packing process" subroutine is a process for adding up the event interval data divided and stored before and after the second and subsequent tap events, as described with reference to FIG.

FIG. 11 shows an example of this "data packing process" subroutine. First, the write pointer PA and the read pointer PB for data packing processing are set to 0 (step 85), and then the address PDM (PB) of the performance data memory PDM designated by the pointer PB.
It is checked whether or not the stored content of is an event interval instruction code (step 86). If the answer is NO, it means that the stored content of the next address of the performance data memory PDM is not the event interval instruction code indicating the event interval data. In this case, therefore, the "data packing process" subroutine is not performed. , Go to step 87 and check whether the stored content of the address PDM (PB) is a key event instruction code. When it is a key event instruction code, the key event instruction code is stored in the address PDM (PA) of the performance data memory PDM designated by the pointer PA, and at the next address PDM (PA + 1) of the performance data memory PDM. The key code related to the key event instruction code is stored (step 88). When the processing of step 89 ends, the pointer P
A and the pointer PB are each advanced by 2 (step 89) and the process returns to step 86. The result of step 87 is N
When it is O, the address P of the performance data memory PDM
Since the end code is stored in DM (PB), the end code is stored in the address PDM (PA) of the performance data memory PDM designated by the pointer PA (step 90), and the process returns.

The result of step 86 is YES, that is, the stored content of the address PDM (PB) of the performance data memory PDM designated by the pointer PB indicates that the stored content of the next address is the event interval data. When the code is the event interval instruction code, the procedure goes to step 91, and the event interval register KI is set to "0". Then, a value obtained by adding the current contents of the register KI and the value of the event interval data stored in the next address PDM (PB + 1) of the performance data memory PDM is set in the event interval register KI (step 9).
2), the pointer PB is advanced by 2 (step 93).
Next, at step 94, the performance data memory P designated by the pointer PB advanced by 2 in this way.
It is checked whether the stored content of the DM address PDM (PB) is the event interval instruction code. When the result is YES, the processes of steps 92 and 93 are repeated. By the processing subroutine of steps 92, 93, and 94, the event interval data recorded separately in the performance data memory PDM before and after the tap event in the performance data memory PDM are added, that is, data is packed and stored. Will be done. When the necessary data packing is completed, the result of step 94 is NO, and the routine proceeds to step 95, where it is checked whether the stored content of the address PDM (PB) of the performance data memory PDM designated by the pointer PB is the end code. If it is an end code, the process returns through step 90. If it is not the end code, it is checked whether the content of the event interval register KI is larger than 0 (step 96). Y
At the time of ES, the event interval instruction code is stored in the address PDM (PA) of the performance data memory PDM designated by the pointer PA, and the next address PD is also stored.
The content of the event interval register KI is stored in M (PA + 1) (step 97). In this way, the address PDM (PA + 1) of the performance data memory PDM is
The event interval data packed with data will be stored. Next, the pointer PA is advanced by 2 and step 8
After performing the "data packing process" subroutine of 8 and 89, the process returns to step 86. The result of step 96 is N
When O, that is, when the value of the event interval register KI is 0, the process returns to step 86 through steps 88 and 89 without performing the processing of steps 97 and 98.

Returning to FIG. 10, the result of step 83 is N
When O, that is, when the number of tap events is three or more, the pointer TP is set to 0 (step 99), the process proceeds to step 100, and the stored content of the address TDM (TP) of the tap data memory TDM designated by the pointer TP is Check whether it is an end code. If yes,
Going to step 84, the "data packing process" subroutine of FIG. 11 is performed, and the process returns.

The result of step 100 is NO, that is,
If it is not the end code, go to step 101 and enter the address TDM of the tap data memory TDM.
The tap address data stored in (TP) is stored in the performance data memory PDM, and the tap event interval data stored in the next address TDM (TP + 1) of the tap data memory TDM is set in the tap event interval register DTM. To do. And the pointer T
Advance P by 2 (step 102), then step 10
Go to 3.

In step 103, the event interval data stored in the next address PDM (PDP + 1) of the performance data memory PDM is modified according to the modification of the tap event interval data. That is,
As described schematically in FIG. 2, the reference tap event interval BT stored in the reference tap interval register BTM.
Value is divided by the value of the tap event interval stored in the tap event interval register DTM to obtain the correction rate of the corresponding tap event interval data, and the correction rate is stored in the address PDM (PDP + 1). Multiply the value of the interval data. Then, the multiplication result is overwritten on the address address PDM (PDP + 1) of the performance data memory PDM. By such processing, for example, the event interval data “4” stored at the address “15” of the performance data memory PDM in the example of FIG. 3A is the tap event interval correction rate 16
By multiplying ÷ 8 = 2, it is corrected to 8.

When the processing of step 103 is completed, the pointer PDP is advanced by 2 (step 104), and step 10
Go to 5. In step 105, the performance data memory PD designated by the pointer PDP advanced by 2 in this way
It is checked whether the stored content of the address PDM (PDP) of M is the end code. If it is an end code, the data packing process of FIG. 11 is performed in step 84, and the process returns. If NO, that is, if it is not the end code, in the next step 106, the address PD
It is checked whether the stored content of M (PDP) is a key event instruction code. If YES, the pointer PDP is further advanced by 2 (step 107), and step 105 is performed again.
And 106 are performed. The processing subroutine of steps 105, 106 and 107 is repeated until the result of step 106 is NO, that is, the event interval instruction code.

When the result of step 106 becomes the event interval instruction code, the process proceeds to the next step 108, and the value of the pointer PDP is the value stored in the address TDM (TP) of the tap data memory TDM designated by the pointer TP. It is checked whether or not the above is true, that is, whether or not PDP ≧ TDM (TP). When the address designated by the pointer PDP has not reached the next tap address stored in the address TDM (TP) of the tap data memory TDM, the result is NO, and in this case, the next address PDM of the performance data memory PDM. (PDP + 1)
In order to correct the event interval data stored in, the processing from step 103 to step 108 is repeated. The value of the pointer PDP is the tap data memory T.
When the value of the next tap address stored in DM is reached, the result of step 108 is YES, and in this case, the process returns to step 100 and the address TDM (T
It is checked whether the stored content of P) is an end code. If it is an end code, the data is packed in step 84, and if it is not the end code, the steps after step 101 are repeated to correct the event interval data corresponding to the next tap address.

When the traveling in the recording mode is stopped after the tap event is recorded twice or more by the correction processing as described above, the correction processing and the "data packing processing" subroutine described above are performed. That is, the tap event interval data between the second and subsequent tap events are corrected to be equal to each other, and the event interval data corresponding to the corrected tap event interval data is adjusted according to the correction rate of the corresponding tap event interval data. , Will be fixed. In addition, the event interval data recorded by being divided by the tap event after the second time is 1
Data will be packed into one.

In the above embodiment, the tap operation is performed and the timing of the tap event is recorded in parallel with the recording of the performance data generated by the performance of the keyboard. However, not limited to this, the performance data of the keyboard may be temporarily recorded, and the tap operation may be performed while the performance data is reproduced to record the timing of the tap event. Further, the means for performing the tap operation is not limited to the foot switch, and other means may be used.

Further, the performance timing data may be stored while moving the write address of the performance data memory in correspondence with the event interval data. Further, the memory format of the performance data memory is not limited to that of the embodiment, and may be other formats, and data other than the event interval data may be stored. Furthermore, the tempo may be correlated with the tempo before the change so that the tempo does not change suddenly. The present invention is not limited to electronic musical instruments, but may be applied to an automatic accompaniment device, an automatic rhythm playing device, or the like.

[0056]

As described above, according to the present invention, the beat operation timing intervals are corrected equally, and the performance timing of the corresponding performance data is corrected according to the correction of each beat operation timing interval. .. as a result,
According to the present invention, even performance data having uneven performance timing can be easily corrected so that the performance timing becomes constant, and the performance data can be recorded as automatic performance data that can be reproduced at a constant tempo. It has an excellent effect that it can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of an embodiment of an electronic musical instrument to which an automatic performance device according to the present invention is applied.

FIG. 2 is a diagram for explaining the outline of the operation of the present invention.

FIG. 3 is a diagram showing an example of a memory format of a tap data memory and a performance data memory of FIG.

FIG. 4 is a flowchart showing an example of a main routine executed by the microcomputer shown in FIG.

5 is a flowchart showing an example of a switch event process in FIG.

FIG. 6 is a flowchart showing an example of key event processing in FIG.

FIG. 7 is a flowchart showing an example of tap event processing in FIG.

8 is a flowchart showing an example of a reading process in FIG.

FIG. 9 is a flowchart showing an example of interrupt processing executed in response to a tempo clock signal.

FIG. 10 is a flowchart showing an example of a correction process in FIG.

11 is a diagram showing an example of a data packing process in FIG.

[Explanation of symbols]

1 ... CPU, 2 ... Program ROM, 3 ... Data and working RAM, 5 ... Key release detection circuit, 6 ... Panel operation detection circuit, 7 ... Tap operation detection circuit, 8 ... Operation panel, 12 ... Foot switch, KB ... Keyboard, PDM ... Performance data memory, TDM ... Tap data memory.

Claims (1)

Claims: 1. A performance means for generating performance data in response to a performance operation by a performer, an operation means operated by the performer to obtain a beat, and a performance means generated from the performance means. Performance data storage means for storing the performance data corresponding to the performance timing, beat operation timing storage means for storing the beat operation timing by the operating means, and each of the beat operation timing storage means The time intervals between the beat operation timings are corrected so that the time intervals between the beat operation timings are equal, and in accordance with this correction, the time interval between the beat operation timings is stored in the performance data storage means. An automatic performance device having performance data correction means for correcting the performance timing of each performance data.