JPH0511520U - Multiplier circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] The object is to obtain a multiplication circuit which can be used in a high frequency band and can be easily integrated into an IC even at high multiplication. [Structure] A full-wave rectified waveform generating circuit that constitutes a circuit is combined with a one-stage differential amplifier circuit and a current mirror, and a circuit that does not use a feedback circuit is used. [Effect] The order of the LPF in the latter stage can be lowered and these I
C conversion can be performed easily.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

The present invention relates to a multiplication circuit for converting a frequency to 2 ⁿ times.

[0002]

[Prior art]

  In the multiplication circuit, for example, the input wave is distorted by a non-linear circuit, and , Which takes out the required second harmonic from a resonant circuit consisting of a coil and a capacitor, Alternatively, an operational amplifier, an integrating amplifier circuit, an OR circuit, a NAND circuit, and an AND There are a combination of circuits and a circuit as shown in FIG.

[0003]   FIG. 1 is a block diagram showing an embodiment of the present invention, but a conventional circuit has a similar structure. The conventional multiplication circuit will be described with reference to FIG.   In FIG. 1, reference numeral 1 denotes the entire doubler circuit, which is a full-wave rectified waveform generator. It consists of a raw circuit 10, a DC bias correction circuit 11, and an LPF 12, and has a sine wave. Is input, the full-wave rectified waveform generation circuit 11 obtains the full-wave rectified waveform and the DC bias A doubled waveform is obtained through the correction circuit 11 and the LPF 12. Figure 1 points Waveforms of A, B and C are shown in A, B and C of FIG. 2, respectively.

[0004]

[Problems to be solved by the device]

The problem to be solved is that in the conventional multiplication circuit as shown in the figure, the full-wave rectified waveform generating circuit 10 uses a circuit for alternately flowing the output current of the operational amplifier to obtain the full-wave rectified waveform. The operating frequency band is low, and since a large number of capacitors are used, the circuit is expensive and large in size, which makes it difficult to form an IC for the entire multiplication circuit. This problem becomes particularly noticeable when multi-stage connection is performed to obtain a 2 ⁿ multiplier circuit.

[0005]   The present invention has been made to solve such a problem, and it is easy to form an IC and is expensive. The purpose is to obtain a multiplication circuit that can be used in the frequency band.

[0006]

[Means for Solving the Problems]

The multiplier circuit according to the present invention is characterized in that the full-wave rectified waveform generating circuit that constitutes the circuit is configured by a circuit that does not use a feedback circuit by combining a single-stage differential amplifier circuit and a current mirror. It is characterized in that a plurality of stages are connected across a stage number switching circuit which operates according to a signal from the circuit to form a 2 ⁿ multiplication circuit.

[0007]

[Action]

  In the present invention, the full-wave rectified waveform generator circuit has a single-stage differential amplifier circuit and a current mixer. High frequency by using a circuit that does not use a feedback circuit It is possible to operate the IC in the following stage, and the LPF in the subsequent stage can be easily integrated into an IC.

[0008]

【Example】

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. 2 is a block diagram and FIG. 2 is a diagram showing waveforms at points A, B, and C in FIG. , FIG. 2 has been described as a conventional technique, and a duplicate description will be given here. Is omitted.

[0009]   FIG. 3 is a connection diagram showing an embodiment of the circuit configuration of the full-wave rectified waveform generating circuit in the present invention. In the figure, this full-wave rectified waveform generation circuit is based on the same application filed by the applicant of the present application on the same date. Since it has been explained in detail in the devising and "full-wave rectified waveform generation circuit", it is omitted here. Although omitted, a nearly complete full-wave rectified waveform can be obtained, and no capacitor should be used. Instead, it can be operated in a high frequency band.   Therefore, by using this full-wave rectified waveform generation circuit, the LPF 11 in the subsequent stage can be The order of can be reduced, and these ICs can be realized.

[0010]   FIG. 4 is a view showing another embodiment of the present invention, in which 1a to 1n are 2 respectively. Multiplier circuits 2a to 2n-1 are stage number switching circuits, respectively.

Next, the operation will be described. When a sine wave (shown by A in FIGS. 1 and 22) is input to the full-wave rectified waveform generating circuit 10, this output waveform becomes a waveform shown by B in FIG. Here, when the peak value is H, the output can be expressed by the equation (1) shown in the lower part of FIG. Therefore, the doubled component is 4H / π · cos2x / 3, and the other harmonic components are 4H / π · cos4x / 15, 4H / π · cos6x / 35, ... 4H / π · cos2nx / 4n ² It becomes -1, and the harmonic component is very small, being 1/5 or less compared to the doubled component. Therefore, the LPF 12 in the subsequent stage can use a lower one.

When the LPF 12 removes the harmonic component, only the doubled component remains, and a doubled waveform as shown in FIG. 2C is obtained. If the losses in the full-wave rectification waveform generation circuit 10, the bias correction circuit 11 and the LPF 12 are amplified before the rectification circuit shown in FIG. 3, the input and output amplitudes are the same. Therefore, as shown in FIG. 4, the doubler circuit 1 having the above-described structure has a plurality of stages (1a, 1b) with a stage number switching circuit (2a, 2b, ... , ... 1n) By connecting, an output of ²ⁿ multiplication is obtained.

Further, since the full-wave rectified waveform generating circuit shown in FIG. 3 directly connects each stage, a decoupling capacitor is not necessary. Further, since a high frequency can be used in the LPF 12, the capacitor is integrated into an IC. Can be built-in. When using a low frequency, SCF can be used. Further, by operating one of the stage number switching circuits by a signal from the outside, an output of 2 ^m multiplication (m is an integer of 1 or more) can be arbitrarily obtained. For example, by switching the output circuit of the m-th stage from the input side of the next stage to the output terminal side, and disconnecting the final stage (n-th stage) switching circuit from the output terminal side, an output of 2 ^m multiplication can be obtained. .

[0014]

[Effect of device]

  As explained above, the multiplier circuit of the present invention can be used in a high frequency band. However, there is an advantage that even a high multiplication circuit can be easily integrated into an IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of each point shown in FIG.

FIG. 3 is a connection diagram showing a circuit configuration of a full-wave rectified waveform generation circuit in this embodiment.

FIG. 4 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

1, 1a, 1b, ... 1n 2 multiplication circuit 2a, 2b, ... 2n-1 stage number switching circuit 10 Full-wave rectified waveform generator 11 DC bias correction circuit 12 LPF

Claims (2)

[Scope of utility model registration request] 1. A full-wave rectified waveform generation circuit, a DC bias correction circuit, and an LPF, wherein the full-wave rectified waveform generation circuit is combined with a one-stage differential amplifier circuit and a current mirror to form a feedback circuit. A doubling circuit characterized by using an unused circuit. 2. The n-stage multiplier circuit is connected to n stages (n is an arbitrary integer) with a stage number switching circuit operating by an external signal interposed therebetween, and an arbitrary stage number switching circuit is operated by an external signal. A 2 ⁿ multiplier circuit characterized in that it is configured to obtain 2 ^m (m is an arbitrary integer and m ≦ n).