JPH05110466A - Frequency converter circuit - Google Patents

Abstract

PURPOSE:To obtain a 2nd intermediate frequency signal with high frequency stability even when the frequency stability of a reference oscillator circuit is comparatively low with respect to the frequency converter circuit converting modulated received signals into an intermediate frequency in the mobile set of the mobile communication system. CONSTITUTION:At the time of reception start, 1st and 2nd frequency difference detection means 13, 14 and a 1st frequency control means 15 control a 1st local oscillating frequency of a 1st frequency converter means 11. In this case, the frequency control operation of the 2nd frequency control means 17 is inhibited by a frequency control operation inhibit means 18. When the frequency control state of the 1st frequency control means 15 is converged to a prescribed state, the operation inhibit state of the 2nd frequency control means 17 released. Thus, the control operation of the 2nd local oscillation frequency of the 1st frequency converter means 12 is started by the 3rd frequency difference detection means 16 and the 2nd frequency control means 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit for converting a modulated reception signal into an intermediate frequency signal in a mobile device of a mobile communication system, for example.

[0002]

2. Description of the Related Art Generally, in a mobile communication system such as an automobile telephone system, a reference oscillation circuit is provided, and a local oscillation signal for frequency conversion and a carrier signal for modulation are obtained based on the oscillation output of this reference oscillation circuit. It is like this.

In such a mobile communication system,
With the increasing demand in recent years, effective use of the frequency spectrum by narrowing the channel spacing and interleaving the frequency arrangement is desired.

In order to meet this demand, it is necessary to increase the frequency stability of high frequency signals (hereinafter referred to as "RF signals").

Generally, when an RF signal is transmitted from a base station to a mobile device, high frequency stability can be ensured. This is because the base station can be provided with a highly accurate oscillation circuit of 0.1 ppm or less as the reference oscillation circuit due to its nature.

On the other hand, when the RF signal is transmitted from the mobile station to the base station, high frequency stability cannot be ensured. This is because in a mobile device, the operating environment conditions are severe, and the accuracy of the reference oscillation circuit is limited to about 3 ppm.

Therefore, in order to meet the above demands,
It is necessary to increase the frequency stability of the transmission RF signal of the mobile device.

Therefore, in the conventional mobile equipment, the oscillation frequency of the reference oscillation circuit is controlled based on the RF signal sent from the base station.

With such a configuration, the frequency stability of the RF signal transmitted from the base station is high, so that the frequency stability of the RF signal transmitted from the mobile device can be increased.

By the way, in the mobile communication system as described above, the voice signal which is the main signal is conventionally analog-processed.

In such an analog mobile communication system, since the frequency modulation system is adopted as the modulation system, a very high frequency stability is not required for the received intermediate frequency signal.

On the other hand, in recent years, digital processing of voice processing has been considered in such mobile communication systems.

In this digital mobile communication system, a π / 4 shift QPSK modulation system is generally adopted as a modulation system.

When the π / 4 shift QPSK modulation method is adopted as the modulation method, the deviation of the frequency of the second intermediate frequency signal (hereinafter referred to as the “second intermediate frequency”) which is the input signal of the demodulation circuit becomes the phase error. To be converted. As a result, the error rate of the demodulation output is extremely likely to deteriorate.

Therefore, in the digital mobile communication system, stabilization of the second intermediate frequency is desired.

In order for the second intermediate frequency to be stable, at least the frequency of the received RF signal (hereinafter referred to as "RF frequency") is stable, and the frequency of the local oscillation signal for frequency conversion (hereinafter referred to as "RF frequency"). "Local oscillation frequency")
Must be stable.

In order for the reception RF frequency to be stable, at least the transmission RF frequency must be stable. Further, in order for the local oscillation frequency to be stable, the oscillation frequency of the reference oscillation circuit needs to be stable.

Here, the transmission RF frequency is kept stable in both cases of transmitting the RF signal from the base station to the mobile station and transmitting the RF signal from the mobile station to the base station, as described above. Be drunk

Therefore, regarding the received RF frequency,
High stability can be ensured in both the base station and the mobile device.

On the other hand, regarding the oscillation frequency of the reference oscillation circuit, as described above, the base station can secure a stable frequency, but the mobile device cannot secure a stable frequency.

As a result, with respect to the local oscillation frequency,
The base station can secure high stability, but the mobile device cannot secure high stability.

From the above, at present, the base station can obtain the second intermediate frequency with high stability, but the mobile station cannot obtain the second intermediate frequency with high stability.

Therefore, in order to advance the digitalization of the mobile communication system, it is desirable to immediately stabilize the second intermediate frequency of the mobile device.

[0024]

As described above, in the mobile communication system, it is desired to stabilize the second intermediate frequency of the mobile unit in response to the demand for digitization of all signal processing.

Therefore, an object of the present invention is to provide a frequency conversion circuit capable of stabilizing the second intermediate frequency even if the frequency stability of the reference oscillation circuit is relatively low.

[0026]

FIG. 1 is a block diagram showing the principle configuration of the present invention.

In the figure, 11 is a first frequency converting means for obtaining a first intermediate frequency signal having a frequency of a difference between the modulated received signal and the first local oscillation signal by mixing them. is there.

A second element 12 mixes the converted output of the first frequency converting means 11 and the second local oscillation signal to obtain a second intermediate frequency signal having a difference frequency between them.
Frequency conversion means.

Reference numeral 13 is a first frequency difference detecting means for detecting the difference between the frequency of the converted output of the second frequency converting means 12 and the frequency of the second local oscillation signal.

Reference numeral 14 is a second frequency difference detecting means for detecting the difference between the detection output of the first frequency difference detecting means 13 and the true value of the frequency of the first intermediate frequency signal.

Reference numeral 15 is a first frequency control means for controlling the first local oscillation frequency based on the detection output of the second frequency difference detection means 14.

Reference numeral 16 is a third portion for detecting the difference between the frequency of the converted output of the second frequency converting means 12 and the true value of this frequency.
Is a frequency difference detecting means.

Reference numeral 17 is a second frequency control means for controlling the second local oscillation frequency based on the detection output of the third frequency difference detection means 16.

Reference numeral 18 is frequency control operation prohibiting means for prohibiting the frequency control operation of the second frequency control means 17 until the frequency control state of the first frequency control means 14 converges to a predetermined state.

[0035]

In the above structure, if the frequency stability of the received signal is high, only the frequency deviation ΔfL1 of the first local oscillation signal appears as the frequency deviation in the converted output of the first frequency conversion means 11.

Similarly, in the converted output of the second frequency converting means 12, only the sum of the frequency deviation ΔfL1 of the first local oscillation signal and the frequency deviation ΔfL2 of the second local oscillation signal appears.

As a result, the first frequency difference detecting means 13
From, the frequency of the converted output of the first frequency converting means 11 is detected. Further, the frequency deviation ΔfL1 of the first local oscillation signal is detected from the second frequency difference detection means 14.

Based on the detected output, the first frequency control means 15 controls the first local oscillation frequency.
As a result, the first local oscillation signal has its frequency deviation Δ
The frequency is controlled so that fL1 is removed.

When the frequency control converges to such a value that the frequency deviation ΔfL1 of the first local oscillation signal can be ignored, the frequency control operation prohibiting means 1
The operation prohibition state of the second frequency control means 17 by 8 is released.

At this time, the frequency deviation ΔfL2 of the second local oscillation signal is detected from the third frequency difference detecting means 16. Therefore, when the operation prohibition state of the second frequency control means 17 is released, the frequency of the second local oscillation signal is controlled based on the frequency deviation ΔfL2.

As a result, the frequency of the second local oscillation signal is controlled in the direction in which its frequency deviation is removed.

From the above, the frequency deviation Δ of the first and second local oscillation signals from the converted output of the second frequency converting means 12 is obtained.
fL1 and ΔfL2 can be removed. As a result, the second intermediate frequency signal having high frequency stability can be obtained even if the frequency stability of the reference oscillation circuit is low.

[0043]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In the following description, this invention will be referred to as PSK.
A case where the present invention is applied to a frequency conversion circuit of a mobile device of a digital mobile communication system adopting a π / 4 shift QPSK modulation system as a modulation system will be described as a representative.

First, the configuration from reception of an RF signal to demodulation will be described.

In the figure, the RF signal received by the antenna 21 is supplied to a bandpass filter (hereinafter referred to as "BPF") 22 to remove unnecessary components.

The RF signal from which the unnecessary component has been removed is supplied to the first mixing circuit 23 and mixed with the first local oscillation signal output from the synthesizer 24. As a result, the first intermediate frequency signal is obtained.

The frequency of the first intermediate frequency signal is set to 130 MHz, for example. Therefore, now
Assuming that the frequency of the received RF signal is 820 MHz,
The frequency of the first local oscillation signal is 950 MHz.

The first intermediate frequency signal output from the first mixing circuit 23 is supplied to the BPF 25 to remove unnecessary components.

This first intermediate frequency signal is supplied to the second mixing circuit 26 and is supplied to a voltage controlled crystal oscillation circuit (hereinafter referred to as "V
CXO ”) 27 and is mixed with the second local oscillation signal. As a result, the second intermediate frequency signal is obtained.

Here, the second intermediate frequency is, for example, 4
It is set to 55 KHz. So in this case,
The second local oscillation frequency is 129.5545 MHz.

The second intermediate frequency signal output from the second mixing circuit 26 has its unnecessary component removed by the BPF 28 and then amplified by the amplitude limiting amplifier circuit 29.

This amplified output is supplied to the demodulation circuit 30, and the baseband signal is demodulated.

The above is the configuration from the reception of the RF signal to the demodulation. Next, the configuration of an automatic frequency control (hereinafter referred to as “AFC”) circuit for stabilizing the second intermediate frequency will be described.

As this AFC circuit, there are a first AFC circuit for controlling the first local oscillation frequency and a second AFC circuit for controlling the second local oscillation frequency.

First, the configuration of the first AFC circuit will be described.

The amplified output of the amplitude limiting amplifier circuit 29 is
Further, it is supplied to the modulated wave removing circuit 31 and is used for extracting a carrier signal for modulation.

The extracted output of the modulated wave removing circuit 31 is 1/1
The frequency division circuit 32 divides the frequency by 1/10. The frequency division ratio 1/10 of the frequency division circuit 32 is set to the same frequency division ratio 1/10 as the frequency division target 1/10 of the frequency division circuit described later.

The frequency-divided output of the frequency-dividing circuit 32 is frequency-counted by the frequency counter 33.

As a result, data indicating a frequency that is 1/10 of the actual frequency of the second intermediate frequency signal is obtained. This data is supplied to one input terminal of the adder circuit 34.

The oscillation output of the VCXO 27 is
The frequency is divided by 1/10 by the 1/10 frequency dividing circuit 35. Here, the frequency division ratio of the 1/10 frequency divider circuit 35 is determined by the operating frequency of the frequency counter 36 described later.

The frequency output of the frequency dividing circuit 35 is counted by the frequency counter 36. As a result, data indicating a frequency that is 1/10 of the actual frequency of the second local oscillation signal is obtained. This data is supplied to the other input terminal of the adder circuit 34.

As a result, the data showing the actual frequency of the first intermediate frequency signal is obtained from the adder circuit 34.
This data is supplied to one input terminal of the subtraction circuit 37.

At the other input terminal of the subtraction circuit 37,
Data indicating the frequency that is 1/10 of the true value of the first intermediate frequency stored in advance in the table 38 is supplied.

As a result, the subtraction circuit 37 obtains data indicating the frequency which is 1/10 of the frequency deviation of the first local oscillation signal.

This data is converted into an analog signal by a digital / analog conversion circuit (hereinafter referred to as "D / A conversion circuit") and then supplied to the reference oscillation circuit 35 as a control signal.

As a result, the oscillation frequency (eg, 12.8 MHz) of the reference oscillation circuit 35 is controlled based on the frequency deviation of the second intermediate frequency signal.

The oscillation output of the reference oscillation circuit 40 is supplied to the synthesizer 24 as a reference signal. As a result, the first local oscillation signal is synchronized with the oscillation output of the reference oscillation circuit 40.

The above is the configuration of the first AFC circuit. Next, the configuration of the second AFC circuit will be described.

The amplified output of the amplitude limiting amplifier circuit 29 is
Further, the frequency is counted by the frequency counter 41. This count output is supplied to one input terminal of the subtraction circuit 42.

At the other input terminal of the subtraction circuit 42,
The true value of the second intermediate frequency stored in advance in the table 43 is supplied.

As a result, from the subtraction circuit 42, until the AFC operation of the first AFC circuit converges to a state where the frequency deviation of the first local oscillation signal can be ignored, Data indicating the sum of the frequency deviations of the local oscillation signals of 2 are obtained.

On the other hand, when the AFC operation of the first AFC circuit converges to the above-mentioned state, data indicating the frequency deviation of the second local oscillation signal is obtained.

This data is supplied to the D / A conversion circuit 45 via the switch circuit 44 and converted into an analog signal. This converted output is supplied to the VCXO 27 as a control signal.

As a result, the frequency of the second local oscillation signal is controlled based on the frequency deviation.

In the figure, reference numeral 47 indicates the frequency counters 33 and 3 based on the oscillation output of the reference oscillation circuit 40.
6 is a timing generation circuit for generating timing signals for controlling the operations of 6, 41 and the like.

The above is the configuration of the second AFC circuit. The AFC operation of the second AFC circuit is prohibited until the AFC operation of the first AFC circuit converges to a predetermined state. Therefore, next, a configuration for prohibiting the AFC operation will be described.

The switch circuit 44 is set to the OFF state at the start of reception, and is switched to the ON state when the frequency deviation of the first local oscillation signal converges to a negligibly small value.

When the switch circuit 44 is off, D /
The A conversion circuit 45 outputs an analog signal having a constant voltage. As a result, the oscillation frequency of the VCXO 27 is fixed to a certain initial value.

ON / OFF of the switch circuit 44 is controlled by the switch control circuit 46. This switch control circuit 46 has a predetermined threshold value, and when the output level of the subtraction circuit 37 is higher than this threshold value, it sets the switch circuit 44 to the off state, and when it becomes lower than the threshold value, it is turned on. It is set to.

The threshold value is set so as to be the output level of the subtraction circuit 37 when the frequency deviation of the second local oscillation signal becomes a value that can be ignored.

As a result, the AFC operation of the second AFC circuit is started only when the frequency deviation of the first local oscillation signal becomes negligible due to the AFC operation of the first AFC circuit. ..

The above is the overall configuration of FIG. Next, the configurations of the synthesizer 24 and the modulated wave removing circuit 31 will be described.

First, the structure of the synthesizer 24 will be described. FIG. 3 is a block diagram showing an example of a specific configuration of the synthesizer 24.

In the figure, reference numeral 241 is a voltage controlled oscillator circuit (hereinafter referred to as "VCO") which outputs a first local oscillation signal.

The oscillation output of the VCO 241 is supplied to the first mixing circuit 23 as the first local oscillation signal and is divided by the variable frequency dividing circuit 242.

This frequency-divided output is supplied to one input terminal of the phase comparison circuit 243. A signal obtained by dividing the oscillation output of the reference oscillation circuit 40 by the frequency dividing circuit 244 is supplied to the other input terminal of the phase comparison circuit 243.

As a result, the phase comparison circuit 243 detects a phase error between the oscillation output of the reference oscillation circuit 40 and the first local oscillation signal.

The detected output is integrated by the integrating circuit 245 and then supplied to the VCO 241 as a control signal. As a result, the first local oscillation signal is phase-locked with the oscillation output of the reference oscillation circuit 40.

The variable frequency dividing circuit 242 divides the first local oscillation signal into a signal of 25 KHz, for example. In this case, the frequency division ratio of the frequency dividing circuit 242 is controlled based on the tuning data of the receiving channel.

As a result, the first local oscillation frequency is adjusted to the frequency corresponding to the reception channel.

Similarly to the variable frequency dividing circuit 242, the frequency dividing circuit 245 also divides the oscillation output of the reference oscillation circuit 40 into a signal of 25 KHz. However, the frequency division ratio in this case is fixed.

Next, the structure of the modulated wave removing circuit 31 will be described. FIG. 4 is a block diagram showing an example of a specific configuration of the modulated wave removing circuit 31.

In the figure, reference numeral 311 denotes 8 for multiplying the second intermediate frequency signal output from the amplitude limiting amplifier circuit 8 by 8.
It is a multiplication circuit. The multiplied output of this 8-times multiplication circuit 311 is
The center frequency is the carrier frequency of the second intermediate frequency signal (45
5 KHz) to the BPF 312 of 8 times.

As a result, the carrier component of the second intermediate frequency signal is extracted. This extracted output is the 1/8 frequency divider circuit 3
It is divided by ⅛ by 13. As a result, the extracted carrier component is returned to the original frequency.

In the above configuration, first, the AFC operation will be described.

This AFC operation is started by receiving an RF signal. However, when the RF signal is received, since the switch circuit 44 is set to the off state, the AFC operation of the second AFC circuit is not executed, and only the AFC operation of the first AFC circuit is executed.

On the other hand, the AFC operation of the first AFC circuit progresses, and the frequency deviation ΔfL of the first local oscillation signal.
When 1 converges to a value that can be ignored, the switch circuit 44 is set to the ON state.

As a result, in such a state, the AFC operation of both AFC circuits is executed.

Therefore, first, A of the first AFC circuit
The FC operation will be described.

In general, the RF signal sent from the base station is generated by using the reference oscillation circuit whose accuracy is 0.1 ppm or less as described above.

Therefore, the true value of this RF frequency is fR
Then, the actual frequency of the received RF signal output from the BPF 22 can also be regarded as fR.

On the other hand, the first local oscillation signal output from the frequency synthesizer 24 is generated based on the oscillation output of the reference oscillation circuit 40 having an accuracy of about 3 ppm.

Therefore, this first local oscillation signal is
It has a frequency deviation corresponding to the frequency deviation of the reference oscillation circuit 40.

If this frequency deviation is ΔfL1, then
The actual frequency of the local oscillation signal is fL1 + ΔfL1. Here, fL1 is the true value of the frequency of the first local oscillation signal.

As a result, the actual value of the frequency fIF1 of the first intermediate frequency signal output from the first mixing circuit 33 is fIF1 = fR- (fL1 + ΔfL1) (1).

The second local oscillation signal is VCXO2
It is output from 7. The accuracy of this VCXO 27 is not so high because it is provided in the mobile device. Therefore, this second local oscillation signal also has a frequency deviation according to the accuracy of the VCXO 27.

If this frequency deviation is ΔfL2, the second
The actual frequency of the local oscillation signal is fL2 + ΔfL2. Here, fL2 is the true value of the second local oscillation frequency.

As a result, the actual value of the frequency fIF2 of the second intermediate frequency signal output from the second mixing circuit 34 becomes fIF2 = fR- (fL1 + ΔfL1)-(fL2 + ΔfL2) ... (2).

As a result, the addition circuit 34 outputs the equation (1)
The data indicating the value obtained by dividing the first intermediate frequency fIF1 shown in 1 by 1/10 is obtained.

As a result, the subtraction circuit 37 obtains data indicating the frequency obtained by dividing the frequency deviation ΔfL1 of the first local oscillation signal by 1/10.

As a result, the oscillation frequency of the reference oscillation circuit 40 is controlled based on the frequency deviation ΔfL1 of the first local oscillation signal.

As a result, the first local oscillation signal output from the synthesizer 24 is controlled so that its frequency deviation ΔfL1 is removed.

Next, the AFC operation of the second AFC circuit will be described.

By the AFC operation of the first AFC circuit described above, when the frequency deviation ΔfL1 of the first local oscillation signal converges to a value that can be ignored, the value of the subtraction output of the subtraction circuit 37 reaches a value that can also be ignored. Converge.

As a result, the switch control circuit 46 switches the switch circuit 44 from the ON state to the OFF state. As a result, the AFC operation of the second AFC circuit is started.

At this time, the value of the subtraction output of the subtraction circuit 42 is substantially equal to the frequency deviation ΔfL2 of the second local oscillation signal.

As a result, the second local oscillation signal output from the VCO 27 is controlled based on the frequency deviation ΔfL2. As a result, the second local oscillation signal is controlled so that its frequency deviation ΔfL2 is removed.

By the above AFC operation, the frequency deviation Δf
The second intermediate frequency signal from which L1 and ΔfL2 have been removed is output from the second mixing circuit 26. As a result, the demodulation circuit 3
At 0, no phase error occurs due to the frequency deviation of the second intermediate frequency signal.

Next, the modulated wave removing operation of the modulated wave removing circuit 31 will be described.

In the case of the analog frequency modulation method, the frequency spectrum of the modulated signal is the Bessel function B (fD / f represented by the ratio of the modulation frequency fS to the frequency deviation fD.
Based on S), as shown in FIG.
They are arranged at intervals of the modulation frequency fs with 0 as the center.

On the other hand, digital π / 4 shift QPS
In the case of K modulation, the frequency spectrum of the modulated signal is lined up in a packed state as shown in FIG.

This is because the digital modulation signal is scrambled on the transmission side. That is, when the digital modulation signal is scrambled, the digital modulation signal has the same frequency band as the noise signal.

The reason why the digital modulation signal is scrambled is to prevent the code fragment of the digital modulation signal.

That is, in the π / 4 shift QPSK modulation, the code "1" or "0" of the digital modulation signal.
May line up consecutively.

When such a deviation of the code occurs, the frequency spectrum of the modulated signal becomes the carrier frequency f0.
It deviates to the positive side or the negative side with (= fR-fL1-fL2) as the center.

As a result, if the frequency of this modulated signal is directly counted, a count error may occur.

Therefore, as described above, the digital modulation signal is scrambled on the transmitting side so as to prevent the code fragment.

However, the degree of offset prevention effect due to scrambling is proportional to the period of the PN (noise) pattern.

Therefore, it is necessary to lengthen the period of the PN pattern in order to obtain the desired offset prevention effect. Specifically, the symbol rate of the modulated signal is 21 Kbps,
If the PN pattern has 15 stages, one frame is
The cycle is about 1.5 seconds.

On the other hand, the count time of the frequency counter 32 cannot be lengthened because it is necessary to shorten the time from the start of reception until the AFC operation converges. Specifically, the time is set to about 100 msec to 1 sec.

Therefore, even if the modulated signal is scrambled, in reality, the frequency can be counted only partially (100 msec to 1 sec) during one period of the PN pattern, so that the counting error can be almost prevented. Can not.

Therefore, in this embodiment, the carrier component of the second intermediate frequency signal is extracted from the amplified output of the amplitude limiting amplifier circuit 29, and the frequency of this carrier component is counted.

That is, the amplified output of the amplitude limiting amplifier circuit 29 is first multiplied by 8 by the 8 × circuit 311 in FIG. As a result, as shown in FIG. 6B, components other than the carrier component S1 of the modulated signal (second intermediate frequency signal) are suppressed, and this carrier component S1 is extracted.

However, in the case of π / 4 shift QPSK modulation,
When the modulated signal is multiplied by 4, 8f0 + fS, 8f0-f
The components S2, S3 having a frequency of S are obtained.

Therefore, in this embodiment, the quadruple multiplication circuit 31
BPF312 whose center frequency is 4f0
I am trying to pass it through. As a result, as shown in FIG. 6C, the components S1 and S2 are removed from the octupled output, and only the carrier component is extracted.

After that, the extraction output of the BPF 312 is 1 /
The frequency-dividing circuit 314 divides the frequency by 1/8. As a result, the frequency of the carrier component S1 is returned to the original frequency.

According to the configuration in which the modulated signal is removed from the modulated wave and the carrier signal is extracted in this way, the counting operation is not affected by clogging or deviation of the frequency spectrum, and thus a counting error occurs. There is no.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, since the first and second local oscillation frequencies fL1 and fL2 are controlled by the first and second AFC circuits, the frequency stability of the reference oscillation circuit 36 is relatively low. Also, the frequency stability of the second intermediate frequency signal can be increased.

Thus, it is possible to prevent the demodulation circuit 30 from generating a phase error based on the frequency deviation of the second intermediate frequency signal.

(2) When counting the second intermediate frequency fIF2, the carrier component S1 of the second intermediate frequency signal is extracted and the frequency of this carrier component S1 is counted. The frequency fIF2 can be accurately counted.

(3) If the second AFC circuit obtains the frequency deviation ΔfL2 of the second local oscillation signal, the second
Since the intermediate frequency fIF2 is directly counted, the convergence time of the AFC operation of the second AFC circuit can be shortened.

That is, in order to obtain the frequency deviation ΔfL2, it is possible to count the frequency of the second local oscillation signal output from the VCXO 27. For example, in FIG.
In, a method of inputting the output of the frequency counter 36 to the subtraction circuit 42 can be considered.

However, in this case, since the second local oscillation frequency fL2 is as high as 129.5545 MHz, the frequency counter 41 normally composed of CMOS transistors cannot count.

Therefore, in such a case, it is necessary to divide the frequency of the second local oscillation frequency fL2.

However, when performing such frequency division processing,
To obtain the same counting accuracy as when the frequency division processing is not performed, it is necessary to lengthen the counting time. As a result, in this case, the convergence time of the AFC operation of the second AFC circuit becomes long.

On the other hand, in this embodiment, the second intermediate frequency fIF2 is directly counted.
Since the second intermediate frequency fIF2 is 455 KHz, it can be sufficiently counted even by the frequency counter 41 composed of CMOS transistors.

As a result, in this embodiment, the convergence time of the AFC operation can be shortened as compared with the case of counting the second local oscillation frequency fL2.

(4) Further, as described above, the count time of the second AFC circuit can be shortened,
It is also possible to repeat the counting operation a plurality of times within a preset time for the AFC operation of the AFC circuit.

As a result, the average value of the plurality of count values can be used as the final count value, so that the counting accuracy can be improved.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to such an embodiment.

(1) For example, in the above embodiment, the carrier component S1 extracted by the BPF 312 of the modulated wave removing circuit 31 is divided by 1/8 by the 1/8 dividing circuit,
The case where the frequency of the carrier component S1 is returned to the original frequency has been described.

However, in the present invention, the carrier component S1
The extracted output of the BPF 312 may be directly counted without returning the frequency of 1 to the original frequency.

With such a configuration, it is possible to count a higher frequency than in the previous embodiment, so if the same time as in the previous embodiment is set as the count time,
The counting accuracy can be improved more than in the previous embodiment.

On the other hand, if the counting accuracy is the same as that of the previous embodiment, the counting time can be made shorter than that of the previous embodiment.

(2) Further, in the previous embodiment, the subtraction circuit 3
The case where the convergence state of the first AFC circuit is monitored by monitoring the output level of No. 7 has been described.

However, the present invention may employ any monitoring configuration as long as it can monitor the convergence state of the first AFC circuit. For example, the frequency of the first local oscillation signal output from the synthesizer 24 may be monitored.

(3) Further, in the previous embodiment, the subtraction circuit 4
The case where the switch circuit 44 is provided in the second output stage and the AFC operation of the second AFC circuit is prohibited by the control of the switch circuit 44 has been described.

However, the present invention may have any structure as long as the AFC operation of the second AFC circuit is not substantially executed.

(4) Also, in the previous embodiment, the subtraction circuit 4
The case where the count output of the frequency counter 41 is used as one of the two inputs has been described.

However, in the present invention, the count output of the frequency counter 33 may be used as shown by the broken line in FIG. In this case, the data stored in the table 43 is 1/10 of that in the previous embodiment.

According to such a configuration, the convergence time of the AFC operation becomes long, but the circuit configuration can be simplified.

(5) Further, in the above embodiment, the case where the present invention is applied to the frequency conversion circuit of the mobile device of the mobile communication system has been described. However, the present invention is applicable to frequencies of communication systems other than such a system. It can also be applied to a conversion circuit.

(6) In addition to this, it is needless to say that the present invention can be variously modified without departing from the scope of the invention.

[0166]

As described in detail above, according to the present invention,
In a mobile device of a digital mobile communication system, it is possible to provide a frequency conversion circuit that can obtain a second intermediate frequency with high frequency stability even if the reference oscillator circuit has low frequency stability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of the synthesizer shown in FIG.

4 is a block diagram showing a configuration of a modulated wave removing circuit of FIG.

FIG. 5 is a diagram showing a frequency spectrum of a modulated signal in an analog frequency modulation method.

FIG. 6 is a diagram for explaining the operation of the modulated wave removing circuit.

[Explanation of symbols]

11 1st frequency conversion means 12 2nd frequency conversion means 13 1st frequency difference detection means 14 2nd frequency difference detection means 15 1st frequency control means 16 3rd frequency difference detection means 17 2nd frequency Control means 18 Frequency control operation prohibiting means 24 Synthesizer (phase synchronizing means) 27 VCXO (voltage controlled oscillating means) 31 Modulated wave removing circuit (carrier component extracting means) 33, 41 Frequency counter (frequency counting means) 311 8 multiplication circuit (N Multiplying means) 312 BPF (N multiplying means) 313 1/8 frequency dividing circuit (1 / N frequency dividing means)

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Isao Shimizu 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (8)

[Claims] 1. A first frequency conversion means (11) for obtaining a first intermediate frequency signal having a frequency of a difference between them by mixing the modulated reception signal and the first local oscillation signal.
And a second frequency conversion means for obtaining a second intermediate frequency signal having a frequency that is the difference between the two by mixing the conversion output of the first frequency conversion means (11) and the second local oscillation signal.
(12), first frequency difference detection means (13) for detecting a difference between the frequency of the converted output of the second frequency conversion means (12) and the frequency of the second local oscillation signal, and The detection output of the first frequency difference detection means (13) and the first
Second frequency difference detecting means (14) for detecting a difference between the true frequency of the intermediate frequency signal and the first local portion based on the detection output of the second frequency difference detecting means (14). A first frequency control means (15) for controlling the frequency of the oscillation signal, and a third frequency difference for detecting the difference between the frequency of the converted output of the second frequency conversion means (12) and the true value of this frequency. A detection means (16); a second frequency control means (17) for controlling the frequency of the second local oscillation signal based on the detection output of the third frequency difference detection means (16); Frequency control operation prohibiting means (18) for prohibiting the frequency control operation of the second frequency control means (17) until the frequency control state of the first frequency control means (15) converges to a predetermined state.
A frequency conversion circuit comprising: 2. The first and third frequency difference detecting means (13,
16) is a carrier component extracting means (31) for extracting a carrier component of the converted output of the second frequency converting means (12) and a frequency count for counting the frequency of the extracted output of the carrier component extracting means (31) 3. The frequency conversion circuit according to claim 2, wherein the means (33, 41) is configured to detect the frequency of the converted output of the second frequency conversion means (12). 3. The frequency conversion circuit according to claim 2, wherein the received signal is PSK modulated. 4. The carrier component extracting means (31) extracts the carrier component by multiplying the conversion output of the second frequency converting means (12) by N (N is an integer of 2 or more). The frequency conversion circuit according to claim 3, wherein the frequency conversion circuit is configured as follows. 5. The carrier component extracting means (31) outputs the converted output of the second frequency converting means (12) as N (N is 2).
By multiplying by N, the frequency of the carrier component is calculated by dividing the extracted output of the N multiplier (311,312) and the N multiplier (311,312) by 1 / N. 4. The frequency conversion circuit according to claim 3, further comprising 1 / N frequency dividing means (313) for returning the frequency to the frequency. 6. The first frequency control means (15), a reference oscillation means (40) whose oscillation frequency is controlled based on the detection output of the second frequency difference detection means (14), The oscillation output of the reference oscillating means (40) is used as a reference signal, and a phase synchronizing means (24) for synchronizing the phase of the first local oscillation signal with the reference signal is provided. The frequency conversion circuit according to claim 1. 7. The second frequency control means (17) controls an oscillation frequency based on a detection output of the third frequency difference detection means (16), and the oscillation output is the second local oscillation. 2. The frequency conversion circuit according to claim 1, wherein the frequency conversion circuit is a voltage controlled oscillation means (27) used as a signal. 8. The frequency control operation prohibiting means (18) determines whether or not the detection output of the second frequency difference detecting means (14) converges to a predetermined value, thereby determining the first frequency difference. The frequency conversion circuit according to claim 1, characterized in that it is configured to judge whether or not the frequency control state of the frequency control means (15) has converged to a predetermined state.