JPH05110112A - Nonvolatile semiconductor memory and its readout method - Google Patents

Abstract

PURPOSE:To reduce the dimension of a memory cell with no need of a source region and a selection separation transistor by making an MNOS capacitor with a drain region serve as the memory cell and by detecting charge transfer due to capacitor charge current to read out information. CONSTITUTION:A title memory consists of an MNOS structure capacitor and a drain region adjacent to it. A voltage lower than a threshold voltage in erasure state is applied to a polysilicon electrode 7 to keep the surface of a silicon substrate of the MNOS capacitor on storing charges. After precharged to 0V, an N<+> drain region 3 is separated from another circuit, and a positive voltage as high as possible is applied to the polysilicon electrode 7 over a range lower than a threshold voltage in write-in state. At this time, erasure state of low threshold voltage inverts the surface of a silicon substrate of an MNOS capacitor to cause electrons to flow from an N<+> drain region 2, resulting in a rise in potential of the N<+> drain region 3. This change in potential is detected for readout.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, particularly a non-volatile semiconductor memory suitable for high-density integration and a reading method thereof.

[0002]

2. Description of the Related Art A MNOS type EEPROM has been put into practical use as one of nonvolatile semiconductor memories capable of being electrically written and erased. Conventionally, this MNOS type EEPROM
The memory device has a MNOS gate as shown in FIG.
It consisted of a field-effect transistor with a structure.

In FIG. 5, 21 is a P-type silicon substrate,
22 is N⁺Drain region, 23 is N ⁺Source area, 24
Is a thin silicon oxide film that can be a tunneling medium, 2
5 is a silicon nitride film, 26 is a polysilicon gate electrode
is there. The operation of the conventional memory device shown in FIG. 5 will be briefly described.
To do. The write operation starts with the polysilicon gate electrode.
Apply a high voltage (Vpp) of about 15V to 26 and keep it at 0V.
Was N⁺Drain region 22 or N⁺Source region 23
From the surface of the silicon substrate under the polysilicon gate electrode
Introduce electrons as inversion charge. At this time, silicon base
Inversion layer on the plate surface is N⁺Keep the same 0V as the drain region 22
The thin silicon oxide that is the gate insulating film because it is dripping
Is a high electric field applied to the laminated film of the film 24 and the silicon nitride film 25?
Therefore, the electrons in the inversion layer are thinly oxidized by tunneling.
The transistor film 24 is tunneled and is transferred into the silicon nitride film 25.
Threshold voltage as a transistor rises
It In addition, the erase operation keeps the P-type silicon substrate 21 at 0V.
The polysilicon gate electrode 26 has a negative voltage of about -15V.
By applying a high voltage (-Vpp), a voltage is applied to the silicon nitride film 25.
The wrapped electrons are tunneled to the silicon substrate side.
The threshold voltage of the transistor
Let me do it. And the read operation is
The difference in pressure is determined by the polysilicon gate electrode 26 and N⁺Dray
Between source and drain when voltage is applied to the drain region 22
Read as the difference in the current of the
I am responding.

[0004]

However, when a memory cell array is constructed using the conventional MNOS memory transistors as described above, as shown in FIG. 6, selective writing and reading for each bit of the memory cell array is performed. At this time, since it is necessary to disconnect the unnecessary MNOS memory transistor from the common source line, the selective separation transistor 29 connected in series with the MNOS memory transistor 28 is required for each bit. Therefore, there is a problem that the cell area per bit becomes very large, which hinders the increase in capacity and integration.

Therefore, an object of the present invention is to provide a non-volatile semiconductor memory and a method of reading the same, which can achieve a large reduction in cell area and enable large-capacity integration.

[0006]

The present invention adopts the following constitution in order to solve the above problems. That is,
A nonvolatile semiconductor memory according to a first aspect of the present invention is a thin-type silicon oxide film formed at a predetermined position on a semiconductor substrate of one conductivity type, an insulating layer and a conductive layer sequentially stacked on the silicon oxide film, It is composed of a diffusion region of another conductivity type formed in the semiconductor substrate adjacent to one end of the silicon oxide film.

In addition, the reading method of the non-volatile semiconductor memory according to the second aspect of the invention is such that the information is read out by detecting the movement of charges due to the charging current of the capacitor of the MNOS structure in the non-volatile semiconductor memory of the first aspect. ing.

[0008]

According to the structure of the present invention, the source region in the case of forming the memory cell array can be omitted, and since there is no common source region, the selecting transistor can be omitted. It can be reduced significantly. When a voltage is applied to the word line of the upper electrode of the capacitor having the MNOS structure, MN
Since the charging current to the OS capacitor is different between the writing state and the erasing state, this can be used to read information.

[0009]

1 is a cross-sectional view showing the structure of a nonvolatile semiconductor memory according to an embodiment of the present invention, which is composed of a capacitor of MNOS structure and a drain region adjacent to the capacitor. In FIG. 1, 2 is a P-type silicon substrate, 3 is N ⁺
Drain region 4 is 2 nm, which can be a tunneling medium
A thin silicon oxide film, 5 is a silicon nitride film having a thickness of about 30 nm, and 7 is a polysilicon electrode.

The operation of the nonvolatile semiconductor memory 1 having the above structure will be described. First, the write operation is the same as in the case of the conventional MNOS transistor, in which the N ⁺ drain region 2 is kept at 0 V and a high voltage (Vpp) of about 15 V is applied to the polysilicon electrode 7 to set the threshold of the MNOS capacitor. Increase the voltage. Similarly to the case of the MNOS transistor of the conventional example, the erasing operation keeps the P-type silicon substrate 2 at 0 V, and the polysilicon electrode 7 is -1.
The threshold voltage of the MNOS capacitor is lowered by applying a negative high voltage (-Vpp) of about 5V or by keeping the polysilicon electrode 7 at 0V and applying Vpp to the P-type silicon substrate 1. ..

Next, in the read operation, first, a voltage lower than the threshold voltage in the erased state (low threshold state) is applied to the polysilicon electrode 7 to bring the silicon substrate surface of the MNOS capacitor into the accumulated state. .. Then, after precharging the N ⁺ drain region 3 to 0 V, the N ⁺ drain region 3 is separated from other circuits, and a positive voltage as high as possible within the range lower than the threshold voltage in the written state is applied to the polysilicon electrode 7. At that time, if the MNOS capacitor is in the writing state, MN
Although electrons do not flow into the surface of the silicon substrate of the OS capacitor, in the erased state where the threshold voltage is low, the surface of the silicon substrate of the MNOS capacitor is inverted and electrons flow from the N ⁺ drain region 2 to the N ⁺ drain region 3. The potential rises. Reading is performed by detecting the change in the potential of the N ⁺ drain region 3.

FIG. 2 is a diagram showing a configuration in which the nonvolatile semiconductor memory of FIG. 1 is configured as a memory cell array, and 10 shows a MNOS capacitor with a drain region which is the nonvolatile semiconductor memory of the present invention. In this non-volatile semiconductor memory, the source region as in the conventional example is eliminated, and therefore the read operation is performed by detecting the movement of charges due to the charging current of the MNOS capacitor. Therefore, even if the selective separation transistor is not used,
It is possible to write and read bit by bit. The operation will be described below.

First, in the write operation, only the bit line of the cell to be written is set to 0V and the other bit lines are set to 1V.
A high voltage (Vpp) of about 5V is applied. Then, when Vpp is applied only to the word line of the write target cell and 0 V is applied to the other bit lines, only the write target cell is written under the write operation condition described above. Other states (polysilicon electrode voltage and N ⁺
The drain region voltages are Vpp and Vpp, 0V and V, respectively.
No writing is performed in the cells of pp, 0V and 0V) because the inversion charge is not introduced under the polysilicon electrode 7.

Next, in the erase operation, the P-type silicon substrate is set to 0.
By keeping the voltage at V and applying a negative voltage (-Vpp) of about -15 V to a certain word line, the memory cells associated with that word line can be erased at once.
In addition, in the read operation, after applying a voltage lower than the threshold voltage in the erased state (for example, about −3V if the threshold voltage in the erased state is −2V) to all the word lines, the desired cell The bit line is precharged with 0 V, and then the bit line is disconnected from the power supply and left floating. Then, when a positive voltage as high as possible within the range lower than the threshold voltage in the written state (for example, about 4 V if the threshold voltage in the written state is 5 V) is applied to the word line of the desired cell, the cell Is in an erased state (state in which the threshold voltage is low), electrons flow from the drain into the surface of the silicon substrate of the MNOS capacitor, and the potential of the bit line rises. This change in potential is read by a highly sensitive sense amplifier such as a flip-flop type.

3 and 4 are a sectional view and a plan view showing the structure of the memory cell array, 2 is a P-type silicon substrate, 3 is an N ⁺ drain region, 4 is a thin silicon oxide film which can be a tunneling medium, 5 is a silicon nitride film, 11 is a silicon oxide film for isolation formed by the LOCOS method, 12 is a word line made of polysilicon, 1
Reference numeral 3 is an interlayer insulating film made of a silicon oxide film, and 14 is a bit line made of aluminum. In this embodiment, the number of contacts of the bit line 14 to the N ⁺ drain region 2 is one for each 2 bits, and thereby higher integration is achieved. Further, the silicon oxide film 4 and the silicon nitride film 5 other than the word lines were simultaneously etched and dry-etched for forming the word lines 12. In addition, N ⁺ drain region 2
Are self-aligned using the word line 12 made of polysilicon as a mask.

In the above embodiment, the method of applying the negative high voltage (-Vpp) to the word line to erase is described. However, the memory cell array is formed in the P type region on the N type silicon substrate. To 0V on all word lines,
It is also possible to selectively erase cells in the P-type region by applying a positive high voltage (Vpp) to the P-type region. In this case, the negative high voltage (-Vpp) is not required, and the peripheral circuit can be simplified.

Further, in the above embodiments, the laminated film of the silicon oxide film and the silicon nitride film is used as the insulating film of the MNOS capacitor, but the surface of the silicon nitride film is oxidized to change to the silicon oxide film. Let MON
The same effect can be obtained by using an OS structure capacitor. Further, as the insulating film, a high dielectric film such as aluminum oxide (Al ₂ O ₃ ) or tantalum oxide (Ta ₂ O ₃ ) can be used instead of the silicon nitride film.

[0018]

As described above, according to the nonvolatile semiconductor memory and the reading method thereof of the present invention, the MNOS capacitor with the drain region is used as the memory cell, and the movement of the charge due to the charging current of the capacitor is detected to detect the information. , The source region and the selective isolation transistor, which have been required in the past, are no longer required, the size of the memory cell can be significantly reduced, and a large-capacity nonvolatile semiconductor memory can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory which is an embodiment of the present invention.

FIG. 2 is a circuit diagram when a nonvolatile semiconductor memory is configured as a memory cell array.

FIG. 3 is a cross-sectional view showing a configuration of a memory cell array.

FIG. 4 is a plan view showing a configuration of a memory cell array.

FIG. 5 is a cross-sectional view showing a configuration of an MNOS transistor which is a conventional nonvolatile semiconductor memory.

FIG. 6 is a circuit diagram of a conventional memory cell array.

[Explanation of symbols]

2 P-type silicon substrate 3 N ⁺ drain region 4 silicon oxide film 5 silicon nitride film 7 polysilicon gate electrode

Claims (2)

[Claims] 1. A thin silicon oxide film formed at a predetermined position on a semiconductor substrate of one conductivity type, an insulating layer and a conductive layer sequentially laminated on the silicon oxide film, and one end of the silicon oxide film. A non-volatile semiconductor memory provided with a diffusion region of another conductivity type formed adjacently in the semiconductor substrate. 2. A thin silicon oxide film formed at a predetermined position on a semiconductor substrate of one conductivity type, an insulating layer and a conductive layer sequentially stacked on the silicon oxide film, and one end of the silicon oxide film. A method of reading a non-volatile semiconductor memory, comprising a diffusion region of another conductivity type formed adjacent to the semiconductor substrate, wherein the charge due to a charging current to a capacitor composed of a conductive layer of a semiconductor element and the semiconductor substrate is provided. A method for reading a non-volatile semiconductor memory, which is characterized by detecting movement of a memory cell and reading information.