JPH05102828A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To set the load drive capability of a buffer in response to a load by providing a signal line through which a control signal operating drivers whose number corresponds to the load capacitance added to a common output terminal is supplied to its input terminal to the circuit. CONSTITUTION:Each of drivers 9a-9n is provided with an input terminal 10, a control input terminal 11 to which a state control signal of the drivers is inputted and an output terminal 12. The output buffer circuit is provided with an n-bit register 13 latching signals 14a-14n controlling the operating state of N sets of the drivers 9a-9n and has an input terminal 16 and an output terminal 17. When a large load capacitance is added to the output terminal 17 and data are set to all of n-bits of the register 13, the state control signals 14a-14n go to H. Since an H signal is inputted to each control input of the drivers 9a-9n, they are in the operating state to set a large drive capability. The drive capability of the output drive circuit is changed by setting required data in response to the load capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a buffer circuit capable of setting an optimum drive capacity.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a conventional semiconductor integrated circuit, particularly an output buffer circuit used in an ECL gate array. 7A is an output buffer circuit formed in the master process, FIG. 7B is an output buffer circuit after a slicing process that requires high load driving capability, and FIG. 7C is low load driving capability. This is an output buffer circuit after the slicing step. In the figure, 1a to 1c are transistors, 2a to 2g are resistance elements, 3 is an input terminal, and 4 is an output terminal. The transistors 1a and 1b and the resistance elements 2a to 2f form a current switching circuit, and the transistor 1c and the resistance element 2g form an emitter follower circuit.

Next, a circuit configuration according to the magnitude of the load capacitance added to the output terminal of the output buffer circuit having the above configuration will be described. First, when a large load capacitance is added to the output terminal 4, the output buffer circuit of the transistors 1a to 1c and the resistance elements 2a to 2g formed in the master process shown in FIG. ), The resistors of the current switching circuit are wired in parallel with the resistance elements 2a and 2b, the resistance elements 2c and 2d, and the resistance elements 2e and 2f. The output terminal 4 is wired so as to have an open emitter output form. With this wiring, the circuit current can be set to a high current.

Next, when a small load capacitance is added to the output terminal 4, the output buffer circuit of the transistors 1a to 1c and the resistance elements 2a to 2g formed in the master process shown in FIG. As shown in FIG. 7C, the resistance of the current switching circuit is set to the resistance elements 2a, 2d, 2e.
And the resistance of the emitter follower circuit is wired by the resistance element 2g. With this wiring, the circuit current can be set to a low current.

FIG. 8 is a diagram showing another conventional semiconductor integrated circuit, particularly an output buffer circuit used in a CMOS gate array, FIG. 8 (A) being an output buffer circuit in a master process, and FIG. 8 (B). An output buffer circuit after the slicing process that requires a high load driving capability is shown, and FIG. 8C shows an output buffer circuit after the slicing process that requires a low load driving capability. In the figure, 5a and 5b are PMOS
Transistors, 6a and 6b are NMOS transistors, 7 is an input terminal, and 8 is an output terminal.

Next, a circuit configuration according to the magnitude of the load capacitance added to the output terminal of the output buffer circuit having the above configuration will be described. First, when a large load capacitance is added to the output terminal 8, as shown in FIG. 8 (A), the output buffer circuit formed in the master step is provided with a plurality of output buffer circuits as shown in FIG. 8 (B) in the slicing step. Wire the buffers in parallel. With this wiring, the output impedance can be lowered and a high current can be set. Next, when a small load capacitance is added to the output terminal 8, as shown in FIG. 8A, the output buffer circuit formed in the master step is added to the output buffer circuit in the slicing step as shown in FIG. The output buffer is configured by wiring so that only one buffer is used. A low current can be set by this wiring.

[0007]

However, in the output buffer circuit configured as described above, the necessary load driving capability is adjusted in the slicing process which is a part of the manufacturing process. When using the integrated circuit of, the integrated circuit is manufactured separately, or the integrated circuit is manufactured for a system that requires a high load driving capability, and is also used for a system with a low load driving capability. It was In the former case, the unit price of the integrated circuit becomes high, and in the latter case, there is a problem that unnecessary current consumption is increased for a system having a low driving capability.

The present invention has been made to solve the above problems, and it is an object of the present invention to control the drive capability of an output buffer circuit from outside the integrated circuit.

[0009]

A semiconductor integrated circuit according to the present invention has a plurality of drivers each having an input terminal and an output terminal connected to each other and capable of controlling operation by a state control signal. The number of drivers to be operated is controlled according to the load connected.

[0010]

According to the present invention, the load driving capability of the output buffer and the input / output buffer can be set by the integrated circuit user according to the load capacitance.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, particularly showing an output dedicated output buffer circuit. In the figure, 9a to 9n are N drivers whose detailed circuit configurations are shown in FIG. 2, and each driver 9a to 9n is an input terminal 10, a control input terminal 11 to which a driver state control signal is input, and an output. The terminal 12 is provided. Reference numeral 13 denotes an n-bit register that holds state control signals 14a to 14n for controlling the operating states of the N drivers 9a to 9n, and 15 denotes N drivers 9a to 9n.
And n-bit register 13 and input terminal 1
6, an output buffer circuit including an output terminal 17.

In the drivers 9a-9n shown in FIG. 2, 18a and 18b are PMOS transistors, 1
Reference numerals 9a and 19b are NMOS transistors, 20a and 20b are transmission gates, and 21 is an inverter.

The operation of the drivers 9a-9n shown in FIG. 2 will be described. When the state control signals 14a-14n are "H", "H" is applied to the control input terminal 11 of the drivers 9a-9n.
Since the signal is input, both the PMOS transistor 18b and the NMOS transistor 19b are in the "off" state, and the transmission gates 20a and 20b are both in the "on" state. Therefore, both the PMOS transistor 18a and the NMOS transistor 19a are in the "off" state. Therefore, the signal input to the input terminal 10 is inverted and output from the output terminal 17.

When the state control signals 14a to 14n are "L", the control input terminal 11 of the drivers 9a to 9n.
Since the "L" signal is input to the
8b and NMOS transistor 19b are both "on"
The transmission gates 20a and 2
Both 0b are in the "off" state. Therefore, both the PMOS transistor 18a and the NMOS transistor 19a are in the "off" state, and the output terminal 17 is in the high impedance state.

Next, the operation of the output buffer circuit constituted by the N drivers 9a to 9n and the n-bit register 13 will be described. First, when a large load capacitance is added to the output terminal 17, when data "1" is set in all n bits of the register 13, the state control signals 14a to 14n become "H". Therefore, the "H" signal is input to each control input terminal 11 of the drivers 9a to 9n, so that the drivers 9a to 9n are in an operating state and can be set to a large drive capacity. Next, when a small load capacitance is added to the output terminal 17, when the data "1" is set to only one bit of the n bits of the register 13, the state control signal, for example, 14a becomes "H". Therefore, the "H" signal is input to the control input terminal 11 of the driver 9a and the "L" signal is input to the control input terminals 11 of the other drivers 9b to 9n.
Only activated and can be set to a small drive capacity.

As described above, by setting necessary data in the register 13 according to the load capacity, the drive capacity of the output buffer circuit can be changed. As a method of setting data in the register 13, setting by a program, setting from an external pin at reset, setting from an external pin in one operation, and the like can be considered.

FIG. 3 is a block diagram showing another embodiment of the semiconductor integrated circuit according to the present invention, and particularly shows an output buffer circuit dedicated to output. In the figure, 22a to 22n are state control signals 1 for controlling the operating states of the drivers 9a to 9n.
External pins 4a to 14n are directly input. The output buffer circuit with this configuration is different only in the setting method of the state control signals 14a to 14n in the output buffer circuit shown in FIG. 1, and the drive capability of the output buffer circuit can be set according to the load capacitance.

FIG. 4 is a block diagram showing still another embodiment of the semiconductor integrated circuit according to the present invention, particularly an output buffer circuit dedicated to output. In the figure, reference numeral 23 is an n-1 bit register for holding state control signals 14b to 14n for controlling the operating states of N-1 drivers 9b to 9n,
Reference numeral 24 is an inverter. In the output buffer circuit having this configuration, the output buffer circuit shown in FIG. 1 can control the operating states of all the N drivers 9a to 9n.
In the case of the embodiment shown in FIG. 4, the inverter 24 is provided as one driver 9a, and the remaining N-
One driver 9b to 9n can control the operating state.
Therefore, the number of driver operation control signals (lines) can be reduced by one.

FIG. 5 is a block diagram showing still another embodiment of the semiconductor integrated circuit according to the present invention, particularly an output buffer circuit dedicated to output. In the figure, 25b to 25n
Is an external pin to which the state control signals 14b to 14n for controlling the operating states of the N-1 drivers 9b to 9n are directly input. The output buffer circuit according to this configuration has state control signals 14a to 14n in the output buffer circuit shown in FIG.
However, it is needless to say that the drive capability of the output buffer circuit can be set in accordance with the load capacitance, except that the setting method is different.

FIG. 6 is a circuit diagram showing a driver used in the output circuit section of the input / output buffer circuit. In the figure, 26 is an inverter, 27 is a NOR circuit, and 28 is a control input terminal to which a state control signal for controlling the operating state of the input / output buffer circuit is input. In the driver having this configuration, the state control signal input to the control input terminal 28 is "L".
When the state control signal is "H", the state is the output state, and when the state control signal is "H", the state is the input state.

[0021]

As described in detail above, according to the semiconductor integrated circuit of the present invention, the output portions of the output buffer and the input / output buffer are connected to the input terminal and the output terminal, respectively, and the operation is controlled. Since a plurality of drivers that can be controlled by the control signal are configured, the integrated circuit user sets up to selectively operate any number of the plurality of drivers according to the load status of the system used. This makes it possible to set the optimum load driving capability with one integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a detailed circuit of the driver shown in FIG.

FIG. 3 is a block diagram showing another embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 4 is a block diagram showing still another embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 5 is a block diagram showing still another embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 6 is a circuit diagram showing another example of the driver shown in FIG.

FIG. 7 is a circuit diagram showing a conventional semiconductor integrated circuit.

FIG. 8 is a circuit diagram showing another conventional semiconductor integrated circuit.

[Explanation of symbols]

 9a-9n driver 10 input terminal 11 state control input terminal 12 output terminal 13 register 14a-14n state control signal 15 output buffer circuit 18a and 18b PMOS transistor 19a and 19b NMOS transistor 20a and 20b transmission gate 21 inverter 22a-22n external pin 23 Register 24 Inverter 25b-25n External pin 26 Inverter 27 NOR circuit 28 Control input terminal

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[Procedure amendment]

[Submission date] November 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

The operation of the drivers 9a-9n shown in FIG. 2 will be described. When the state control signals 14a-14n are "H", "H" is applied to the control input terminal 11 of the drivers 9a-9n.
Since the signal is input, PMOS transistor 18b and NMOS transistor 19b are both "off" state, ing to the transmission gates 20a and 20b are both "on" state. For this reason, the signal input to the input terminal 10 is inverted and output from the output terminal 17.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

FIG. 6 is a circuit diagram showing a driver used in the output circuit section of the input / output buffer circuit. In the figure, 26 is an inverter, 27 is a NAND circuit, and 28 is a control input terminal to which a state control signal for controlling the operating state of the input / output buffer circuit is input. In the driver having this configuration, when the state control signal input to the control input terminal 28 is "L", the impedance is high impedance (input buffer operation
It will work) state, when the state control signal is "H", the output
(Output buffer operation) state.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Explanation of Codes] 9a to 9n Driver 10 Input Terminal 11 State Control Input Terminal 12 Output Terminal 13 Register 14a to 14n State Control Signal 15 Output Buffer Circuit 18a and 18b PMOS Transistor 19a and 19b NMOS Transistor 20a and 20b Transmission Gate 21 Inverter 22a -22n external pin 23 register 24 inverter 25b-25n external pin 26 inverter 27 NAND circuit 28 control input terminal

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (1)

[Claims] 1. A plurality of drivers each having an input terminal, a control input terminal, and an output terminal, and a common input terminal and a common output terminal in which the input terminals and output terminals of the plurality of drivers are commonly connected. And a signal line for sending a state control signal for operating a number of drivers according to the magnitude of the load capacitance added to the common output terminal to the control input terminal, the semiconductor integrated circuit.