JPH05102400A - Semiconductor protective element - Google Patents

Abstract

PURPOSE:To realize a semiconductor holding element having a small breakover current and a large holding current. CONSTITUTION:A P-type third semiconductor region 3 is annularly formed on a surface side of a chip of an N-type first semiconductor region 1. N-type impurity is forcibly implanted in arbitrary one region of the two regions 3, 1 represented as annular outer and inner diameters on the surface of the chip of a P-N junction formed of the regions 1, 3 to form a fifth semiconductor region 5, and a contact is so provided as to have an ohmic contact with a first electrode 6 annularly with the surface of the region 3 near a residual region of two types.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor protection device,
More specifically, the present invention relates to a semiconductor protection element used to protect a wired communication device or the like from an abnormal voltage that enters through a communication cable.

[0002]

2. Description of the Related Art A plan view of a semiconductor chip of a conventional semiconductor protection device is shown in FIG. 9 is a sectional view taken along the line AA of FIG. 8, and FIG. 10 is a sectional view taken along the line BB of FIG. As shown in these figures, P forming a PN homojunction with the first semiconductor region 1 of N-type silicon having a required effective thickness and the entire surface on one side of both surfaces of the first semiconductor region 1. P-type second semiconductor region 2 and P formed by selectively introducing impurities into both surfaces of the first semiconductor region 1 on the side opposite to the side on which the PN junction is formed with the second semiconductor region 2. Type third semiconductor region 3
And an N-type fourth semiconductor region 4 formed by selectively introducing impurities into the third semiconductor region, and a substrate surface portion of a PN junction formed by the first semiconductor region 1 and the third semiconductor region 3. Of the fifth semiconductor region 5 formed by injecting an N-type impurity of an appropriate concentration over the entire region of, and both regions of the third semiconductor region 3 and the fourth semiconductor region 4 so as to have ohmic contact in an arbitrary shape. The first electrode 6 and the second electrode 7 provided in ohmic contact with the second semiconductor region 2, and when an abnormal voltage having a positive electrode on the second electrode 7 side is applied between the two electrodes, Among the PN junctions formed by the one semiconductor region 1 and the third semiconductor region 3, the fifth semiconductor region 5 portion into which an N-type impurity having an appropriate concentration is pressed has the lowest breakdown voltage, and thus is applied. If the abnormal voltage exceeds a certain value, the fifth semiconductor region 5 An avalanche phenomenon occurs, and a current flowing from the second electrode 7 through the second semiconductor region 2, the first semiconductor region 1, and the third semiconductor region 3 to the first electrode 6 begins to flow, and the semiconductor protection element is turned on by this current. I was getting into a state.

FIG. 11 shows a general voltage-current characteristic of this conventional semiconductor protection device.

[0004]

As shown in Figure 11 [0008], the holding current I _H is is the lowest of the current value required for the semiconductor protection element to hold the ON state, the holding current I _H Are generally important characteristic values in semiconductor protection devices.

That is, let us consider a case where a lightning surge is dropped on a communication line during a call in a semiconductor protection element for an exchange, for example. At this time, the semiconductor protection element is turned on by a lightning surge and an abnormal current flows to the ground. At the same time, the call current supplied from the exchange also flows to the ground via the semiconductor protection element. For this reason, even after all the abnormal current due to the lightning surge has finished flowing to the ground, the semiconductor protection element tries to keep the speech current flowing, and if the holding current I _H of the semiconductor protection element is smaller than this speech current, the semiconductor The protection element cannot return to the off state due to the telephone current. Therefore, the holding current I _H of the semiconductor protection element needs to be set larger than the call current.

Further, as shown in FIG. 11, the breakover current I _BO is the maximum current value required when the semiconductor protection element is in the on state from the off state, that is, the breakage current of the semiconductor protection element. It is considered that the smaller the value, the better the characteristics because the value indicates the ease of entering the ON state.

However, according to our experiments, the breakover current component that flows when the semiconductor protection device breaks down, and the holding current component that flows to the end when the current decreases in the on state are also found in the first semiconductor region. Of the PN junction formed by the first semiconductor region 1 and the third semiconductor region 3, the region formed in the vertical direction, that is, the boundary portion between the first semiconductor region 1 and the third semiconductor region 3 in the plan view of FIG. However, it is known that the electric field particularly flows to a portion having a curvature on the plan view.

Therefore, in the conventional device structure shown in FIGS. 8 to 10, both the breakover current component and the holding current component are as indicated by broken line arrows in the sectional views of FIGS. From the portion having a curvature on the plan view of the PN junction formed from the second electrode 7 through the second semiconductor region 2 and the first semiconductor region 1 to the first semiconductor region 1 and the third semiconductor region 3, the third semiconductor region 3 Flowing into the fourth semiconductor region 4
The lower third semiconductor region 3 is carried in the lateral direction, and flows in a path passing through the first electrode 6.

FIG. 12 is an equivalent circuit diagram of a conventional semiconductor protection device.

The PNP transistor 9 is constructed with the second semiconductor region 2, the first semiconductor region 1 and the third semiconductor region 3 as an emitter, a base and a collector, respectively. The NPN transistor 10 is configured with the fourth semiconductor region 4, the third semiconductor region 3 and the first semiconductor region 1 as an emitter, a base and a collector, respectively. The diode 11 is configured with the third semiconductor region 3 as an anode and the fifth semiconductor region 5 as a cathode. The resistance component R is the parasitic resistance of the third semiconductor region 3 along the aforementioned current path.

As is clear from this equivalent circuit, when the resistance component R is large, the breakover current I _BO has a small value, but the holding current I _H also becomes small, and conversely, when the resistance component R is small. The holding current I _H increases, but the breakover current I _BO also increases. There is a problem in that it is difficult to implement a semiconductor protection device having excellent characteristics because it is impossible to reduce the breakover current I _BO and increase the holding current I _H independently of each other.

[0012]

The semiconductor device of the present invention comprises:
An N (or P) -type first semiconductor region, a P (or N) -type second semiconductor region that is provided in contact with the back surface of the first semiconductor region, and an annular shape on the surface of the first semiconductor region. A P (or N) type third semiconductor region formed by introducing an impurity into the second semiconductor region, and an N (or P) type third semiconductor region formed by selectively introducing an impurity into a surface portion of the third semiconductor region. An impurity is selectively introduced into one of the four semiconductor regions, the inner peripheral portion or the outer peripheral portion of the annular third semiconductor region of the boundary portion between the first semiconductor region and the third semiconductor region, and the vicinity thereof. A formed N (or P) type fifth semiconductor region, and a first electrode that makes ohmic contact with portions of the fourth semiconductor region and the third semiconductor region where the fifth semiconductor region is not provided, Having a second electrode in ohmic contact with the second semiconductor region It is intended.

[0013]

The present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a device structure of a semiconductor holding element according to the first embodiment of the present invention, and FIG. 2 is A- of FIG.
A sectional view taken along line A and FIG. 3 are sectional views taken along line BB in FIG.

An N ^-- type first semiconductor region 1 of silicon or the like having a sufficient effective thickness (for example, 70 μm) to have a necessary breakdown voltage 1, a P ⁺ -type second semiconductor region 2, and a P-type formed in an annular shape. Of the third semiconductor region 3, a PNPN4 layer composed of an annular N ⁺ -type fourth semiconductor region 4 formed by selectively introducing impurities to the surface of the third semiconductor region, Due to the annular shape, the first semiconductor region 1
The surface portion of the substrate of the PN junction formed by the third semiconductor region 3 and the third semiconductor region 3 can be formed at two locations, the inner peripheral portion and the outer peripheral portion of the annular third semiconductor region 3. An N-type impurity having an appropriate concentration (for example, 6 × 10 ¹² cm ^-2 ) is introduced into the inner peripheral portion of these two locations,
A fifth semiconductor region 5 for controlling the reverse breakdown voltage of this PN junction is formed.

The region where the third semiconductor region 3 and the first electrode 6 are in ohmic contact is defined as an inner peripheral portion and an outer peripheral portion of the device surface portion of the PN junction region formed by the first semiconductor region 1 and the third semiconductor region 3. Of these, an annular shape is formed on the outer peripheral portion and its vicinity. FIG. 4 is an equivalent circuit diagram of this embodiment.

In this equivalent circuit, the base (first semiconductor region 1) and collector (third semiconductor region 3) of the PNP transistor 9 are the collector (first semiconductor region) and base (third semiconductor region 3) of the NPN transistor 10. The anode (third semiconductor region) and the cathode of the diode 11 each having a proper breakdown voltage are respectively connected to the collector and the base of the (fifth semiconductor region 5) PNP transistor 9 and the NPN transistor 10 is connected. A resistance component R _ON when in the _ON state and a resistance component R _OFF when returning to the OFF state are inserted between the base and the emitter.

In this embodiment, the current when the semiconductor protection element is in the ON state is curved on the plan view in which the electric field is likely to concentrate in the fifth semiconductor region 5, as shown by the broken line in FIG. Flows from the portion having the area to the area in ohmic contact with the first electrode 6 near the outside of the third semiconductor region 3, so that the distance of the current path is long and the resistance component R _ON becomes large.

When returning to the off state, as shown by the broken line in FIG. 3, of the outer diameter portion and the inner diameter portion of the device surface of the PN junction region formed by the first semiconductor region 1 and the third semiconductor region 3. From the portion having the curvature on the plan view of the outer diameter portion of the third semiconductor region 3 and the first electrode 6 formed near this portion.
Since a current path is formed in the region in which ohmic contact is made, the distance is short and the resistance component R _OFF is small.

For example, the chip size is 2.5 mm × 1.8.
The impurity concentration of phosphorus in the first semiconductor region 1 is about 4 × 1
0 ¹⁴ cm ⁻³ , the third semiconductor region 3 has a boron dose of 1
When the fourth semiconductor region 4 is formed to have a phosphorus impurity concentration of about 9 × 10 ¹⁵ cm ^-3 with an acceleration energy of 50 keV and an indentation time of 10 hours or more at × 10 ¹⁵ cm ^-2 , the breakover current I _{BO is} about 30 mA in the conventional structure. , Holding current I _H 25m
Although only a semiconductor protection element of about A was obtained, using the structure of the present invention, the breakover current I _BO can be maintained and the holding current I _H can be 100 mA or more.

FIG. 5 is a plan view of the device structure of the second embodiment of the present invention, FIG. 6 is a sectional view taken along the line AA of FIG. 5, and FIG.
FIG. 6 is a sectional view taken along line BB of FIG.

In the present embodiment, the planar shape of the outer peripheral portion of the third semiconductor region 3 formed in an annular shape is rectangular.

The mechanism when the semiconductor protection element is in the ON state is the same as that of the first embodiment, but when returning to the OFF state,
The electric field concentration becomes larger in the corner portion of the outer peripheral portion of the substrate surface of the PN junction formed by the first semiconductor region 1 and the third semiconductor region 3, and the current flowing along the current path at the time of OFF becomes larger, and thus the holding There is an advantage that the current is larger.

In the above description, it will be apparent that the present invention can be applied to the case where the conductivity type is reversed.

[0025]

As described above, according to the present invention, the third semiconductor region formed on the surface of the first semiconductor region and the fourth semiconductor region formed on the third semiconductor region are formed into an annular shape, and the fifth semiconductor is formed. The resistance component R _ON at the time of _ON is large, and the resistance component R _OFF at the time of _OFF is small by selectively providing the region and the region where the third semiconductor region and the first electrode are in ohmic contact with each other with the fourth semiconductor region interposed therebetween. Therefore, the breakover current I _BO is small and the holding current I _H
Has the effect that a large semiconductor protection device can be realized.

[Brief description of drawings]

FIG. 1 is a partially fragmented plan view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG.

FIG. 4 is an equivalent circuit diagram of the first embodiment.

FIG. 5 is a partially crushed plan view of a semiconductor chip showing a second embodiment.

6 is a cross-sectional view taken along the line AA of FIG.

7 is a cross-sectional view taken along the line BB of FIG.

FIG. 8 is a partially crushed plan view of a semiconductor chip showing a conventional example.

9 is a cross-sectional view taken along the line AA of FIG.

10 is a sectional view taken along line BB of FIG.

FIG. 11 is a voltage-current characteristic diagram of the semiconductor protection element.

FIG. 12 is an equivalent circuit diagram of a conventional example.

[Explanation of symbols]

1 1st semiconductor region 2 2nd semiconductor region 3 3rd semiconductor region 4 4th semiconductor region 5 5th semiconductor region 6 1st electrode 7 2nd electrode 8 insulating film 9 PNP transistor 10 NPN transistor 11 diode R resistance component R _ON ON Resistance component when entering state R _OFF Resistance component when returning to off state

Claims (2)

[Claims] 1. An N (or P) -type first semiconductor region, a P (or N) -type second semiconductor region provided on a back surface of the first semiconductor region, and the first semiconductor region. Of the P (or N) type third semiconductor region formed by introducing impurities into the surface of the third semiconductor region and N (or N) formed by selectively introducing impurities into the surface of the third semiconductor region. P) type fourth semiconductor region, and either the inner peripheral portion or the outer peripheral portion of the annular third semiconductor region of the boundary portion between the first semiconductor region and the third semiconductor region and the vicinity thereof are selectively formed. An ohmic contact is made between the N (or P) type fifth semiconductor region formed by introducing impurities and the portions of the fourth semiconductor region and the third semiconductor region where the fifth semiconductor region is not provided. A first electrode and a second electrode in ohmic contact with the second semiconductor region A semiconductor protection device comprising: 2. The semiconductor protection device according to claim 1, wherein the first semiconductor region to the fifth semiconductor region are made of silicon as a base material.