JPH05102399A - Bus connecting system - Google Patents

Abstract

PURPOSE:To prevent an erroneous operation in an internal circuit by reducing deterioration of signal transmitting characteristic due to a parasitic resistance and a parasitic capacity of a bus line in a semiconductor integrated circuit. CONSTITUTION:Functional blocks 1, 2, 3 and 4, and bus lines 201, 202, 203 and 204 for coupling input/output buffers 5, 6, 7 and 8 corresponding to the buffers 5, 6, 7 and 8 of the blocks 1, 2, 3 and 4 are laid in a bus connecting system. N-channel MOS transistors 9, 10, 11 and 12 which are operated as functions of switch circuits are inserted to be connected to the bus lines corresponding to the connecting points O of the bus lines. Corresponding parasitic resistances 13-20 and parasitic capacities 20-24 are interposed to the respective bus lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connection system, and more particularly to a bus connection system used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art An example of a conventional bus connection system of this type is shown in FIG. As shown in FIG. 3, in the semiconductor integrated circuit, the function blocks 38, 39, 40 and 4 are provided.
1 and the input / output buffers 42, 43, 44 and 45 attached to each of these functional blocks, the bus lines 205, 20 for connecting the input / output buffers to each other.
6, 207 and 208 are laid. In FIG. 3, the circuit elements represented as resistance and capacitance are
The parasitic resistance (46
˜61) and parasitic capacitance (62-69).

In such a bus connection system, for example, when a signal is transmitted from the function block 38 to the function block 40, the bus lines 205 and 207 and the bus lines laid in an annular shape are present together. All of the parasitic resistance and parasitic capacitance that are involved in the transmission of the signal concerned result in transmission of the transmitted signal including waveform distortion, phase delay distortion, level reduction, noise addition, etc. It becomes a factor that deteriorates the characteristics.

[0004]

In the above-described conventional bus connection system, the bus lines laid between the respective functional blocks are laid out as the semiconductor integrated circuit becomes multifunctional and the chip area tends to increase. The length tends to increase, and the number of input / output gates connected to the bus line has also increased significantly. For this reason, the signal transmission characteristics between the functional blocks are deteriorated due to the parasitic capacitance and parasitic resistance of the bus line itself, the load capacitance and parasitic resistance of the input / output gate itself, and the cause of malfunction of the internal circuit of the semiconductor integrated circuit. There is a drawback that

[0005]

According to the bus connection system of the present invention, functional blocks in a semiconductor integrated circuit are connected to each other through an input / output buffer and a bus line. Corresponding bus lines are laid so as to be commonly connected at a predetermined connection point O, and at a position close to the connection point O, each bus line is used for signal transmission. It is characterized in that the switch means controlled to be closed only in the state is inserted and connected.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, in the semiconductor integrated circuit, the function blocks 1, 2, 3 and 4 are used.
And bus lines 201, 202, 203 and 204 are provided to connect the input / output buffers 5, 6, 7 and 8 to the respective functional blocks, in order to connect the input / output buffers to each other. Corresponding to the connection point O of these bus lines, N-channel MOS transistors 9 and 10 functioning as switch circuits are provided in each bus line.
11 and 12 are inserted and connected. Further, in FIG. 1, the circuit elements shown as resistance and capacitance are the parasitic resistances (13 to 20) and parasitic capacitances (2 to 20) associated with these bus lines, as in the case of the above-mentioned conventional example.
1 to 24) are shown. As is apparent from FIG. 1, the difference from the conventional example of the present invention is that each bus line 201, 20
2, 203 and 204 are commonly connected at the connection point O, and corresponding to the connection point O, the bus lines 201, 2
02, 203 and 204 respectively have N channels M
That is, the OS transistors 9, 10, 11 and 12 are inserted and connected. The N-channel MOS transistor functioning as a switch circuit is a P-channel MO transistor.
It is also possible to substitute and use an S transistor.

Further, FIG. 2A is a circuit diagram showing an embodiment common to the input / output buffers 5, 6, 7 and 8, and as shown in FIG. , NAN
D circuit 25 and inverters 26, 32, 36 and 37
A NOR circuit 27, P channel MOS transistors 28, 31 and 33, N channel MOS transistors 29, 34 and 35, and an EXOR circuit 30. 2 (b), (c) and (d)
2A, the bus input signal IN, the bus opening / closing signal BO and the bus output signal IO are respectively shown in FIG.
It is a figure which shows the truth table which makes output, and what is shown as z has shown the state of high impedance. In the initial state, these input / output buffers 5,
In 6, 7, and 8, the read signal RD and the write signal WR are both set to "0" level.

In FIG. 1, for example, when a signal is transmitted from the functional block 1 to the functional block 4, the write signal WR is at "0" level in the input / output buffers 5 and 8 (see FIG. 2A). The read signal RD is transferred from "0" to "1" while being held at. In response to this,
The bus open / close signal BO is also transited from “0” to “1” and output as open / close signals 101 (input / output buffer 5) and 104 (input / output buffer 8) of “1” level, respectively, and as a switch circuit in FIG. Functioning N-channel MO
It is input to the gates of the S transistors 9 and 12, respectively. As a result, the N-channel MOS transistor 9
Both and 12 are conductive, and the bus lines 201 and 204 are connected. On the other hand, since the input / output buffers 6 and 7 are still in the initial state and the read signal RD and the write signal WR are both set to "0" level, the corresponding N channel M
OS transistors 10 and 11 are held in the non-conducting state.

Therefore, the function block 1 and the function block 4
A transmission bus line for transmitting a signal between and is formed by only the bus lines 201 and 204,
Unnecessary bus lines 202 and 203 have been completely eliminated. As a result, the bus lines 202 and 203
The extra parasitic resistance, parasitic capacitance, and the like that are present in the transmission line are not excluded from the transmission bus line, and the transmission characteristics of the bus line are not deteriorated. Also, connection point O
It is expected that the parasitic resistance and the parasitic capacitance will be further reduced by increasing the number of a series of bus line systems including an N-channel MOS transistor as a switch circuit, an input / output buffer, a functional block, etc. connected to the.

[0011]

As described above, according to the present invention, by inserting and connecting a MOS transistor, which is set in a conductive state at the time of signal transmission, on the bus line corresponding to each functional block, a parasitic transistor existing in the bus line is inserted. The resistance and the parasitic capacitance are reduced, the signal transmission characteristics between the functional blocks are improved, and the malfunction of the internal circuit of the semiconductor integrated circuit can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of an input / output buffer in this embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

1-4, 38-41 Functional block 5-8, 42-45 Input / output buffer 9-12, 29, 34, 35 N-channel MOS transistor 13-20, 46-61 Parasitic resistance 21-24, 62-69 Parasitic capacitance 25 NAND circuit 26, 32, 36, 37 Inverter 27 NOR circuit 28, 31, 33 P-channel MOS transistor 30 EXOR circuit

Claims (1)

[Claims] 1. In a bus connection method for connecting functional blocks in a semiconductor integrated circuit to each other via an input / output buffer and a bus line, a bus line provided corresponding to each functional block has a predetermined connection. Laid so that they are commonly connected at point O,
At a position close to the connection point O, a switch means controlled to be closed is inserted and connected to each bus line only when the bus line is used for signal transmission. Connection method.