JPH0499977A - Semiconductor integrated circuit apparatus - Google Patents

Abstract

PURPOSE:To set various functional blocks on one chip and to reduce the number of test terminals by using one of a plurality of terminals as a test terminal and setting one test mode on the basis of the level of the signal applied to the test terminal. CONSTITUTION:For example, a system-ON chip 12 is mounted on the package 11 of a package LSI 10 and one pin 13 among the input/output pins 13 - 15 outside the package 11 is used as a test pin. A test mode change-over signal VIV for changing over the LSI 10 to a test mode and an actual operation mode is inputted to the pin 13. A test mode setting circuit 20 sets any one of various test modes prepared on the basis of the voltage value of the signal VIN with respect to a CPU 16, an ROM 17, an RAM 18 or a logical cell array 19 being functional block circuits. A test mode selecting circuit 21 connects the set functional block circuits to the predetermined pins 14, 15 on the basis of the set result to conduct a test.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor integrated circuit device, and more specifically relates to a setting function for setting one of various test modes provided. The purpose is to be able to set multiple test modes with a single test terminal and to improve cost performance by reducing the number of test terminals.It is configured with a functional block circuit group consisting of various functional block circuits and multiple terminals. In a semiconductor integrated circuit device in which various test modes are prepared for the functional block circuits of the functional block circuit group, one terminal among the plurality of terminals is used to set the semiconductor integrated circuit device between the test mode and the actual operation mode. A test mode setting circuit is provided, which serves as a test terminal for switching between the test terminals and the test terminal, and sets any one of a plurality of test modes based on the signal level applied to the test terminal.

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device, and specifically relates to a setting function for setting any one of various test modes provided.

As semiconductor integrated circuit devices (hereinafter referred to as LSIs) have become highly integrated in recent years, the various functional block circuits that make up internal circuits have also become more complex, and the amount of test patterns needed to reliably discover failures has become enormous. Put it away. Therefore, when testing an LSI, there is a tendency to operate a test-dedicated circuit and test various functional block circuits using a route different from the route used in actual operation of the LSI. When performing such a test, the number of test modes increases as the number of functional block circuits forming the internal circuit increases.

Therefore, the number of test terminals for switching the LSI between the test mode and the actual operation mode increases, but in order to reduce costs, it is necessary to reduce the number of test terminals.

[Prior Art] In a conventional semiconductor integrated circuit device, if only one test mode is prepared, only one test terminal is required, since only one test mode and an actual operation can be switched.

However, when the number of functional block circuits forming the internal circuits of an LSI increases and a plurality of test modes become necessary, the number of test terminals increases.

That is, for example, in an LSI (system-on-chip) in which various functional block circuits are formed on one chip, when the number of test modes increases to two or four, one of the test pads provided near the outer periphery of the chip The number of test pads is increased by two or three, and one of various test modes is set by combining the signals of these test pads. Also, an LSI in which one chip or multiple chips are mounted in a package (hereinafter referred to as a package LSI)
), the number of test pins is increased to two or three out of the multiple pins provided outside the package depending on the number of test bats, and one of various test modes is selected by combining the signals of those test pins. I was supposed to set one.

[Problems to be Solved by the Invention] However, in a system-on-chip, the number of pads formed near the outer periphery of the chip is determined depending on the chip size, and if the number of test pads is increased as the number of test modes increases, The number of pads that can be used for actual operation of the LSI decreases. Therefore, the number of functions that can be installed on the chip is smaller than the maximum function that can be installed when the number of test bats is one. That is, an increase in the number of test bats in a system-on-chip has the problem of lowering the ratio of mountable functions to the chip size and lowering cost performance.

Furthermore, in a package LSI, when the number of test pins is increased, the number of pins that can be used for actual operation of the LSI decreases. For this reason, the chip that can be mounted in that package (
The number of mounted functions (one or more) is smaller than the number of chip mounted functions that can be mounted when the number of test pins is one. That is, an increase in the number of test pins in a package LSI reduces the ratio of mountable functions to the package size, resulting in a decrease in cost performance.

The present invention has been made to solve the above problems, and when testing a semiconductor integrated circuit device, it is possible to set a plurality of test modes with one test terminal, and the cost performance is improved by reducing the number of test terminals. The aim is to be able to improve.

Another object of the present invention is to increase the number of test modes by subdividing the threshold value in the level determining circuit and increasing the number of level determining circuits.

[Means to solve the problem] FIG. 1 shows a diagram explaining the principle of the present invention.

The functional block circuit group 1 is made up of various functional block circuits, and various test modes are prepared for the functional block circuits of the functional block circuit group 1.

The test terminal 3 is one of the plurality of terminals 2, and is used to switch the semiconductor integrated circuit device between a test mode and an actual operation mode. Test mode setting circuit 4
sets one of a plurality of test modes based on the signal level applied to the test terminal 3.

Further, in the second aspect of the invention, the test mode setting circuit includes a plurality of level determination circuits each having a different threshold value and outputting an output signal that is higher or lower than the signal level applied to the test terminal. and a test mode specifying section that outputs a signal specifying any one of the plurality of test modes prepared based on the output signals of the plurality of level determination circuits.

[Operation] According to the present invention, one of the various test modes prepared by the test mode setting circuit 4 is set based on the signal level applied to the test terminal 3.

Therefore, for example, in the case of a system-on-chip, all but one test pad among the multiple pads provided near the outer periphery of the chip can be used for actual operation, so the functions that can be mounted for the chip size can be used for actual operation. ratio will increase and cost performance will improve.

In addition, for example, in the case of a package LSI, all pins other than one test pin among the multiple pins provided outside the package can be used for actual operation. The ratio will increase and cost performance will improve.

Furthermore, the number of test modes can be increased by increasing the number of level determination circuits by subdividing the threshold values in the level determination circuits.

[Embodiment] An embodiment in which the present invention is embodied in a package LSI will be described below with reference to FIGS. 2 to 6.

FIG. 2 shows the package LSI10, and the package 11
A system-on-chip 12 is mounted inside. On the outside of the package 11, there is one test pin 13 as a test terminal and a plurality of input/output pins 14 and 15 as terminals.
and is provided.

A test mode switching signal VIN for switching the package LSI10 between a test mode and an actual operation mode is input to the test pin 13.

The system-on-chip 12 includes various functional block circuits formed on one chip, that is, a CPU (central processing unit).
16. It includes a ROM (read only memory) 17, a RAM (random access memory) 18, a logic cell array 19, and the like, as well as a test mode setting circuit 20 and a test mode selection circuit 21.

The test mode setting circuit 20 receives the test mode 1 switching signal VIN from the test pin 13 via wiring (not shown), and based on the voltage value of the test mode switching signal VIN, the CPU 16. ROM17, RAMI 8.
One of the various test modes prepared for the logic cell array 19 and the like is set. The test mode selection circuit 21 selects the CPUI 6. based on the setting result of the test mode setting circuit 20. ROMI 7. RAMI
8. Any one of the functional procuring circuits, such as the logic cell array 19, is connected between a predetermined input pin 14 and output pin 15 to perform a test.

Next, the test mode setting circuit 20 will be explained.

As shown in FIG. 3, the test mode setting circuit 20 includes a mode switching section 30 and a test mode specifying section 31. The mode switching unit 30 includes n inverter circuits 30 connected to the test pin 13 as a level determination circuit.
A1-30An and all inverter circuits 30A1-3
NAND (
NAND) circuit 30B.

As shown in FIG. 4, each of the inverter circuits 30A1-
30An is a p connected in series between the power supply VDD and GND.
It is composed of MO8 and nMOS transistors 32 and 33. pMO of each inverter circuit 30A1 to 30An
The channel lengths of the 8l-transistors 32 are formed to be equal to each other, and the channel lengths of the nMOS transistors 33 are formed to increase sequentially, that is, each inverter circuit 3
0Ai (i=L 2. . . . , n) is the threshold value,
That is, the output inversion voltage VTi (i=1.2....*,
n) are formed differently. Each output inversion voltage VTi is pMO8 and nMOs transistor 32
．． Letting a be the coefficient determined by the process accuracy of 33, it is determined by the following formula.

VTi= VDDX aX i < VDD Therefore,
Each inverter circuit 30A1 to 30An outputs an output signal TSI to TSn of logical value "H" when the test mode switching signal VIN is less than its output inverted voltage VTi, and when the test mode switching signal VIN is higher than its output inverted voltage VTi. Output signals TSI to TSn of logical values rL, , + are output. FIG. 5 explains the operation of each inverter circuit 30A1 to 30An. For example, the test mode switching signal VIN satisfies VDDXa≦V IN<VDDX 2 a
In this case, only the output signal TSI has the logical value rLJ, and the output signals TS2 to TSn have the logical value rHJ.

Then, when any one of the output signals TS1 to TSn of all the inverter circuits 30A1 to 30An reaches a logical value rLJ, the NAND circuit 30B sends a mode switching signal T of logical value "H" to the test mode selection circuit 21. output, and switches this package LSI10 to test mode. Further, when the output signals TSI to TSn of all the inverter circuits 30A1 to 30An reach the logic value "H", the NAND circuit 30B outputs the mode switching signal T of the logic value "L" to the test mode selection circuit 21, and this Switch the package LS110 to actual operation mode.

The test mode specifying section 31 is composed of n exclusive OR (ExOR) circuits 31A1 to 31An. Each ExOR circuit 31AI to 31An-1 is an output signal TSI to each inverter circuit 30A1 to 30An-1.
TSrr-1 as one input, and output signals TS2 to TSn of each ink output circuit 30A2 to 30An.
is used as the other input. Further, the ExOR circuit 31An receives the output signal TSn of the inverter circuit 30An as one input, and uses the power supply VDD as the other input.

Each of the ExOR circuits 31A1 to 31An outputs mode designation signals T1 to Tn to the test mode selection circuit 21 based on both input signals. That is, each Ex
The OR circuits 31A1 to 31An output a signal with a logical value rL when the logical values of both input signals are equal, and output a signal with a logical value rHJ when the logical values of both signals are different. FIG. 6 explains the operation of the test mode setting circuit 20, for example, the output signal TS of the inverter circuit 30A1.
Only l has the logical value "L", and the inverter circuits 30A2-3
When the output signals TS2 to TSn of 0An have a logic value "H", only the mode designation signal Tl has a logic value "H", and the test mode selection circuit 21 selects one functional block circuit corresponding to this mode designation signal TI. is selected and the test is executed.

In this way, in the package LS110 of this embodiment, only one of the plurality of pins provided outside the package 11 is used as the test pin 13, and all other pins 14 and 15 are used for actual operation. I try to do that.

Therefore, the system-on-chip 12 having the maximum functionality that can be implemented for the size of the package 11 is mounted on the package 11. That is, the ratio of mountable functions to the package size can be increased, and cost performance can be improved.

Further, by subdividing the threshold value (output determination voltage) in each inverter circuit that constitutes the mode switching unit 30, the number of inverter circuits can be increased, and thereby the number of test motes can be increased. .

In the present embodiment, the mode switching section 30 is composed of n inverter circuits 30A1 to 30An and a NAND circuit 30B, but as shown in FIG. 30C1 to 30Cn and an OR circuit 30D that receives output signals TSI to TSn of all the comparators 30C1 to 30Cn as inputs.

In this case, the reference voltages Vrefl to V refn applied to each of the comparators 30C1 to 30Cn may be set equal to each of the output inversion voltages VTI to VTn.

Further, in this embodiment, the mode switching unit 30 is configured with n inverter circuits and a NAND circuit, but the inverter circuit may be replaced with a buffer circuit, and the NAND circuit may be replaced with an OR circuit.

Further, in this embodiment, the test mode specifying section 31 is
Although it is configured with an OR circuit, the test mote designation section 31 is
Consisting of a D converter and a decoder circuit, the analog test mode switching signal VIN is converted to a digital value by an A/D converter, and the conversion result is decoded by the decoder circuit to output mode designation signals T1 to Tn. You can do it like this.

Further, in this embodiment, the test mode setting by the test mode setting circuit 20 is performed based on the voltage value of the test mode switching signal VIN, but the test mode setting may be performed based on the current value. .

Further, in this embodiment, the present invention is implemented in a package LSI 1.0 in which the system-on-chip 12 is mounted, but it may be implemented in a package LSI in which a plurality of chips are mounted.

Furthermore, although this was applied to a packaged LSI in this embodiment, in the system-on-chip 12 as well, only one pad is used as a test pad among the plurality of pads provided near the outer periphery of the chip, and all other pads are used as test pads. By configuring it to be used for operation, it is possible to increase the ratio of functions that can be mounted to the chip size.
Cost performance can be improved.

[Effects of the Invention] As detailed above, according to the present invention, when testing a semiconductor integrated circuit device, multiple test modes can be set with one test terminal, and cost performance is improved by reducing the number of test terminals. There are excellent effects that can be achieved.

Furthermore, the number of test modes can be increased by increasing the number of level determination circuits by subdividing the threshold values in the level determination circuits.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block circuit diagram showing the configuration of an embodiment, Fig. 3 is a logic circuit diagram showing an example of a test mode setting circuit, and Fig. 4 shows an inverter circuit. FIG. 5 is a diagram explaining the operation of each inverter circuit, FIG. 6 is a diagram explaining the operation of the test mode setting circuit, and FIG. 7 is a logic circuit diagram showing the separate test mode setting circuit. In the figure, 1 is a functional block circuit group, 2 is a terminal, 3 is a test terminal, and 4 is a test mode setting circuit.

Claims (1)

[Claims] 1. Regarding the functional block circuit of the functional block circuit group (1), which is configured to include a functional block circuit group (1) consisting of various functional block circuits and a plurality of terminals (2). In a semiconductor integrated circuit device provided with various test modes, one terminal among the plurality of terminals (2) is a test terminal (3) for switching the semiconductor integrated circuit device between a test mode and an actual operation mode. At the same time, one of the plurality of test modes is selected based on the signal level applied to the test terminal (3).
Test mode setting circuit (4
) A semiconductor integrated circuit device. 2. The test mode setting circuit (4) has a plurality of level judgments each having a different threshold value and outputting an output signal that is higher or lower than the signal level applied to the test terminal (3). A mode switching unit (30) equipped with circuits (30A1 to 30An) and a plurality of level determination circuits (30A1
2. The test mode designating section (31) outputs a signal designating any one of the plurality of test modes prepared based on the output signal of the test mode (30An). Semiconductor integrated circuit device.