JPH0497607A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0497607A JPH0497607A JP21557290A JP21557290A JPH0497607A JP H0497607 A JPH0497607 A JP H0497607A JP 21557290 A JP21557290 A JP 21557290A JP 21557290 A JP21557290 A JP 21557290A JP H0497607 A JPH0497607 A JP H0497607A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- capacitance
- switching
- ground
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000003990 capacitor Substances 0.000 claims abstract description 21
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特にエミッタ接地方式
の増幅器に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a grounded emitter type amplifier.
従来、この種の増幅器は第3図及び第4図に示すように
、増幅用として使用しているトランジスタT r 1の
エミッタとグランドの間に帰還抵抗R2を挿入している
が、特に利得の周波数特性を広帯域化させる場合、利得
が低下していく高周波帯域で帰還抵抗の値を見かけ上小
さくする為、第3図に示すように、チップの内部や、第
4図に示すように外部に抵抗R2と並列に容tc+又は
C2を接続していた。Conventionally, in this type of amplifier, a feedback resistor R2 is inserted between the emitter of the transistor T r 1 used for amplification and the ground, as shown in FIGS. 3 and 4. When widening the frequency characteristic, in order to make the value of the feedback resistor appear smaller in the high frequency band where the gain decreases, it is necessary to install it inside the chip as shown in Figure 3 or externally as shown in Figure 4. A capacitor tc+ or C2 was connected in parallel with the resistor R2.
上述した従来の増幅回路は以下の問題点を有する。すな
わち、内部に容量を作り込む場合に、容量の作り込み段
階で容量値が決定されている為、値を修正するには再び
作り直す必要がある。又、作製上のバラツキを保証する
のが困難である。The conventional amplifier circuit described above has the following problems. That is, when building a capacitor internally, since the capacitance value is determined at the stage of building the capacitor, it is necessary to recreate it to correct the value. Furthermore, it is difficult to guarantee manufacturing variations.
一方、外部に容量を接続する場合、外部に容量を接続す
る為、容量値は可変であるが、ポンディングパッド−パ
ッケージビン間のボンディングワイヤーのインダクタン
スが直列に接続されることとなる為、特にIGHz以上
の高周波数帯域で、その影響は無視できなくなる。On the other hand, when connecting a capacitor externally, the capacitance value is variable because the capacitor is connected externally, but the inductance of the bonding wire between the bonding pad and the package bin is connected in series, so In high frequency bands above IGHz, its influence cannot be ignored.
本発明の目的は、利得等の動作モードが選択可能で、し
かも高周波に対する特性が保証することができる半導体
集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit in which operating modes such as gain can be selected and characteristics at high frequencies can be guaranteed.
本発明の半導体集積回路は、エミッタが帰還抵抗を介し
て電源に接続されたトランジスタと、前記トランジスタ
のエミッタと前記電源間に設けられた容量と、前記容量
の前記電源との導通を制御する制御手段とを有すること
を特徴とする。The semiconductor integrated circuit of the present invention includes a transistor whose emitter is connected to a power source via a feedback resistor, a capacitor provided between the emitter of the transistor and the power source, and a control device that controls conduction between the capacitor and the power source. It is characterized by having a means.
第1図は本発明の第1の実施例を示すエミッタ接地増幅
回路である。Trlはエミッタ接地トランジスタで、R
1は負荷抵抗、R2は帰還抵抗である。Cは帰還抵抗R
2と並列に接続された容量で、この容量Cがグランドに
接続されるか否かを、定電流源Iとスイッチングトラン
ジスタTr2により選択できる。FIG. 1 shows a common emitter amplifier circuit showing a first embodiment of the present invention. Trl is a common emitter transistor, R
1 is a load resistance, and R2 is a feedback resistance. C is feedback resistance R
Whether or not this capacitor C is connected to the ground can be selected by the constant current source I and the switching transistor Tr2.
容量Cをグランドに接続する場合、SWに例えばIVの
弱の電圧を印加する。これによりスイッチングトランジ
スタTr2がオン状態となり、コレクターエミッタ間の
抵抗が下がることになる。When connecting the capacitor C to the ground, a weak voltage of IV, for example, is applied to SW. This turns on the switching transistor Tr2, and the collector-emitter resistance decreases.
又、容量Cを開放にする場合、SWを開放にすればスイ
ッチングトランジスタTr2は非動作となり、T r
2のコレクタ端子側のグランドとの間のインピーダンス
は高くなる。Furthermore, when the capacitor C is opened, the switching transistor Tr2 becomes inoperable if SW is opened, and the switching transistor Tr2 becomes inoperable.
The impedance between the collector terminal side of No. 2 and the ground becomes high.
以上の構成により、SWの電圧に応じて、容量Cの容量
値を可変することが可能となる。With the above configuration, it is possible to vary the capacitance value of the capacitor C according to the voltage of SW.
第2図は本発明の第2の実施例を示す回路図である。同
図に示すように、Trlはエミッタ接地増幅器として動
作するトランジスタで、R1は負荷抵抗、R2は帰還抵
抗である。容量C1゜C2,C3は各々II、Tri−
I2 Tr2−I3.Tr3により帰還抵抗R2と並
列に接続されるか否かが制御される。FIG. 2 is a circuit diagram showing a second embodiment of the present invention. As shown in the figure, Trl is a transistor that operates as a common emitter amplifier, R1 is a load resistance, and R2 is a feedback resistance. The capacitances C1゜C2 and C3 are II and Tri-, respectively.
I2 Tr2-I3. Whether Tr3 is connected in parallel with feedback resistor R2 is controlled.
ここで例えば容量C1を1pF、容量C2を2pF、容
量C3を4pFと設定すると、以下のような容量の組み
合せが可能となる。For example, if the capacitor C1 is set to 1 pF, the capacitor C2 is set to 2 pF, and the capacitor C3 is set to 4 pF, the following capacitor combinations are possible.
SWI 、 SW2 、 SW3がオフの時・・・容量
=OpFSWIのみオンの時 ・・・容量=1pF
SW2のみオンの時 ・・・容量=2pFSW3の
みオンの時 ・・・容量=3pFSWI、SW2が
オンノ時 ・・・容量=4pFSWI 、SW3がオ
ンの時 ・・・容量=5pFSW2 、 SW3がオ
ンの時 ・・・容量=6pFSWI 、SW2.SW
3がオンの時・・・容量=7pF〔発明の詳細な
説明したように、本発明は、定電流源を含有するスイッ
チング回路と接続された内部容量を持つ為、チップ内部
に容量がありながら、スイッチングにより接続するか否
かが外部から操作でき、容量値が可変できる。When SWI, SW2, SW3 are off... Capacity = Op When only SWI is on... Capacity = 1pF
When only SW2 is on... Capacity = 2 pFS When only SW3 is on... Capacity = 3 pFSWI, when SW2 is on... Capacity = 4 pFSWI, when SW3 is on... Capacity = 5 pFSWI, when SW3 is on ...Capacity=6pFSWI, SW2. SW
3 is on...capacitance = 7pF [As explained in detail, the present invention has an internal capacitance connected to a switching circuit containing a constant current source, so even though there is a capacitance inside the chip, , connection or not can be controlled externally by switching, and the capacitance value can be varied.
しかも外部に帰還路を引き出していないので、ボンディ
ングワイヤーのインダクタンスの影響が無視でき、特に
高周波の増幅器において特性の保証ができるだけでなく
、利得等の動作モードの選択可能な増幅器を構成するこ
とが可能となる。Moreover, since no feedback path is drawn out to the outside, the influence of the inductance of the bonding wire can be ignored, which not only guarantees the characteristics especially in high-frequency amplifiers, but also allows the configuration of amplifiers with selectable operating modes such as gain. becomes.
回路図である。It is a circuit diagram.
R1・・・負荷抵抗、R2・・・帰還抵抗、Trl・・
・増幅用トランジスタ、Tr2・・・スイッチング用ト
ランジスタ、■・・・定電流源、C・・・容量、C1・
・・容量、C2・・・外部容量、Ll・・・ボンディン
グワイヤーインダクタンス、SW・・・スイッチ端子、
Vcc・・・電源、IN、OUT・・・信号入力・出力
。R1...Load resistance, R2...Feedback resistance, Trl...
・Amplification transistor, Tr2... Switching transistor, ■... Constant current source, C... Capacity, C1...
...Capacitance, C2...External capacitance, Ll...Bonding wire inductance, SW...Switch terminal,
Vcc...power supply, IN, OUT...signal input/output.
Claims (1)
スタと、前記トランジスタのエミッタと前記電源間に設
けられた容量と、前記容量の前記電源との導通を制御す
る制御手段とを有することを特徴とする半導体集積回路
。A transistor having an emitter connected to a power source via a feedback resistor, a capacitor provided between the emitter of the transistor and the power source, and a control means for controlling conduction of the capacitor with the power source. semiconductor integrated circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21557290A JPH0497607A (en) | 1990-08-15 | 1990-08-15 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21557290A JPH0497607A (en) | 1990-08-15 | 1990-08-15 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0497607A true JPH0497607A (en) | 1992-03-30 |
Family
ID=16674655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21557290A Pending JPH0497607A (en) | 1990-08-15 | 1990-08-15 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0497607A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8807881B2 (en) | 2008-08-29 | 2014-08-19 | Osg Corporation | Throwaway rotary cutting tool |
-
1990
- 1990-08-15 JP JP21557290A patent/JPH0497607A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8807881B2 (en) | 2008-08-29 | 2014-08-19 | Osg Corporation | Throwaway rotary cutting tool |
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