JPH0497534A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0497534A
JPH0497534A JP21505290A JP21505290A JPH0497534A JP H0497534 A JPH0497534 A JP H0497534A JP 21505290 A JP21505290 A JP 21505290A JP 21505290 A JP21505290 A JP 21505290A JP H0497534 A JPH0497534 A JP H0497534A
Authority
JP
Japan
Prior art keywords
film
polysilicon film
layer
oxide film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21505290A
Other languages
Japanese (ja)
Inventor
Kimiharu Uga
宇賀 公治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21505290A priority Critical patent/JPH0497534A/en
Publication of JPH0497534A publication Critical patent/JPH0497534A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent damage to a silicon substrate caused by etching by etching a first polysilicon film on an emitter layer in such a way that it is left somewhat without removing it completely and by implanting impurities for the base layer via an oxide film. CONSTITUTION:When a second oxide film 111 and a first polysilicon film 100 are etched with a first resist film 700 as a mask. the first polysilicon film 100 is left somewhat without removing it completely. The first polysilicon film which is left is denoted by reference numeral 100A. Next. the left film 100A is oxidized completely and an oxide film 100B is formed. A P-type impurity is implanted into an epitaxial layer 3 under the film 100B in an active region of a transistor via the film 100B. and an intrinsic base layer 7 is formed. As this prevents damage to a silicon substrate caused by etching, leak current of a transistor can be reduced and transistor characteristics can be improved. In addition, the performance of transistors can be increased because thin junction is formed.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は、半導体装置の製造方法に関し、特に高性能
のバイポーラトランジスタの製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a high-performance bipolar transistor.

[従来の技術〕 第2図(^)〜(E)は、従来の半導体装置例えばバイ
ポーラトランジスタを製造するための主要製造工程を段
階順に示す断面図である。
[Prior Art] FIGS. 2(^) to 2(E) are cross-sectional views showing the main manufacturing steps for manufacturing a conventional semiconductor device, such as a bipolar transistor, in order of steps.

第2図(^)に示すように、まず低不純物濃度のP型半
導体基板例えばシリコン基板1に高濃度のn型コレクタ
埋込み層2を形成した後、これらの上に半導体層例えば
低濃度のn型エピタキシャル層3を成長させる。なお、
このエピタキシャル層3にはバイポーラトランジスタの
活性領域が形成される0次に素子間分離溝4をエピタキ
シャル層3の表面からコレクタ埋込み層2を通ってシリ
コン基板1の中まで形成し、素子間分離溝4の先端付近
のシリコン基板1中にチャンネルカット用P型層5を形
成した後、分離用酸化膜6を素子間分離溝4に充填する
。その後、素子を酸化してエピタキシャル層3および分
離用酸化膜6の全面に第1酸化!lA110を形成し、
その一部を除去してトランジスタの活性領域およびコレ
クタウオール領域を決定すると共にエピタキシャル層3
を部分的に露出させた後、全面に第1ポリシリコンM1
00、第2酸化膜111を堆積させる。その後、第ルジ
スト膜700をパターンニングする。
As shown in FIG. 2(^), first, a high concentration n-type collector buried layer 2 is formed on a low impurity concentration P type semiconductor substrate such as a silicon substrate 1, and then a semiconductor layer such as a low concentration n type collector layer 2 is formed thereon. A type epitaxial layer 3 is grown. In addition,
In this epitaxial layer 3, a zero-order element isolation groove 4 in which the active region of a bipolar transistor is formed is formed from the surface of the epitaxial layer 3 through the collector buried layer 2 to the inside of the silicon substrate 1, and the element isolation groove 4 is formed in the epitaxial layer 3. After forming a P-type layer 5 for channel cutting in the silicon substrate 1 near the tip of the silicon substrate 4, an oxide film 6 for isolation is filled in the isolation groove 4 between elements. After that, the device is oxidized to perform a first oxidation process on the entire surface of the epitaxial layer 3 and isolation oxide film 6! form lA110,
A portion of the epitaxial layer 3 is removed to determine the active region and collector all region of the transistor.
After partially exposing the first polysilicon M1, the entire surface is covered with the first polysilicon M1.
00, a second oxide film 111 is deposited. After that, the first resist film 700 is patterned.

第2図(B)に示すように、第ルジスト膜700をマス
クとして第2酸化膜111と第1ポリシリコン![10
0をエツチングし、活性領域部におけるエピタキシャル
層3を露出させた後、第ルジスト膜700を除去する。
As shown in FIG. 2(B), using the first polysilicon film 700 as a mask, the second oxide film 111 and the first polysilicon film 111 are bonded together. [10
After etching 0 to expose the epitaxial layer 3 in the active region, the first resist film 700 is removed.

その後、レジストマスク(図示せず)を用いてコレクタ
ウオール領域をマスクしながら露出したエピタキシャル
層3にP型不純物をイオン注入して真性ベース層7を形
成する。そして、別なレジストマスク(図示せず)を用
いて活性領域をマスクしなからコレクタウオール領域に
第2酸化膜111上からn型不純物をイオン注入し、熱
処理を施す事によりエピタキシャル層3中にコレクタウ
オール層6を形成する。
Thereafter, a P-type impurity is ion-implanted into the exposed epitaxial layer 3 while masking the collector all region using a resist mask (not shown) to form an intrinsic base layer 7. Then, without masking the active region using another resist mask (not shown), n-type impurity ions are implanted into the collector all region from above the second oxide film 111, and heat treatment is performed to form the epitaxial layer 3. A collector all layer 6 is formed.

第2図(C)に示すように、再度全面に第3酸化膜11
2を堆積後、全面エッチバックプロセスにより後で明ら
かになるサイドウオール用酸化膜112aを残す。
As shown in FIG. 2(C), the third oxide film 11 is again applied to the entire surface.
2, a sidewall oxide film 112a, which will become apparent later, is left behind by a full-surface etch-back process.

第2図(D)に示すように、全面にエミッタを極となる
第2ポリシリコン膜101をデポジットし、この第2ポ
リシリコン膜101にn型不純物を注入した後、第2レ
ジスト膜701をマスクとして第2ポリシリコン膜10
1および第3酸化膜112をエツチングする。第2レジ
スト膜701を除去せずに残したま)、第3レジスト膜
702をパターンニングし、ベース電極用第1ポリシリ
コン膜100にP型不純物を注入する。
As shown in FIG. 2(D), a second polysilicon film 101 with an emitter as a pole is deposited on the entire surface, and after implanting n-type impurities into this second polysilicon film 101, a second resist film 701 is deposited. Second polysilicon film 10 as a mask
The first and third oxide films 112 are etched. (The second resist film 701 is left without being removed), the third resist film 702 is patterned, and P-type impurities are implanted into the first polysilicon film 100 for the base electrode.

第2図(E)に示すように、その後、熱処理を施す事に
よりエピタキシャル層3中に外部ベース層9をそして真
性ベース層7中にエミッタ層10を形成する。その後、
第2レジスト膜701および第3レジストl[703を
除去して第4酸化膜例えばPSG膜400を堆積し、焼
きしめ、コンクタト用孔を形成した後、第2ポリシリコ
ン膜101上にエミッタ電極600を形成すると共に第
1ポリシリコンIgloo上にベース電極601、コン
フタ電極602をそれぞれ形成する。
As shown in FIG. 2E, an extrinsic base layer 9 is then formed in the epitaxial layer 3 and an emitter layer 10 is formed in the intrinsic base layer 7 by performing heat treatment. after that,
After removing the second resist film 701 and the third resist 703, depositing a fourth oxide film, for example, a PSG film 400, and baking it to form a contact hole, an emitter electrode 600 is formed on the second polysilicon film 101. At the same time, a base electrode 601 and a contour electrode 602 are formed on the first polysilicon Igloo.

[発明が解決しようとする課題] 従来の半導体装置の製造方法では、第1ポリシリコン膜
をエツチングする時に下地シリコン面までエツチングす
るので、この下地シリコン面との選択比がなく、シリコ
ン基板へ多大なダメージを与えるなどの問題点があった
[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method, when etching the first polysilicon film, the underlying silicon surface is etched. There were problems such as causing severe damage.

この発明はこのような問題点を解決するためになされた
もので、エツチングによるシリコン基板への、ダメージ
を回避できる半導体装置の製造方法を得ることを目的と
する。
The present invention has been made to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can avoid damage to a silicon substrate caused by etching.

[課題を解決するための手段] この発明に係る半導体装置の製造方法は、エミッタ層上
の第1ポリシリコン膜をと下地シリコン面までエツチン
グせずに若干残す工程と、残された第1ポリシリコン膜
を酸化して酸化膜を形成する工程と、前記酸化膜を介し
て不純物を注入することにより真性ベース層を形成する
工程とを含むものである。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of leaving a portion of the first polysilicon film on the emitter layer without etching it to the underlying silicon surface, and etching the remaining first polysilicon film. This method includes a step of oxidizing a silicon film to form an oxide film, and a step of forming an intrinsic base layer by injecting impurities through the oxide film.

「作 用] この発明においては、エミッタ層上の第1ポリシリコン
展を全て除去せず、除去残すようにエツチングするため
シリコン基板へのダメージが回避され、また残された第
1ポリシリコン膜を酸化して形成された酸化膜を介して
ベース層用不純物注入を行なっているためバイポーラト
ランジスタの高性能化が期待できる。
[Function] In the present invention, since the first polysilicon film on the emitter layer is etched so as to be removed without completely removing it, damage to the silicon substrate is avoided, and the remaining first polysilicon film is removed. Since the impurity for the base layer is implanted through the oxide film formed by oxidation, it is expected that the performance of the bipolar transistor will be improved.

[実施例] 第1図(^)〜第1図(C)は、この発明の一実施例の
主要工程を段階順に示す断面図である。
[Embodiment] FIGS. 1(^) to 1(C) are sectional views showing the main steps of an embodiment of the present invention in order of steps.

第1図(^)に示すように、第2図(^)に示したのと
同じ状態まで従来例と同様な方法で製造する。
As shown in FIG. 1(^), it is manufactured in the same manner as the conventional example until it reaches the same state as shown in FIG. 2(^).

第1図(B)に示すように、第ルジスト膜700をマス
クとして第2酸化膜111と第1ポリシリコンl110
0をエツチングするが、その際、第1ポリシリコン膜1
00を全部除去しないで、若干残す、なお、残された第
1ポリシリコン膜を符号100^で示す。
As shown in FIG. 1B, using the first polysilicon film 700 as a mask, the second oxide film 111 and the first polysilicon film 110 are
0, but at that time, the first polysilicon film 1
The first polysilicon film 00 is not completely removed, but is left slightly, and the remaining first polysilicon film is indicated by the reference numeral 100^.

第1図(C)に示すように、残された第1ポリシリコン
膜100^を全て酸化して酸化膜100Bを形成する。
As shown in FIG. 1C, the remaining first polysilicon film 100^ is entirely oxidized to form an oxide film 100B.

トランジスタの活性領域に在る酸化膜100Bを介して
その下のエピタキシャル層3にP型不純物を注入して真
性ベース層7を形成する。その後、従来例と同様にして
、コレクタウオール層8、外部ベース層9、エミッタ層
10を順次形成する。
P-type impurities are implanted into the underlying epitaxial layer 3 through the oxide film 100B in the active region of the transistor to form the intrinsic base layer 7. Thereafter, a collector all layer 8, an external base layer 9, and an emitter layer 10 are sequentially formed in the same manner as in the conventional example.

[発明の効果コ 以上、詳しく説明したように、この発明は、エミッタ層
上の第1ポリシリコン膜をと下地シリコン面までエツチ
ングせずに若干残す工程と、残された第1ポリシリコン
膜を酸化して酸化膜を形成する工程と、前記酸化膜を介
して不純物を注入することにより真性ベース層を形成す
る工程とを含むので、エツチングによるシリコン基板へ
のダメージを回避できるためトランジスタのリーク電流
等が低減されてトランジスタ特性が向上し、かつ浅い接
合が形成されてトランジスタの高性能化が実現されると
いう効果を奏する。
[Effects of the Invention] As explained in detail above, the present invention includes a step in which the first polysilicon film on the emitter layer is left slightly etched without being etched to the underlying silicon surface, and a step in which the remaining first polysilicon film is etched. The process includes a step of oxidizing to form an oxide film and a step of forming an intrinsic base layer by injecting impurities through the oxide film, thereby avoiding damage to the silicon substrate due to etching and reducing transistor leakage current. etc., thereby improving transistor characteristics, and forming a shallow junction to realize higher performance of the transistor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(^)〜(C)はこの発明の一実施例を説明する
断面図、第2図(^)〜(E)は従来の半導体装置の製
造方法を説明する主要工程断面図である。 図において、1はシリコン基板、3はエピタキシャル層
、7は真性ベース層、8はコレクタウオール層、9は外
部ベース層、10はエミッタ層、100は第1ポリシリ
コン膜、100^は残された第1ポリシリコン膜、10
0Bは酸化膜、111は第2酸化膜である。 なお、各図中、同一符号は同一または相当部分を示す。
FIGS. 1(^) to (C) are cross-sectional views explaining one embodiment of the present invention, and FIGS. 2(^) to (E) are cross-sectional views of main steps explaining a conventional method of manufacturing a semiconductor device. . In the figure, 1 is the silicon substrate, 3 is the epitaxial layer, 7 is the intrinsic base layer, 8 is the collector all layer, 9 is the external base layer, 10 is the emitter layer, 100 is the first polysilicon film, and 100^ is the remaining layer. first polysilicon film, 10
0B is an oxide film, and 111 is a second oxide film. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 バイポーラトランジスタを有する半導体装置の製造方法
において、 前記バイポーラトランジスタの活性領域が形成される半
導体層中のエミッタ層上の第1ポリシリコン膜を全て除
去せず、若干残すようにエッチングする工程と、 残された第1ポリシリコン膜を酸化して酸化膜を形成す
る工程と、 前記酸化膜を介して不純物を前記半導体層に注入するこ
とにより真性ベース層を形成する工程と、を含むことを
特徴とする半導体装置の製造方法。
[Claims] In a method of manufacturing a semiconductor device having a bipolar transistor, a first polysilicon film on an emitter layer in a semiconductor layer in which an active region of the bipolar transistor is formed is not completely removed but is left slightly. a step of etching; a step of oxidizing the remaining first polysilicon film to form an oxide film; and a step of forming an intrinsic base layer by injecting impurities into the semiconductor layer through the oxide film. A method for manufacturing a semiconductor device, comprising:
JP21505290A 1990-08-16 1990-08-16 Manufacture of semiconductor device Pending JPH0497534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21505290A JPH0497534A (en) 1990-08-16 1990-08-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21505290A JPH0497534A (en) 1990-08-16 1990-08-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0497534A true JPH0497534A (en) 1992-03-30

Family

ID=16665968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21505290A Pending JPH0497534A (en) 1990-08-16 1990-08-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0497534A (en)

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