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Priority to JP1991029095UpriorityCriticalpatent/JPH0536274Y2/ja
Publication of JPH0497351UpublicationCriticalpatent/JPH0497351U/ja
Application grantedgrantedCritical
Publication of JPH0536274Y2publicationCriticalpatent/JPH0536274Y2/ja
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
H01L2224/42—Wire connectors; Manufacturing methods related thereto
H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
H01L2224/4805—Shape
H01L2224/4809—Loop shape
H01L2224/48091—Arched
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
H01L2924/181—Encapsulation
Landscapes
Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices
(AREA)