JPH0496867A - Memory bank access system and vector arithmetic unit applied to the same system - Google Patents

Abstract

PURPOSE:To reduce an area occupied by a decoder circuit, and to promote a miniaturization and a high integration by sharing the plural memory banks of the decoder circuit. CONSTITUTION:A decoder circuit 13 which decodes an address signal, latch circuit 11 which latches the output signal of this circuit 13, and memory cell array 12 connected with a word line WL1 to which the output from the circuit 11 is supplied, are provided at a first memory bank 1. And also, latch circuits 21 - 41 which latch the output signals of the latch circuits at the memory banks at the previous stage, and memory cell arrays 22 - 42 connected with word lines WL2 - WL4 to which the outputs of these circuits 21 - 41 are supplied, are provided at each of memory banks 2 - 4 after the second. Then, the output of the decoder circuit 13 provided at the first memory bank 1 is delayed in every one cycle by the latch circuit provided at each memory bank, and the memory cell array in each memory bank is simultaneously performed access of by the address which is different in every one cycle.

Description

[Detailed Description of the Invention] [Summary] Regarding a high-speed memory bank access method suitable for vector processing and a vector arithmetic device applying the method, the decoder circuit is shared by a plurality of memory banks. The purpose is to promote miniaturization and high integration by reducing the area occupied, and it is equipped with multiple memory banks and performs pipeline processing by accessing vector data stored in the multiple memory nodes. A vector arithmetic device, comprising a decoder circuit that decodes an address signal, a latch circuit that latches an output signal of the decoder circuit, and a memory cell array connected to a word line to which the output of the latch circuit is supplied. The first memory bank and the previous memory bank\
a second or subsequent memory bank comprising a latch circuit that latches an output signal of the latch circuit in the first bank; and a memory cell array connected to a word line to which the output of the latch circuit is supplied; The output of the decoder circuit provided in the memory bank is delayed one cycle at a time by the circuit provided in each memory bank, and the memory cell array in each memory bank is accessed simultaneously at different addresses one cycle at a time. Configure.

[Industrial application field]

The present invention relates to memory bank access technology in vector processing, and in particular to a high-speed memory bank access method suitable for vector processing and a vector arithmetic device applying the method.

In recent years, there has been a strong demand for faster computer processing, and the field of application of vector arithmetic processing has expanded from large general-purpose computers to workstations and personal computers.

Therefore, there is a demand for vector arithmetic devices to be smaller and more highly integrated.

[Prior Art] FIG. 6 is a block diagram showing an example of a conventional vector calculation device. As shown in the figure, the conventional vector arithmetic device includes a plurality of memory banks 101-104, and each memory bank 101-104 has latch circuits 111-141. Memory cell arrays 112-142 and decoder circuits 113-143 are provided.

By the way, when performing vector processing, it is necessary to access data from all memory banks 101 to 104 every cycle.
It is necessary to input an address for each cycle one cycle at a time. Further, each memory node 101-104 is provided with a decoder circuit 113-143, respectively, which decodes a common address shifted by one cycle for each memory cell array 101-104. is designed to be accessed.

(Problems to be Solved by the Invention) As described above, in the conventional vector arithmetic device shown in FIG. , it is necessary to supply one cycle of address signals to each of these decoder circuits 113 to 143.The area occupied by the decoder circuits 113 to 143 provided in the memory banks 101 to 104 is limited to the size of a small vector arithmetic device. This is hindering the development of high-density and high-density integration.

In view of the above-mentioned problems with conventional vector arithmetic devices, the present invention reduces the area occupied by the decoder circuit by sharing the decoder circuit with a plurality of memory banks, thereby promoting miniaturization and high integration. The purpose is to

[Means for Solving the Problems] According to the present invention, a vector arithmetic device includes a plurality of memory banks 1 to 4 and performs pipeline processing by accessing vector data stored in the plurality of memory banks. There is a decoder circuit 1 that decodes the address signal.
3, a latch circuit 11 that latches the output signal of the decoder circuit 13, and a memory cell array 12 connected to the word line ridge to which the output of the latch circuit 11 is supplied. , a latch circuit 2 that latches the output signal of the latch circuit in the previous stage memory bank.
1 to 41 and memory cell arrays 22 to 42 connected to word lines -L2 to -L4 to which the outputs of the latch circuits 21 to 41 are supplied, The output of the decoder circuit 13 provided in the first memory bank 1 is delayed one cycle at a time by a latch circuit provided in each memory bank, and the memory cell arrays in each memory bank are sequentially moved one cycle at different addresses at the same time. A vector arithmetic device is provided which is characterized in that it is configured to access.

[For production]

According to the vector arithmetic device of the present invention, the first memory bank 1 includes a decoder circuit 13 that decodes an address signal, a latch circuit 11 that latches an output signal of the decoder circuit 13, and an output signal of the latch circuit 11. A memory cell array 12 connected to the word line Sushi is provided, and each of the second and subsequent memory banks 2 to 4 includes a latch circuit that latches the output signal of the latch circuit in the previous memory bank. 21 to 41, and word lines -L2 to which the outputs of the latch circuits 21 to 41 are supplied.
-Memory cell arrays 22 to 42 connected to L4 are provided. Then, the output of the decoder circuit 13 provided in the first memory bank 1 is delayed by one cycle by the latch circuit provided in each memory bank, and the memory cell array in each memory bank is sequentially read at a different address by one cycle. They are accessed simultaneously. In this way, the vector arithmetic device of the present invention shares the decoder circuit with a plurality of memory banks.
The area occupied by the decoder circuit can be reduced to promote miniaturization and high integration.

〔Example〕

Hereinafter, embodiments of a vector calculation device according to the present invention will be described with reference to the drawings.

1M is a block diagram showing an embodiment of the vector calculation device according to the present invention, and shows a layout image of a 4-bank configuration.

As shown in FIG. 1, the vector arithmetic device of this embodiment includes a plurality of memory banks 1-4. The first memory bank 1 is provided with a latch circuit 11, a memory cell array 12, and a decoder circuit 13.
The latch circuits 21 to 3 are provided in memory banks 2 to 3 after the memory bank 2 to 3.
41 and memory cell arrays 22 to 42 are provided, and no decoder circuit is provided. Then, the address signal is supplied only to the decoder circuit 13 in the first memory bank 1, and the address signal is supplied only to the decoder circuit 13 in the first memory bank 1.
3, the output signal of the coder circuit 13 in the first memory bank l is used.

First, the output signal of the decoder circuit 13 is supplied to the memory cell array 12 of the first memory bank 1 via the latch circuit 11 of the first memory bank 1; Latch circuit 2 of second memory bank 2 via word line
1 to the memory cell array 22 of the second memory bank 2. Similarly, the output signal of the latch circuit 21 is supplied to the memory cell array 32 of the third memory bank 3 via the word line -L2 of the memory cell array 22 and the latch circuit 3I of the third memory bank 3. The output signal of the circuit 31 is the word MWI of the memory cell array 32.

The signal is then supplied to the memory cell array 42 of the fourth memory bank 4 via the latch circuit 41 of the fourth memory bank 40. Here, the latch circuits 11 to 41 in each memory bank 1 to 4 are supplied with a clock signal CLK, respectively, and in the latch circuits 11 to 41, the output of the decoder circuit 13 and the previous stage latch circuits 11 to 41 are supplied with a clock signal CLK. The outputs of 31 are each delayed by one cycle and supplied to the corresponding memory cell arrays 12-42.

That is, the memory cell array 12 of the memory bank 1 is
The memory cell array 22 of the memory bank 2 is accessed by the output signal of the decoder circuit 13 delayed by one cycle by the latch circuit 11.
1 and 21, the output signal of the decoder circuit 13 is delayed by two cycles. Similarly,
The memory cell array 32 of the memory bank 3 is accessed by the output signal of the decoder circuit 13 delayed by three cycles by the latch circuits II, 21 and 31, and the memory cell array 22 of the memory bank 4 is accessed by the output signal of the decoder circuit 13 delayed by three cycles by the latch circuits II, 21 and 31. It is accessed by the output signal of the decoder circuit 13 delayed by 4 cycles by .31 and 41. Therefore, the memory cell arrays 11 to 41 in each memory bank 1 to 4 have different addresses by one cycle sequentially. In other words, the address accessing the previous memory bank is supplied to the next memory bank with a one cycle delay. As a result, a plurality of memory banks are accessed simultaneously, and successive access/write processing is executed in parallel in a plurality of memory banks.

FIG. 2 is a circuit diagram showing essential parts of the vector calculation device shown in FIG. 1. As shown in the figure, the decoder circuit 13 in the first memory bank 1 has 0 address inputs (
The decoder circuit 13 is a circuit that receives an address signal (address signal) and activates one of the 2'' outputs.Here, the decoder circuit 13 has, for example, four inverters and four NOR gates, and the address input is Although the two output lines are configured to select one of the four output lines, various configurations can be used.

The latch circuits 11.2H31, 41) are each configured with a flip-flop, are supplied with the clock signal CLK, hold data at the change point (rising edge) of the clock signal CLK, and hold the data at each memory cell array 12.22 (32H).
, 42). Then, the memory cell array 12.22 (32, 42) is activated by the signal (word line WL+, WLz (WLzJLa)) output from the corresponding latch circuit LL21 (31, 41). ) to perform read or write processing (bit line BL+ (:BIT, BIT")
, BL2 (BL3.BL4) ).

FIG. 3 is a diagram for explaining the operation of the vector arithmetic device shown in FIG. 1. As shown in Figures 1 and 3,
First, at the rising edge C1 of the clock signal CLK, the address signal ADO is taken into the decoder circuit 13 in the first memory bank 1 and decoded.

Next, at the rising edge C2 of the clock signal CLK, the address signal MDI is taken into the decoder circuit 13 and decoded. At this time, the output signal BDO (signal obtained by decoding address ADO) of the decoder circuit 13 is latched by the latch circuit 1 of the memory bank 1. Then, the signal BDO is supplied from the latch circuit 11 to the memory cell array 12 in the first memory bank 1, and data input/output (write/read) processing is performed on the memory cell corresponding to the address ADO. In addition, latch circuit 1
1 output signal (BDO) is also supplied to the latch circuit 21 in the second memory bank 2 via the word line -Ll of the memory cell array 12. This output signal BDO is latched by the latch circuit 21 at the next rising edge C3 of the clock signal CLK.

Further, at the rising edge C3 of the clock signal CLK, the address signal AD2 is taken into the decoder circuit 13 and decoded. At this time, the output signal BDI of the decoder circuit 13 is latched by the latch circuit 11 of the memory bank 1, and data input/output processing is performed to the memory cell corresponding to the address ADI of the memory cell array 12. In addition, in the second memory bank 2, the latch circuit 2
Data input/output processing is performed on the memory cell corresponding to the address ADO of the memory cell array 22 in the second memory bank 2 by the output signal BDO from the second memory bank 2 . Here, the output signal (BDO) of the latch circuit 21 is also supplied to the latch circuit 31 in the third memory bank 3 via the word line hole 2 of the memory cell array 22.

This output signal BDO is latched by the latch circuit 31 at the next rising edge C4 of the clock signal CLK. Thereafter, such operations are performed until the instruction ends. From the perspective of the input/output (bit line) of the memory cell array, pipeline processing is performed.

In this way, the memory cell arrays 11 to 41 in each memory bank 1 to 4 are sequentially accessed in parallel by different addresses one cycle at a time. In FIG. 3, all four nodes operate in parallel after the rising edge C5 of the clock signal CLK.

FIG. 4 is a block diagram showing another embodiment of the vector calculation device of the present invention.

The vector arithmetic device in FIG.
The output signal of 31 is a dedicated next-stage bank connection line.

~L3, the signal is supplied to the latch circuits 21 to 41 at the next stage. That is, in the vector calculation device shown in FIG. 1, for example, the output signal of the latch circuit 11 is 1.
It is supplied to the latch circuit 21 in the second memory bank 2 via the word line of the memory cell array 12 in the second memory bank 1. The output signal is sent to the latch circuit 21 in the second memory bank 2 via the dedicated next-stage bank connection line L+ without passing through the memory cell array 12 in the first memory bank 1.
is being supplied to. The other configuration and operation of the vector arithmetic device shown in FIG. 4 are the same as those of the vector arithmetic device shown in FIG. 1, and their explanation will be omitted.

FIG. 5 is a diagram schematically showing the overall configuration of the vector arithmetic device, and shows how pipeline processing is performed by the vector arithmetic device shown in FIGS. 1 and 4 described above.

As shown in FIG. 5, in the vector arithmetic device, (R) data read from memory banks 1 to 4 is supplied to arithmetic pipelines A to C via a bank selector BS, and the arithmetic pipelines The output of A-C is written to memory banks 1 to 4 via bank selector BS (W)
It looks like this.

That is, the operation pipeline A-C is, for example, an addition 1
It performs arithmetic processing such as multiplication and subtraction, and the data read from each memory bank 1 to 4 is sequentially switched by the B link selector BS and supplied to the arithmetic pipelines A to C for vector processing. It has become. Here, vector processing refers to processing in which data to be processed is stored in an orderly manner, and the data is sequentially read out and pipeline processing is performed to make the data processing speed appear higher. Further, vector data needs to be read every cycle, but at that time, other banks are accessed at the same time. In the vector arithmetic device shown in Part 1 and FIG. 4, in the access method involving R/W4 of hector registers (memory banks 1 to 4), there is one address decoder (decoder circuit 13), and the same address is By shifting the input for each memory bank, it is possible to read/write continuous vector data, making it possible to read and write continuous vector data.

Line processing is now possible.

(Effects of the Invention) As detailed above, the vector calculation device of the present invention has the following features:
By sharing the decoder circuit among a plurality of nodes, the area occupied by the decoder circuit can be reduced and miniaturization and high integration can be promoted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the vector calculation device according to the present invention, FIG. 2 is a circuit diagram showing the main parts of the vector calculation device shown in FIG. 1, and FIG. 3 is the vector calculation device shown in FIG. 1. FIG. 4 is a block diagram showing another embodiment of the vector calculation device of the present invention; FIG. 5 is a diagram schematically showing the overall configuration of the vector calculation device; FIG. 6 1 is a block diagram showing an example of a conventional vector calculation device. (Explanation of symbols) 1-4...Bank, 11-41...Latch circuit, 12-42...Memory cell array, 13...Decoder circuit, BL, -BL4...Word line, WL2- WL4...word line, L1-L3...next stage bank connection line. FIG. 4 is a program diagram showing another embodiment of the vector arithmetic device of the present invention, and bank selector BS is a diagram S schematically showing the overall configuration of the vector arithmetic device.

Claims (1)

[Claims] 1. A vector arithmetic device comprising a plurality of memory banks (1 to 4) and performing pipeline processing by accessing vector data stored in the plurality of memory banks, the device comprising: an address signal; a decoder circuit (13) for decoding the
A latch circuit (1) that latches the output signal of the decoder circuit.
1) and a word line (W) to which the output of the latch circuit is supplied.
a first memory bank (1) comprising a memory cell array (12) connected to the memory cell array (12), a latch circuit (21 to 41) that latches the output signal of the latch circuit in the previous memory bank, and the latch circuit. and memory cell arrays (22 to 42) connected to word lines (WL_2 to WL_4) to which the outputs of the second and subsequent memory banks (2 to 4) are connected to the first memory bank. The output of the provided decoder circuit is delayed one cycle at a time by a latch circuit provided in each memory bank,
A vector arithmetic device characterized in that memory cell arrays in each memory bank are sequentially accessed one cycle at a time using different addresses. 2. The output of the decoder circuit provided in the first memory bank is sequentially supplied to the latch circuit provided in the next stage memory bank via the latch circuit and the word line of the memory cell array. A vector calculation device according to claim 1. 3. The output of the decoder circuit provided in the first memory bank is sequentially connected to a latch circuit and a dedicated connection wiring (L_
2. The vector arithmetic device according to claim 1, wherein the vector arithmetic device is supplied to a latch circuit provided in a next-stage memory bank via L_3). 4. A memory bank access method that performs pipeline processing by accessing vector data stored in multiple memory banks, in which the output of a decoder circuit provided in the first memory bank is provided in each memory bank. A memory bank access method characterized in that the memory cell array in each memory bank is sequentially accessed one cycle at a time at different addresses by delaying one cycle at a time using a latch circuit. 5. The output of the decoder circuit provided in the first memory bank is sequentially supplied to the latch circuit provided in the next stage memory bank via the latch circuit and the word line of the memory cell array. The memory bank access method according to claim 4. 6. The output of the decoder circuit provided in the first memory bank is sequentially supplied to the latch circuit provided in the next stage memory bank via the latch circuit and dedicated connection wiring. The memory bank access method according to item 4.