JPH0496277A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To erase by application of a low voltage by forming the same conductivity type erasing gate as that of a drain near the drain, and forming a bipolar transistor of an erasing gate, a semiconductor substrate and the drain. CONSTITUTION:When information is erased, a p-type semiconductor substrate 1 is held at 0V, an n-type erasing gate 4 is held at -1V, and an n-type drain 3 is held at about 7V. Thus, an n-p-n type bipolar transistor having the gate 4 as an emitter, the substrate 1 as a base and the drain 3 as a collector is conducted. If a collector voltage is sufficiently raised, the vicinity of the collector becomes a high electric field, and many hot holes and hot electrons are generated. The hot holes are implanted in a floating gate 8, stored electrons in the gate 8 are neutralized, the valve of charge approaches to '0', and stored information can be erased.

Description

[Detailed Description of the Invention] [Summary] Regarding the structure of a non-volatile semiconductor memory device that can be written and erased electrically, erasing can be performed by applying a low voltage without the need for ultraviolet irradiation or high voltage. The purpose of the present invention is to provide a floating gate that is not electrically connected to the outside, which is formed on the surface of a first conductivity type semiconductor substrate via an insulating film, and which is capacitively coupled to the floating gate. A MISFET non-volatile semiconductor memory device comprising a control gate formed on the semiconductor substrate, and a source and drain of a first conductivity type and an opposite conductivity type formed oppositely to each other with the floating gate in between. , an erase gate having the same conductivity type as the drain is formed near the drain, a bipolar transistor is formed by the erase gate, the semiconductor substrate, and the drain, and M near the drain is formed.
A charge of a first polarity generated from the channel of the ISFET is injected into the floating gate and accumulated, or a charge of a polarity opposite to the first polarity generated from the base of the bipolar transistor near the drain is injected into the floating gate. However, it was configured to store information by electrically changing the accumulated charge in the floating gate.

Furthermore, in the above case, one gate is used which serves both as a control gate and an erase gate.

[Industrial Application Field] The present invention relates to the structure of an electrically writable and erasable nonvolatile semiconductor memory device.

[Conventional technology]

EPRO is a typical non-volatile semiconductor memory device.
M is widely known.

3(a) to 3(c) are block diagrams of a conventional EFROM memory cell, where FIG. 3(a) is a plan view, and FIG. 3(b) is a cross-sectional view taken along line A-A''. Figure 3(c) is B.
It is a sectional view taken along the -B' line.

In this figure, 11 is a P-type Si substrate, 2 is a source of an n3-type region, 13 is a drain of an n-type region, 14 is a channel,
15 is a Sin gate insulating film, 16 is a Sin field insulating film, 17 is a floating gate that is not electrically connected from the outside, 18 is a Sin insulating film, and 19 is capacitively coupled to the floating gate. It is a control gate.

In this way, the memory cell of the EPROM has a structure in which a floating gate exists under the gate of the so-called n-channel MO3) run lister.

Note that the thickness of the above 5iOz insulating film 15.18 is 300
The thickness of the SiO□ insulating film 16 is about 7,000 people.

The operation of this EFROM will be explained below.

Erasing When attempting to erase the memory contents of the EFROM, the floating gate of the memory cell is irradiated with ultraviolet rays.

The ultraviolet rays cause the charges accumulated in the floating gate to be discharged to the semiconductor substrate, and the charges in the floating gate become zero.

In this state, the memory cell control gate, source,
When a voltage suitable for operation is applied to the drain, it becomes conductive.

This conductive state is defined as information "1".

That is, erasing is to change all memory cells to information "'1" by irradiating them with ultraviolet rays.

When writing write information, a high voltage is applied to the control gate and drain.

This high voltage causes avalanche breakdown, and some of the electrons that have gained high energy during this process are captured and stored in the floating gate.

In this state, even if an operating voltage is applied to the control gate, source, and drain of the memory cell, the memory cell will not conduct because electrons are accumulated in the floating gate and its potential is negative. do not.

This state is defined as information II OII.

That is, the information in the storage cell changes from "1" to "O" due to the avalanche breakdown.

This is information writing.

In EPROM, all memory cells are erased with information'
Necessary information can be erased and stored by changing a predetermined memory cell to information "0".

Read the correct operating voltage for this storage cell, e.g. OV at the source.
l When IV is applied to the drain and 5V is applied to the control gate, a drain current flows into the storage cell with information ``1'', but no drain current flows into the storage cell with information ``0''.

In this way, reading is to detect whether the memory cell is conductive or not conductive when an appropriate voltage is applied to the memory cell.

In addition, EEPROM and FLASHEPRO do not use ultraviolet rays for erasing, but instead use tunneling for writing and erasing.
A nonvolatile semiconductor memory device called M has been realized.

[Problem to be solved by the invention]

In the conventional EFROM described above, ultraviolet irradiation is required to erase the stored information, so a separate large-sized ultraviolet irradiation device is required, and the irradiation method in that case is also complicated. Ta.

In addition, (7) EEPROM and FLASHEPROM
In order to utilize the tunnel phenomenon for writing and erasing, it is necessary to form an extremely thin oxide film called a tunnel region in the memory cell. V/c
Since a high electric field of m is required, a power supply close to 20V must be used.

However, high voltage and micro integrated circuits are difficult to coexist.

Currently, writing to EFROM can be done at about IOV using avalanche breakdown, so there is a strong demand for an EFROM that can also be erased at a similar low voltage. ing.

SUMMARY OF THE INVENTION An object of the present invention is to provide an EPROM that can be erased by applying a low voltage without irradiating ultraviolet rays or applying a high voltage.

[Means for Solving the Problems] In the nonvolatile semiconductor memory device of the present invention, a floating device that is not electrically connected to the outside and is formed on the surface of a first conductivity type semiconductor substrate with an insulating film interposed therebetween. a gate, a control gate formed to capacitively couple with the floating gate, and a source and drain of a first conductivity type and an opposite conductivity type formed on the semiconductor substrate to face each other and to be separated from each other with the floating gate in between. MISF consisting of
In the ET nonvolatile semiconductor memory device, an erase gate having the same conductivity type as the drain is formed near the drain, a bipolar transistor is formed by the erase gate, the semiconductor substrate, and the drain, and a MISFE near the drain is formed.
Charges of the first polarity generated from the channel of the T are injected into the floating gate and accumulated, or charges of opposite polarity to the first polarity generated from the base of the bipolar transistor near the drain are injected into the floating gate. , adopted a means of storing information by electrically changing the accumulated charge in the floating gate.

Furthermore, in this case, one gate was used that served both as a control gate and an erase gate.

[Effect]

In order to erase the information in the conventionally known ultraviolet erasure EFROM, it is necessary to irradiate it with ultraviolet light or apply a high voltage.
A bipolar transistor is formed by the source, semiconductor substrate, and erase gate, and when a certain high voltage is applied to the drain corresponding to the collector, the charge in the floating gate is neutralized by real holes generated near the collector, and the memory is stored. You can erase the information that has been

[Example〕 Embodiments of the present invention will be described below based on the drawings.

(1) First Embodiment FIGS. 1(a) to 1(C) are block diagrams of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1(a) is a plan view;
FIG. 1(b) is a cross-sectional view taken along line AA', and FIG. 1(c) is a cross-sectional view taken along line B-B'i.

In the figure, l is a p-type semiconductor substrate, 2 is an n-type source, and 3
is an n-type drain, 4 is an n-type erase gate, 5 is a channel,
6 is a 5in2 gate insulating film, 7 is a SiO□ field insulating film, 8 is a floating gate, 9 is a Sin, film, 1
0 is a control gate capacitively coupled to the floating gate.

The thickness of the SiOz film 6 and the SiO□ film 9 is approximately 300, and the thickness of the SiO2 film 7 is approximately 7000.

In this embodiment, when the erase gate 4 is kept at Ov during reading and writing, the operation is exactly the same as that of a conventional EPROM storage cell.

Next, the case of erasing information stored in this memory cell will be explained.

In this case, the p-type semiconductor substrate 1 is set to OV, the n-type erase gate 4 is set to about 11cm, and the n-type drain 3 is set to about 7cm.

In this way, an npn type bipolar transistor having the n type erase gate 4 as the emitter, the P type semiconductor substrate 1 as the base, and the n type drain 3 as the collector becomes conductive.

If the collector voltage is raised sufficiently, a high electric field will be created near the collector, and a large number of hot holes and hot electrons will be generated.

Here, if the control gate 10 is set to 0■,
When electrons are accumulated in the floating gate 8, hot holes are injected into the floating gate 8 by the electric field created by the electrons, the accumulated electrons in the floating gate 8 are neutralized, the charge approaches O, and the electric charge is accumulated. This will allow you to delete the information that was previously displayed.

(2) Second Embodiment FIGS. 2(a) to 2(c) are block diagrams of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 2(a) is a plan view;
FIG. 2(b) is a sectional view taken along the line AA", and FIG. 2(c) is a sectional view taken along the line BB".

The same reference numerals in the figure are used for those having the same meaning as those used in the first embodiment, and the n-type erase gate 4 also serves as the control gate 10 in the first embodiment.

The operation of this embodiment is basically the same as the erasure shown in FIG. 1, but in this case, since the n-type erase gate 4 also serves as a control gate,
When configuring and erasing an npn bipolar transistor with the n-type drain 3 as the collector, the electric field formed by the n-type erase gate 4 is applied to the floating gate 8.
This will add to the electric field created by the electrons stored in the

[Effects of the Invention] As explained above, according to the present invention, information stored in a memory cell can be electrically erased by applying a low voltage without using ultraviolet irradiation.
A FROM storage cell can be realized.

Furthermore, in the present invention, by selecting the bit line connected to the erase gate and drain, only the memory cell at the intersection can be erased.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are cross-sectional views of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, and FIGS. 2(a) to (c) are
3(a), (b), and (C) are cross-sectional views of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
FIG. 2 is a configuration diagram of a memory cell of FIG. 1-p-type semiconductor substrate, 2-n-type source, 3-n-type drain, 4-n-type erase gate, 5-channel, 6-・-3i
O□ gate insulating film, 1-3 i O□ field insulating film, 8-.- floating gate, 9-3 iOt film, 1
0-・-Control Gate Patent Applicant Fujitsu Limited Representative Patent Attorney Shoji Aitani

Claims (2)

[Claims] (1) A floating gate that is not electrically connected to the outside and is formed on the surface of a first conductivity type semiconductor substrate via an insulating film, and a control gate that is formed to be capacitively coupled to the floating gate. , in a MISFET nonvolatile semiconductor memory device comprising a source and a drain of a first conductivity type and an opposite conductivity type, which are formed on the semiconductor substrate to face each other with the floating gate in between; Forming an erase gate of the same conductivity type, forming a bipolar transistor with the erase gate, the semiconductor substrate, and the drain, and injecting a first polarity charge generated from the channel of the MISFET near the drain into the floating gate. Alternatively, by injecting charges having a polarity opposite to the first polarity generated from the base of the bipolar transistor near the drain into the floating gate and electrically changing the accumulated charges in the floating gate, information can be stored. A nonvolatile semiconductor memory device characterized by storing. (2) The nonvolatile semiconductor memory device according to claim 1, wherein one gate is formed which serves both as a control gate and an erase gate.