JPH0488750A - Picture processor - Google Patents

Abstract

PURPOSE:To keep the picture quality of both an image data and a text data in an excellent way without increasing a memory capacity by using plural gradation information storage means selectively based on resolution information stored in a resolution information storage means. CONSTITUTION:A data inputted from an input terminal 1 is given to a data identification circuit 2, in which header information is decoded, the decoded data for identifying a background is stored in a resolution memory 3, a background color and a drawn color in an image area are stored in a gradation memory 4 and a text drawn color and an image data are stored in a gradation memory 52 respectively. Then a data by one page is transferred to the memories 3, 4, 52 and a printer engine is started, then a data corresponding to each picture element from a head picture element of the page is fed sequentially to a control terminal of a selector 6 and terminals a, b from the resolution memory 3 and the gradation memories 4, 52. A selector 6 selects a background color being an output of the gradation memory 4, the text drawn color being an output of the gradation memory 52 and the image data according to an output signal of the resolution memory 3 and outputs the gradation data from an output terminal 7 to the printer engine.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device having a storage means for storing images, and particularly to line drawings such as characters and graphics (hereinafter referred to as "text"), The present invention relates to an image processing device that stores image information containing a mixture of halftone images (hereinafter referred to as "images") such as photographs having halftones.

[Conventional technology]

Generally, when storing text, high resolution is required to ensure smoothness and continuity of diagonal lines, etc., while when storing images, high gradation is required to avoid deterioration of image quality due to false contours. sexuality is required. Therefore, conventionally, when storing an image in which an image area and a text area coexist, the number of pixels that can achieve sufficient resolution to ensure the quality of the text, that is, the smoothness and continuity of diagonal lines, etc., and the image The storage device is configured to have a number of gradation levels that can avoid image quality deterioration due to false contours.

[Problem that the invention is trying to solve]

However, according to the above conventional storage device, in order to achieve high image quality for both text and images, both the number of pixels and the number of gradations increase, resulting in the need for a huge memory capacity. However, the disadvantage is that the scale of the device (hardware) and cost become enormous. In particular, when trying to store a full-color image, three branes for the three primary colors, red (R), green (G), and blue (B), are required, so the memory capacity is tripled. For example, set the number of gradations of each RGB plane of image data to 2.
56, the number of bits per pixel required for full-color display is 24, and 24 times the memory capacity is required compared to the case of only monochrome characters (the number of bits per pixel is 1).

The present invention has been made in view of the above-mentioned points, and is an apparatus for storing images in which text and images are mixed, without increasing the memory capacity, and in particular, improving the image quality of both images and text having color information. An object of the present invention is to provide an image processing device that can maintain good image quality.

[Means and effects for solving the problems] In order to solve the above problems, the image processing apparatus of the present invention includes a plurality of gradation information storage means for storing gradation information and a plurality of gradation information storage means for storing resolution information. The present invention is characterized in that it has a resolution information storage means, and selectively uses the plurality of gradation information storage means according to the resolution information stored in the resolution information storage means.

〔Example〕

First Embodiment> FIG. 1(a) is a block diagram showing the configuration of an image storage section of an image processing apparatus according to a first embodiment of the present invention. In the figure,
1 is an input terminal, 3 is a resolution memory, 50 is a data identification circuit, 4.51.52 is a gradation memory, 6.53 is a selector,
7 is an output terminal.

A host computer or the like is connected to the input terminal 1, and the header information of the data input from the input terminal 1 is interpreted by the data identification circuit 50, and the bitmap data of the text is stored in the resolution memory 3 as the text. The gradation (color) data is stored in the gradation memory 4, the background color is stored in the gradation memory 51, and the image data having halftones is stored in the gradation memory 52. When data for one page is transferred from the host computer to each of the above memories and the printer engine is started, the page is transferred from resolution memory 3 and gradation memory 451 and 52 in response to a synchronization signal from the printer side. Reading of the memory is controlled so that data corresponding to each pixel is output in order from the beginning. The output (i.e., background color) of the gradation memory 51 is connected to the terminal a of the selector 53, the output (i.e., image data) 121 of the gradation memory 52 is connected to the terminal a, and the output of the gradation memory 51 (i.e., image data) is connected to the control terminal. An image area signal 122 output from 52 is input. Therefore, image data is output to the terminal C of the selector 52 when the current pixel is in the image area, and the background color is output when the current pixel is outside the image area (supplied to the terminal C of the selector 6).

The selector 6 follows the output data of the resolution memory 3, and when the data of the resolution memory 3 is "1", the data of the terminal a (that is, the data of the gradation memory 4) is set as the drawing color.
When the data of is "0", the data of the terminal 7 (that is, the data of the gradation memory 5) is selected as the background color, and the data of the output terminal 7 is selected.
outputs gradation data to the printer engine.

The data stored in the resolution memory 3 is the gradation memory 4.5.
In this embodiment, each pixel is 1-bit data in order to maintain resolution.

On the other hand, the gradation memories 4 and 51 each store full gradation data (in this embodiment, 24 bits of data in total, 8 bits each for RGB), but the number of pixels (resolution) is limited in order to reduce memory capacity. be done.

FIG. 2 is a block diagram showing a specific example of the configuration of the gradation memory 52 of this embodiment. In the figure, 9 is a memory, 54 is a compression rate setting circuit, 55 is a compression circuit, 56 is an expansion circuit, and 57 is an area detection circuit.

The header of the image data has the start address of the image area and the size of the image area, that is, the width and height, and the compression rate setting circuit 54 calculates the amount of data in the image area from the width and height of the image area. The compression ratio is set based on the ratio to the capacity of the memory 9 and is output to the compression circuit 55.

The compression circuit 55 is a circuit as shown in FIG. 3, and the quantization conditions are controlled so that a set compression ratio is achieved, and the compressed data is stored in the memory 9. The compression rate setting circuit 54 also generates coordinate values of the start and end points of the image area from the header information, and sets the coordinate values in each register of the area detection circuit 57. The area detection circuit 57 is similar to the area detection circuit 33 in FIG. 7, which will be described later.

On the other hand, when the printer engine is started, in synchronization with H8YNC on the printer side, the area detection circuit 57 determines whether the current pixel is a pixel in the image area. Output area signal. When the image area signal is input to the decompression circuit 56, the decompression circuit 56 decompresses the compressed data stored in the memory 9 into the original image data and outputs it from the signal line 121.

The compression circuit 55 is a compression encoding circuit that performs known encoding such as orthogonal transform encoding, vector quantization, and block encoding. In this embodiment, the compression ratio is set quite high in order to reduce memory capacity, so lossy encoding is used.

Therefore resolution is not preserved. However, it is of course possible to use reversible encoding such as run-length encoding.

FIG. 3 is a block diagram showing a specific example of the configuration of the compression circuit 55. As shown in FIG. This example uses JPEG (Joint Photography), which is a collaboration between Is○ and CCITT.
Ba5 of the International Standardization Office for Color Still Image Coding proposed by the phicExpert Group)
The encoding unit of the eline System is shown. (
References Niyasuda, “International Standardization of Color Still Image Coding” 9
Journal of the Institute of Image Electronics Engineers.

Volume 18, No. 6, PP, 398-407. 19
89) The image pixel data inputted from the signal line 103 is cut out into blocks of 8×8 pixels by the blocking circuit 11 configured with line memories for several lines, and then processed by the discrete cosine transform (DCT) circuit 12. A cosine transform is performed, and the transform coefficients are supplied to a quantizer (Q) 13. The quantizer 13 performs linear quantization of the transform coefficients according to the quantization step information applied by the quantization table 14. Among the quantized transform coefficients, the DC coefficient is used in a predictive coding circuit (DPCM) 15 to calculate the difference (prediction error) from the DC component of the previous block.
6.

FIG. 4 is a detailed block diagram of the predictive encoding circuit 15. The DC coefficients quantized by the quantizer 13 are applied to a delay circuit 25 and a subtracter 26. The delay circuit 25 is
The discrete cosine transform circuit is a circuit that delays the time required to calculate one block, that is, 8×8 pixels. Therefore, the DC coefficient of the previous block is supplied from the delay circuit 25 to the subtracter 26. Therefore, the subtracter 26 outputs the difference in DC coefficients (prediction error) from the previous block. (Since this predictive coding uses the previous block value as the predicted value, the predictor is configured with a delay circuit as described above.

The Huffman encoding circuit 16 variable-length encodes the prediction error signal supplied from the predictive encoding circuit 15 according to the DC Huffman code table 17, and sends the prediction error signal to the multiplexing circuit 24 using DC
Provides Huffman code.

On the other hand, the AC coefficients (coefficients other than DC coefficients) quantized by the quantizer 13 are sent to the scan conversion circuit 18 as shown in FIG.
), the coefficients are zigzag-scanned in order from the lowest order coefficients and are supplied to the significant coefficient detection circuit 19.

In the significant coefficient detection circuit 19, the quantized AC coefficient is “0”.
”, and if “O”, run length counter 20
A count-up signal is supplied to the counter, and the value of the counter is increased by +1. On the other hand, in the case of a coefficient other than "0", a reset signal is supplied to the run length counter, the value of the counter is reset, and the coefficients are sent to the grouping circuit 21 as shown in FIG.
), the group number 5sss is divided into a group number 5sss and additional bits, and the group number 5sss is supplied to the Huffman encoding circuit 22, and the additional bits are supplied to the multiplexing circuit 24, respectively.

The run length counter 20 is a circuit that counts the run length of "0" and supplies the number NNNN of "0" between significant coefficients other than "0" to the Huffman encoding circuit 22. Huffman encoding circuit 2
2 performs variable length encoding on the supplied run length NNNN of "0" and group number 5sss of significant coefficients according to the AC Huffman code table 23, and supplies the AC Huffman code to the multiplexing circuit 24.

The multiplexing circuit 24 multiplexes the DC Huffman code, AC Huffman code, and additional bits for one block (8×8 input pixels), and compressed image data is output from the signal line 104.

Therefore, it is possible to reduce the memory capacity by storing the compressed data output from the signal line 104 in a memory and decompressing it by performing the reverse operation when reading the data.

Note that since the decompression circuit 56 performs the opposite operation of the compression circuit 8,
Explanation will be omitted.

FIG. 6 is a block diagram showing a specific example of the configuration of the gradation memories 4 and 51. In the figure, 29. 31 is a selector, 30
is a register group, and 32 is an area determination circuit.

The gradation data input from the signal line 108 is sent to the selector 29.
The data are sequentially stored in registers 30-2 to 30-n. Note that default gradation data (for example, white in the gradation memory 4 and white in the gradation memory 51) is set in the register 30-1. The area determination circuit 32 is connected to the signal line 10
5. The range in which the gradation data stored in each register is valid is determined from the coordinate values of the output data of the resolution memory 3 inputted from the signal line 106, the selector 31 is controlled, and the effective gradation data is inputted from the signal line 109. Output.

FIG. 7 is a block diagram showing a specific example of the configuration of the area determination circuit 32. In the figure, 33 is an area detection circuit, 34 is a priority encoder, 35.36 to 3738 are registers, 39.40 is a comparison circuit, and 41 is an AND circuit.

In this embodiment, the effective area of each gradation register 30-2 to 30-n is limited to a rectangle as shown in FIG. 8, and the first scanned point (xo, yo) (in FIG. the upper left corner (hereinafter referred to as the "starting point") and the last scanned point (
Xl, yl) (In the figure, the lower right corner of the rectangle, hereinafter referred to as the "end point"
It is set at two points. Note that in the figure, the X-axis direction is the main scanning direction of the printer, and the y-axis direction is the sub-scanning direction.

The coordinate values (x) of the starting point and ending point identified by the data identification circuit 2.

yo) and (x l+ yl) are the respective registers 35 of the area detection circuit 33 corresponding to the gradation register 30 in FIG.
Stored at ゜37.36.38.

On the other hand, when printing out, each coordinate value of pixel data read out from the resolution memory 3 is inputted from the signal lines 105 and 106. The first comparison circuit 39 calculates the X coordinate value X of the resolution memory 3 and the X coordinate values X of the starting point and the X ending point.

+Xl, and when x0≦x≦x1, set “1” to x
When <x O or x>x 1, set “0” to AND circuit 4
Enter 1. Similarly, the second comparison circuit 40 calculates that y0≦y
“1” when ≦y1, and “1” when Y<Y.

Or, when y>yl, 0'' is input to the AND circuit 41. Therefore, from the AND circuit 41, (i) x0≦X≦X1
When y0≦y≦y1, “1” is output, and when the conditions other than (ii) and (i), “0” is output, making area detection possible. The results detected by each of the area detection circuits 33-2 to 33-n are processed by the priority encoder 34 to determine the priority of overlapping areas as shown in the shaded area in FIG. , the number of the last set area is encoded and output from the signal line 107.

That is, in the overlapping part, the area set later is determined to be valid. Note that if all the region determination results are "0", the priority encoder 34 outputs "0" and selects the gradation data (i.e., default value) of the gradation register 30-1 in FIG. The selector 31 is controlled as follows.

Usually, the resolution memory 3 stores dot resolution data such as text which requires high resolution, and the gradation memory 5 stores data such as images which requires high gradation. The gradation (color) data of the text data is stored in the gradation memory 4. If the gradation (color) of the text data is constant (i.e. single color) over one page, or if the background (background color) is constant (single color), the text data that overlaps the image part has the above background color. If the above,
Since the content of the gradation memory 4 is only the default, registers after the area determination circuit 32, 30-2 are not required.

Note that the gradation memory is, for example, 8 (pixels) x 8 (lines).
A configuration in which one gradation (color) is set for each block may also be used.

The resolution memory 3 is a memory with a page capacity for each pixel of 1 bit, but since it is used for switching gradation data, the correlation between pixels is quite high, and reversible data as shown in Figure 12 is generated. By using compression encoding, it is also possible to compress the amount of data.

FIG. 12 is a block diagram showing another embodiment of the resolution memory 3. In the figure, 60 is a run-length encoding circuit, 61
62 is a memory, 63 is a Huffman decoding circuit, and 64 is a run-length decoding circuit. Since the run length and Norfman encoding/decoding circuits are well known, their explanations will be omitted.

FIG. 1(b) is a diagram showing the overall configuration of an image processing apparatus including the image storage section of FIG. 1(a).

In FIG. 1(b), 200 is an image input unit connected to the host computer, which is an interface for image reading devices such as an image scanner including a CCD sensor, and external devices such as the Sv right camera and video camera. etc. may be used. In the latter case, the data identification circuit 50 identifies the data. The image data input from 200 is stored in the image storage unit 2 shown in FIG. 1(a).
01 input terminal 1. Reference numeral 202 indicates an operation unit through which the operator specifies output light for image data, and 203 indicates an output control unit, which selects output light for image data, outputs a synchronization signal for reading memory such as HSYNC of the printer engine, etc. I do. The synchronization signal is supplied to the identification circuit 50 of FIG. 1(a) and each memory, and is used as a control signal for data transfer, reading from the memory, etc. 20
4 is an image display unit such as a display; 205 is a transmitting unit that communicates image data via a public line or local area network; and 206 is, for example, a laser beam irradiated onto a photoreceptor to form a latent image, which is This is an image output unit such as a laser beam printer that creates a visible image. Note that the image output unit 206 may be an inkjet printer, a thermal transfer printer, a dot printer, or the like.

As described above, this embodiment uses an image memory that compresses and stores continuous tone data such as image data using the correlation between pixels and visual characteristics, and a text color (drawing color) or background color for each specific area. By providing a gradation memory for storing the dot resolution of pixel data and a resolution memory for storing the dot resolution of pixel data, and switching the output data of the image memory and gradation memory according to the output signal of the resolution memory, the image quality of both text and images can be improved. The aim is to reduce memory capacity while maintaining good performance.

<Second Embodiment> FIG. 9 is a block diagram showing the configuration of an image processing apparatus according to a second embodiment of the present invention. In the figure, components that perform the same functions as those in FIG. 1 are given the same symbols, and only points different from the embodiment in FIG. 1 will be described below.

In the figure, 2 is a data identification circuit. The header information of the data input from the input terminal 1 is interpreted by the data identification circuit 44, the resolution data for background identification is stored in the resolution memory 3, and the background color and drawing color in the image area are stored in the gradation memory. 4, the text drawing color and image data are each stored in the gradation memory 52. Each of the above memories 3.4.5
When data for one page is transferred to 2 and the printer engine is started, data corresponding to each pixel of the page is sequentially transferred from the resolution memory 3 and gradation memories 4 and 52 according to the synchronization signal from the first pixel of the page. are supplied to the control terminal, terminal a, and terminal S of the selector 6, respectively. The selector 6 switches the background color output from the gradation memory 4 and the text drawing color and image data from the gradation memory 52 in accordance with the output signal of the resolution memory 3, and sends the gradation to the printer engine from the output terminal 7. Outputs key data.

This embodiment is configured so that the resolution of the background portion is preserved. Since the number of background colors in one page is usually very small compared to the number of text drawing colors, the hardware amount of the gradation memory 4 can be made quite small. In addition, in the case where the drawing color of text changes continuously (for example, when the gradation and coordinates of characters are overwritten by shifting them little by little), in the first embodiment, in reality, pseudo-coloring such as dithering Although gradation processing is required, in this embodiment, the gradation memory 5 is advantageous for storing continuous gradations.
By storing the drawing color in , very good image quality can be obtained. Furthermore, since this embodiment is configured to preserve the resolution of the background portion, it is possible to easily trim the image portion at the highest resolution of the printer.

<Third Embodiment> FIG. 1O is a block diagram showing the configuration of an image processing storage device according to a third embodiment of the present invention. In the figure, components that perform the same functions as in Figure 1 are given the same reference numerals, and hereinafter,
Only the points different from the embodiment shown in FIG. 1 will be explained.

In the figure, 44 is a data identification circuit, 45 is an area determination circuit, and 4
6 is an EXOR circuit.

The data input from the input terminal 1 is sent to the data identification circuit 4.
The header information is interpreted in step 4, and the bitmap data of the background part is stored in the resolution memory 3, the background color and drawing color in the image area are stored in the gradation memory 4, and the drawing color and image data of the text are stored in the gradation memory 52. Each is stored. Also,
The image area is stored in a register of the area determination circuit 45. When one page of data is transferred from the host computer to each of the memories 3, 4, 52 and the printer engine is started, the page is transferred from the resolution memory 3, gradation memory 4, 52 and area determination circuit 45. Data corresponding to each pixel is sequentially output from the first pixel. The area determination circuit 45 supplies "1" to one terminal of the EXOR circuit 46 when the current pixel is image data. The output of the resolution memory 3 is connected to the other terminal of the EXOR circuit 46,
With the above configuration, the resolution data within the image area is inverted. Therefore, in the case of text pixels in the background and image areas, the selector 6 selects the gradation (color) data from the terminal a, that is, the gradation memory 4; in other cases, the selector 6 selects the gradation (color) data from the terminal b1, that is, the gradation memory 50. is output from terminal C, and the selected gradation data is supplied from output terminal 7 to the printer engine.

In this embodiment, since the contents of the resolution memory are inverted in the image portion, text data can be easily overwritten. That is, in the second embodiment, the host computer processes the text data to be overwritten on the image portion as background data. That is, it is necessary to store "l" in the resolution memory 3 only for the image part where text is not overwritten and the text drawing part outside the image area, and "0" for the other parts, but in this embodiment,
In order to invert the output of the resolution memory 3 within the image area, it is sufficient to always set the text drawing section to "1" regardless of whether it is inside or outside the image area.

In addition, in the first to third embodiments, the resolution memory was configured with 1 bit for each pixel, but the present invention is not limited to this.
For example, a configuration may be adopted in which gradation data is selected from four types of gradation memories for each pixel with 2 bits.

〔Effect of the invention〕

As described above, according to the image processing apparatus of the present invention, it is possible to obtain an image containing both text and images with good quality with a small memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a specific configuration example of a gradation memory. Figure 3 is a diagram showing a specific configuration example of a compression circuit. Figure 4 shows a specific example of the configuration of a predictive coding circuit (DPCM). Figure 5 shows the scan order of DCT coefficients. Figure 6 shows a specific example of the configuration of the second gradation memory. The figure shows a specific example of the configuration of the area determination circuit. FIG. 8 shows the effective area of the gradation memory on a page. FIG. 9 is a block diagram showing the configuration of the second embodiment of the present invention. 11 is a block diagram showing a configuration of a third embodiment of the present invention. FIG. 11 is a block diagram showing a specific configuration example of a third gradation memory. FIG. 12 is a block diagram showing another specific configuration example of a resolution memory. ,
44. 50...Data identification circuit 3...Resolution memory 4, 51. 52...Gradation memory 6.53...Selector 45...Area determination circuit 46...EXOR circuit l Fig. 6-'' Fig. 5(E)) 11th function r' Fig. 12

Claims (12)

[Claims] (1) It has a plurality of gradation information storage means for storing gradation information and a resolution information storage means for storing resolution information, and the resolution information stored in the resolution information storage means An image processing apparatus characterized in that the plurality of gradation information storage means described above are selectively used. (2) The image processing apparatus according to claim 1, wherein at least one of the plurality of tone information storage means compresses and stores tone information. (3) The image processing apparatus according to claim 2, wherein discrete cosine transformation and variable length coding are used to compress the gradation information. (4) At least one of the gradation information storage means,
3. The image processing apparatus according to claim 2, further comprising specifying means for specifying a specific area on one screen, and storing gradation information for each specific area. (5) The specifying means is based on the coordinates (x_0, y_0) of the pixel scanned first in the area expressed by the rectangle and the coordinates (x, y) of the pixel scanned last in the area. The image processing apparatus according to claim 4, wherein the image processing apparatus is determined to be within the area if the coordinates (x, y) of the pixel being scanned satisfy x_0≦x≦x_1 and y_0≦y≦y_1. . (6) The image processing apparatus according to claim 4, wherein the specifying means validates the last set area in a portion where the specific areas overlap. (7) At least one of the gradation information storage means,
3. The image processing apparatus according to claim 2, wherein gradation information is stored for every n pixels×m lines (m and n are integers of 2 or more). (8) The gradation information storage means includes a gradation memory for storing a background color and a gradation memory for compressing and storing gradation data of image data and text data, and the resolution information storage means 2. The image according to claim 1, further comprising a resolution memory for storing a signal for identifying a background portion, and selectively using the gradation memory according to an identification signal of the resolution memory. Processing equipment. (9) The image processing apparatus according to claim 8, further comprising means for identifying an image area, and inverting the identification signal of the resolution memory within the image area. (10) The image processing apparatus according to claim 1, wherein the resolution information stored in the resolution information storage means is compressed and stored by lossless encoding. (11) The image processing apparatus according to claim 8, further comprising means for detecting the amount of the image data, and changing the compression ratio of the compression circuit depending on the amount of data. (12) Gradation memory that stores the gradation of text data;
It has a gradation memory for compressing and storing image data, a gradation memory for storing a background color, a resolution memory for storing a signal for identifying text data (drawing pixels), and an identification means for identifying an image area. The output of the gradation memory for image data is selected within the image area identified by the image area identifying means, and the output of the gradation memory for storing the background color is selected outside the image area. An image processing apparatus characterized in that the gradation data outputted from the gradation memory storing the gradation of the text data is switched in accordance with a signal from the resolution memory.