JPH0488669A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain hot carriers to meet the demands of a MOS transistor and to enable an element to operate at a higher speed by a method wherein two or more MOS transistors of different kinds where the offset regions of diffusion layers of DD structure are different from each other in impurity concentration are provided onto a semiconductor substrate. CONSTITUTION:A first-a third MOS transistor, Tr3-Tr5, are formed on three element forming regions surrounded with a selective oxide film 2 on a P-type silicon substrate 1. Tr3 is used in one of semiconductor circuits formed on the substrate 1 which is required to be high in breakdown strength and long in service life, and Tr3 us provided with a gate electrode 3b formed through the intermediary of a gate oxide film 3a and a diffusion layer 6. Tr4 is used in one of semiconductor circuits formed on the substrate 1 which is required to operate at a high speed, and Tr4 is provided with a gate electrode 4b formed through the intermediary of a gate insulating film 4a and a diffusion layer 7 of LLD structure. Tr5 is used in one of semiconductor circuits formed on the substrate 1 which is not required to be high in operation speed and breakdown strength, and Tr5 is provided with nearly the same structure with the transistors Tr3 and Tr4. By this setup, hot carriers can be restrained so as to meet the demands of transistors and an element can be made to operate at a higher speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device equipped with a plurality of MOS transistors having a diffusion layer of an LDD structure, MOS! -Aiming at suppressing the deterioration of the transistor and increasing the speed according to the performance requirements of the element, the structure includes two or more types of MO3I-transistors with different impurity concentrations in the offset region in the diffusion layer of the LDD III structure. do.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device equipped with a plurality of MOS transistors having a diffusion layer of an LDD structure. LDD (lightly dop) is adopted to prevent deterioration of mutual conductance.
The (ed drain) diffusion layer has a structure in which a low concentration diffusion layer (offset a region) 63 is formed on the side of the high concentration diffusion layer 62 near the gate electrode 61, as shown in FIG. .

By the way, MOS transistors are formed on the same semiconductor substrate 60.
When forming multiple MOS transistors on the top, other MOS
The impurity concentration of the offset region 63 of the S transistors T2, T, is set.

[Means to solve the problem]

The problem mentioned above is the offset region 6b in the diffusion layer of the LDD structure, as illustrated in FIG.

2 or more types of MOS with different impurity concentrations of 7b and 8b)
This is achieved by a semiconductor device characterized in that transistors 3 to 5 are provided on a semiconductor substrate 1.

[Problem to be solved by the invention]

However, according to such a structure, since the impurity concentration of all the offset regions 63 is low, the drain current of the transistor T (MOS) which requires high speed is small (which becomes an obstacle to high speed). There are some inconveniences.

The present invention has been made in view of these problems, and provides a semiconductor device that can suppress element deterioration due to the hot carrier effect and can increase speed in response to the performance requirements of MOS transistors. The purpose is to

[For production]

According to the present invention, two or more types of MOS transistors 3 to 5 having different impurity concentrations in the offset regions 6b, 7b, and 8b in the LDDI diffusion layer are provided on the semiconductor substrate 1.

Therefore, by analyzing the semiconductor circuit formed on the semiconductor substrate 1 in advance, grasping the operating state of the MOS transistors therein, and setting the impurity concentration of the offset region to the optimum value for each MOS transistor, each MO9) This makes it possible to suppress hot carriers and increase the speed of devices in accordance with the requirements of

For example, the most frequently used MOS) transistor LD
The impurity concentration of the offset region of the D structure diffusion layer is
If it is made smaller than the offset area of the OS transistor,
The withstand voltage increases, deterioration caused by hot carriers is reduced, and the lifespan is extended.

〔Example〕

Therefore, the details of the present invention will be explained below based on the drawings.

Figure 3 is a sectional view showing one embodiment of the present invention,
A selective oxide film 2 is formed on the surface of the mold silicon substrate 10,
Further, in the three element forming regions surrounded by the selective oxide film 2, transistors 3 to 30 (1 to 30M05), which will be described later, are formed, respectively.

The first (DMO3) transistor 3 is used in a part of a semiconductor circuit formed on a silicon substrate 1 that requires high voltage resistance and long life, such as an input/output driver or a transfer gate of a memory cell. Substrate I
Gate oxidation IP on top! ! The diffusion 116 consists of an n-type layer 116a and an n-type layer extending toward the gate electrode 3b on the side thereof. (offset SJf region) 6b, and is configured to suppress the hot electron effect.

The n-type layer 6a has an implantation energy of 1ookeV,
Arsenic ions are implanted and diffused at a dose of I x I 01 S/cd or more, and the n-type layer 6b is implanted at a dose of I x 10'' at the same energy.
Phosphorous ions are implanted under conditions of approximately /c-j and then diffused.

The second MOS) transistor 4 is used in a part of the semiconductor circuit that requires high speed.
) The transistor 4 is composed of a gate electrode 4b formed on a gate insulator 114a and an LDD structure diffusion layer 7 formed on both sides of the gate electrode 4b in the silicon substrate 1. One of the diffusion layers 7 is a source layer and the other is a source layer. Used as a drain layer.

In this case, the n0 type layer 7a constituting the diffusion layer 7 is 100%
keV implantation energy, dose I x 10 ”/
Arsenic ions are implanted and diffused under the conditions of c-2 or higher, and the n-type N (offset region) 7b is
3×1O13~IX at 100keV implant energy
Phosphorous ions are implanted and diffused at a dose of IOIs/cd, and the concentration is higher than that of the n-type layer 6b of the first MOS transistor 3.

The third MOS transistor 5 is used in a part of the semiconductor circuit formed on the silicon substrate that does not particularly require high voltage resistance or high speed, and is almost similar to the MOS transistor 3.4 in the 1.2. structure, and the diffusion layer 8
The n-type layer (offset region) 8b is implanted with an implantation energy of 100 keV and a dose of lXl013 to IXI'
The difference is that phosphorus ions are implanted under the condition of 0''/cd.

8a indicates an n-type layer.

In the figure, reference numeral 10 indicates a glabellar insulating film that covers the MOS transistors 3 to 5, and 11 to 16 indicate electrodes connected to each diffusion layer 6 to 8 through contact holes 17 to 21 of the glabellar insulating film 10. .

Next, the operation of the above embodiment will be explained.

MOS transistors 3 to 5 have an n-type layer 6b with an LDD structure.
, 7b, and 8b have different drain currents and lifetimes.For example, the dose/drain current characteristics shown in Figure 2(a) and the dose/lifespans shown in Figure 2(b) differ. characteristics are obtained.

Therefore, when the carrier movement direction is bidirectional in the diffusion layer of the transistor, as in a transfer gate, and the transistor is used under conditions of high frequency of use, the first MOS transistor 3 with a low impurity concentration in the offset region is
By using this, the withstand voltage of the diffusion layer 6 is increased, damage caused by hot carriers is suppressed, and the life is extended.

Further, according to the second MOS transistor 4, since the impurity concentration of the offset region 7b is relatively high, the first Iy
) MOS) The drain current is larger than that of the transistor 3, and the speed of the semiconductor circuit can be increased. In this case, as shown in FIG. 2(b), the life of the first MOS is shortened, but
When used less frequently than the transistor 3 or when the load is small, the deterioration life can be made approximately the same as that of the first MOS transistor 3.

Furthermore, according to the third MOS transistor 5, the dose of the n-type layer 8b is the same as that of the other two MOS transistors 3.
Since this value is between the values of 4 and 4, it is possible to obtain characteristics that are approximately intermediate between those transistors in terms of drain current and lifetime.

Next, the above-mentioned first to third MOS transistors 3 to
The formation process No. 5 will be briefly explained based on FIG. 3.

First, the n'' type layers of the diffusion layers 6 to 8 in the first to third MOS transistors 3 to 5 are formed, and the amount of impurity ions implanted therein is determined based on the characteristics shown in FIG. Ru.

In other words, the relationship between the gate-source voltage vo and the drain-source voltage ■□ of a MOS transistor has the characteristics shown in the solid line, -dot-dashed line, and two-dot-dashed line shown in Figure 4, depending on the load. It will be done. The characteristic shown by the solid line indicates the case where there is almost no load capacity, and as the load capacity increases, the loop characteristic becomes such that the loops of the dashed line and the dashed double dot line become wider.

Also, the drain-source voltage V. , and the substrate current per gate width I, , , /W, an equilinear line as shown by the broken line in FIG. 4 is obtained, and the drain and source voltages . , the higher is the equiline of the substrate current 1--b/W.

By the way, in addition to the fact that the amount of hot carriers generated increases as the substrate current r-h/W increases, as shown in FIG. is known to increase.

As a result, as the load capacity increases, the amount of hot carriers generated also increases, so the impurity concentration of the n-type layer must be limited in order to suppress hot carriers.

In this way, when determining the dose of the n-type layer, consider the relationship between the load characteristics and the substrate current (Figure 4), and the relationship between the substrate current and the dose of the n-layer (Figure 5). It is necessary to determine the upper limit of impurity concentration.

Therefore, when determining the dose of the n-type layer 6b of the diffusion layer 6 of the first MOS transistor 3, a value smaller than the upper limit is selected to optimize the dose, while the second In the case of the MOS l-transistor 4, the upper limit value of the dose amount is directly selected to determine the amount. Further, in the case of the third MOS transistor 5, an intermediate value between them is used.

After determining the dose of the n-type layers 6b, 7b, 8b of each MO5) transistor 3 to 5 as described above, ions are implanted into the offset HN region according to the determined dose.

Therefore, with the gate electrode formed (Fig. 3(a))
, phosphorus ions are implanted into the region where the first MOS transistor is formed under conditions of an implantation energy of 100 keV and a dose of approximately IXIQ13/cd, thereby forming the gate electrode 3b and the selective oxide film 2.
The first n- ion implantation layer 3 is self-aligned using the mask as a mask.
form 0. In this case, the other element forming regions are covered with a photoresist 25 [FIG. 3(a)].

Next, after the photoresist 25 is ashed, a photoresist 26 is applied again, exposed and developed, and the third MO
A window is formed to expose the S transistor formation region. Then, a relatively high dose amount, which is the limit value for preventing deterioration due to hot carriers, for example, 3X10''~lXl0''
/cd, phosphorus ions are injected into the second MOS l-transistor formation region, and the silicon substrate l on the j# side of the gate electrode 4b is implanted.
A second n-ion implantation layer 31 is provided on the surface layer, and then,
The photoresist 26 is removed (FIG. 3(b)).

Furthermore, after the photoresist 26 is removed, a new photoresist 27 is applied, exposed and developed to form a window exposing the second MOS transistor formation region. Then, the predetermined l x 10 ls
〜I (Fig. 3(C)).

Next, the film thickness is about 400n- (DSiOtl133
(FIG. 3(d)), this is etched using a reactive ion etching method to form sidewalls 34 to 34 on the side walls of each gate electrode 3b, 4b, and 5b.
36 (Figure 3(e)).

Next, arsenic ions are implanted into the entire area under the conditions of a dose of 1 x 101 S/Cd or more and an implantation energy of 100 keV, and the gate electrode 3 of the three MOS transistor formation regions is implanted.
b, 4b, 5b and the side walls 34 to 36 as masks, the first silicon base [1] on both sides is self-aligned.
-3 n' ion implantation layers 37 to 39 are formed.

Then, after this, three MOS) n- ion implantation layers 30 to 32 and n ion implantation layers 37 to 32 of the transistor formation region are formed.
39 is annealed and activated, and the n-type layers 6a, 7a, 8a of the diffusion layers 6-8 of each transistor 3-5 and the n-type layer 6 are activated.
b, 7b, 8b) (FIG. 3(f)), and then a glabellar insulating film 10. Contact holes 17-22 and electrode 1
By sequentially forming elements 1 to 16, a device as shown in FIG. 1 is formed.

[Effects of the Invention] As described above, according to the present invention, two or more types of MOS transistors having different impurity concentrations in the offset regions in the diffusion layer of the LDD structure are provided on the semiconductor substrate. Analyze the semiconductor circuit, understand the operating status of the MOS1 transistors in it, and analyze each MO3)
By setting the impurity concentration in the offset region to an optimum value for each transistor, it is possible to suppress hot carriers and increase the speed of the device according to the requirements of each MOS transistor.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention.
Offset dose and drain current. Figure 4 is a sectional view showing an example of the formation process of a device according to an embodiment of the present invention. FIG. 5 is a characteristic diagram showing an example of the relationship between source voltage and gate-source voltage, and drain-source voltage and substrate current. FIG. 5 is a characteristic diagram showing an example of the relationship between offset dose amount and substrate current. The figure is a sectional view showing an example of a conventional device. (Explanation of symbols) 1...Silicon substrate (semiconductor substrate), 2...Selective oxide film, 3.4.5...MOS transistor, 3a, 4a, 5
a... Gate insulating film, 3b, 4b, 5b... Gate electrode, 6.7.8... Diffusion layer, 6a, 7a, 8a---n-type layer (offset region), 6b, 7b , 8b-n” type layer. Applicant: Fujitsu Limited

Claims (2)

[Claims] (1) A semiconductor device characterized in that two or more types of MOS transistors having different impurity concentrations in offset regions in a diffusion layer of an LDD structure are provided on a semiconductor substrate. (2) In a semiconductor device equipped with a plurality of MOS transistors having a diffusion layer of an LDD structure, the impurity concentration of the offset region of the diffusion layer of the LDD structure constituting the MOS transistor that should be used more frequently is compared to that of other MOS transistors. A semiconductor device characterized in that the offset region of the diffusion layer is smaller than the offset region of the diffusion layer.