JPH0488535A - Memory mapping method for shared memory and multi-cpu system - Google Patents

Abstract

PURPOSE:To improve the throughput of data transfer between CPUs by dynamically setting the size of address space usable in an inter-CPU communication area corresponding to the amount of transfer of data. CONSTITUTION:When a write access request is issued from an execution unit 150, an access controller 160 outputs the write access request to shared memory 4. Also, an access address A is inputted to an address conversion mechanism 120 and an address comparison mechanism 130. The comparator 130 compares the boundary value address AO of an address storage mechanism 140 with the address A. When it is A<AO, the address A is outputted as a bit-expanded address AC to the shared memory 4 as it is. When it is A>=AO, an address AC=A+AS in which an offset value AS is added on the access address A is outputted to the shared memory 4 as an output address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory mapping method for shared memory, and in particular to a shared memory mapping method that is suitable for a multi-CPU system composed of CPUs with different address reaches for the shared memory. Regarding the mapping method.

[Prior Art] One means of inter-CPU communication in a multi-CPU system is to use a shared memory, and communication is performed in such a way that data written by one CPU to the shared memory is read by another CPU. It will be done. In such a system, when CPUs with different address reaches are used, shared memory mapping as shown in FIG. 2 has been performed. (HARDWARE MANIJ
AL HIDTC805erieS”0ctiver,
1983. In other words, three CPUs are currently in use, and the address reach for the shared memory of CPUI, 2 is 512KB (kilobytes), and C
Assume that the address reach of PU3 is 4MB (megabytes). Then, the address of each CPU is I of the shared memory.
The addresses from the IOIT address to addresses accessible by the CPU are mapped. Therefore, in this case, there are three C
As shown in the common part of Figure 2 (a), the common mapping area for PUs is 542KB from addresses 0" to "0007FFFF (hexadecimal)"3, of which all CPs
Assuming that the capacity required for control between U is 256 KB, the remaining 256 KB is divided and used as an area for data transfer between CPU'1 and 3, and between CPU 2 and 3. Figure 2 (b)
3 shows how 128 KB is allocated to each of these.3 [Problems to be Solved by the Invention] In the above-mentioned conventional technology, when communicating between CPUs via a shared memory, the CPU with a small address reach However, only a small communication area can be used, and the more CPUs with small address reach, the more
There was a problem in that the usable area for U became smaller and data transfer efficiency deteriorated.

It is an object of the present invention to provide a shared memory memory mapping method that can improve the communication throughput of the CPUs by expanding the communication area between a CPU with a small address reach and a CPU with a large address reach. is to provide.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an address space for a shared memory of a CPU with a small address reach by dividing the address space into first and second addresses at a preset boundary value address.
Each CPU is divided into areas, and each CPU is provided with an address conversion means for accessing the shared memory from each CPU.
When the access address to the shared memory from is in the first area, it is allocated to a common shared memory area for all CPUs, and when it is in the second area, it is allocated to a different shared memory area among the CPUs with the corresponding small address reach. can be assigned.

[Operation] When accessing the shared memory from CPtJ with a small address reach, the conversion means compares the access address with a preset boundary value address and determines which area of the address space of the shared memory it corresponds to. As a result, the second
If it is in the area, the shared memory 1 is converted to the physical address of the area on the shared memory predetermined for the CPU.
Click j. Therefore, CP with small address reach
The area on the shared memory corresponding to the second area of U can be set as a separate area for each CPU, and there is no need to divide and use one area among CPUs with small address reach. On the other hand, since a large area of the shared memory is mapped to the address of the CPU with a large address reach, each CPU with a small address reach
Each area on the above shared memory corresponding to the second area of U is
It can be distributed and arranged on the mapping area of the CPU with a large address reach. Therefore, CP with small address reach
For communication between each U and the CPU with large address reach, an area on the shared memory corresponding to the entire second area of the CPU with small address reach can be used, and in the conventional method, this area is further divided. Communication throughput is significantly improved.

[Example] The present invention will be explained in detail below using examples.

FIG. 3 shows an example of the configuration of a multi-CPU system to which the method of the present invention is applied. CPUI, 2 is sensor 5.
6 is read through the signal line 51.61, and the data is temporarily stored in the shared memory (GM) 4 through the interface 50.60. Data transfer is performed by the CPU 3 reading the data via the interface 70.

Here, CPUI2 is a CPU with a small bearish reach compared to CPU3.

Figure 1 shows Figure 3 (7) CPUI (or CPL'2)
1 is a block diagram illustrating one embodiment of an execution unit (EU).
150, a basic processing unit (BPU) 155, a private memory (PM) 154, a bus controller (BC) 1
57, Input/output processor (Engineering ○P) 156, Internal bus 1
It consists of 58 parts. Shared Memory Attachment (GMP) 1
00 is the boundary value address storage mechanism (
FENCE) 140, comparator (CMP) 130, address translation mechanism 120, shared memory access controller (
CNT) 160.

The operation of this embodiment will be explained below. First, execution unit 15
When the access controller 160 issues a write access request to the shared memory 4 via the signal line 502, the access controller 160 issues a write access request to the shared memory 4 via the signal line 502. Also,
The access address A is input to the address translation mechanism 120 and the comparator 130 via the address bus 151, and the comparator 130 receives the boundary value address A of the address storage mechanism 140.
Compare O and access address A. As a result, if A<AO, the comparator output is turned off, and at this time, the address translation mechanism 120 adds the necessary number of bits II Oj + bits to the upper part of the input access address A, making it the address AC that is bit-extended. (to the number of digits required for all addresses in the shared memory) and outputs it to the shared memory 4 via the bus 501. On the other hand, when A≧AO1, that is, when the access address A is a boundary value address storage mechanism, the comparator 130 output is turned on, and the address translation mechanism 120
is AC=A+A, which is obtained by adding the offset value AS as conversion information stored in the storage mechanism 110 to the access address A.
S is output to the shared memory 4 as an output address. When the address is sent to the shared memory 4 in this way, the access controller 160 requests the execution unit 150 to send write data via the signal line 153, and sends the write data to the shared memory 4 via the data bus 152 and bus 501. Output write data. When the write access ends in this way, the controller 160 sends a write access end report to the execution unit 150 via the signal line 153.

The same is true for read access from the execution unit, sending a read access request to shared memory 4, comparing access address A with boundary value address AO, and determining whether AHAO or A
The address translation mechanism operates depending on whether ≧AO or not, and its output address AC is sent to the shared memory. In the case of read access, read data is output from the shared memory 4 by sending this address AC, and it is transferred to the bus 501.
．． 152, the controller 160 reports the completion of the read access to the execution unit 150 via the signal line 153.

FIG. 4 shows an example of mapping by the above operation. As in the case of the conventional example (Fig. 2), the CPU,
The address reach for the shared memory of 2 is 512KB,
It is assumed that the address reach of CPU3 is 4MB and the shared memory capacity required for control among all CPUs is 256KB. At this time, the boundary value address AO of the storage mechanism 140 in FIG. AS="000
3FFFF (hexadecimal)''. Then, C
When the access address A of both PUI and 2 is A<AO, A is taken as the address AC of the shared memory, so AO="0O03F from #OIT of the shared memory.
The common area corresponding to "FFF" L, - is accessed. This is an area necessary for the control between the CPtJs described above. On the other hand, if the access address A is "0O07FFFF"≧A≧
When it is AO, it is mapped directly to the shared memory in CPUUI, and in CPU2 it is mapped as AC:A+AS, "0007F.
F F F ”≦AC≦” 0008 F F F F
” Since it is mapped to the address AC, the CPU
The area for data transfer between I and CPU3 is also between CPU2 and CPU
The same area between U5 can also be secured to 256 KB, and the dedicated area for data transfer is doubled compared to the case of FIG. 2 using the conventional method.

FIG. 5 shows another embodiment of the invention.

In the embodiment of FIG. 1, the boundary value address AO and address translation information A stored in storage mechanisms 140 and 120
S was a fixed value. In this case, when transferring data that exceeds the capacity of the secured data transfer area,
Until the data transfer between the PUI or 2 and the CPU 3 is completed, it is not possible to write the data in the data transfer area, and it is necessary to temporarily interrupt the transfer. In this embodiment, boundary value address AO and address conversion information A
This problem was solved by making S rewritable. To this end, a signal line 161 for rewriting the address conversion information of the storage mechanism 110 from the access controller 160 and a signal line 162 for rewriting the boundary value address of the storage mechanism 140 are added to the configuration shown in FIG. .

In the configuration shown in FIG. 5, when a request to change address translation information is issued from the execution unit 150 via the signal line 153, the controller 160 turns on the signal on the signal line 161, and transfers the data bus 152 from the execution unit 150 to the data bus 152. The new address translation information is stored in the storage mechanism 110.
write to.

Further, when a boundary value address change request is issued from the execution unit 150 via the signal line 153, the controller 1
60 turns on the signal on the signal line 162, and the execution unit 1
The new boundary value address bussed from 50 onto data bus 152 is written to storage 140.

According to this embodiment, by making it possible to change the address reach division position for the shared memory and the mapping position of the divided address space on the shared memory, efficient mapping can be achieved with dynamic mapping according to the amount of transferred data. Transfers can be made.

In addition, although the above embodiment described the case of a multi-CPU system with three units, it is clear that the present invention can be implemented not only with three units.

[Effects of the Invention] According to the present invention, in a multi-CPU system made up of CPUs with different address reaches, the address space that can be used for the communication area between the CPUs can be expanded more than before, and the data Since the size of the space can be dynamically set according to the amount of transfer, it is possible to improve the throughput of data transfer between CPUs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a CPU that implements the method of the present invention, FIG. 2 is a diagram showing an example of conventional mapping,
Figure 3 is a diagram showing an example of the configuration of a multi-CPU system;
This figure shows an example of mapping of a shared memory address space when the present invention is used, and FIG. 5 is a block diagram showing another embodiment of the present invention. 1 to 3...CPU, 4...Shared memory device, 110...
・Address translation information storage mechanism, 120...Address translation mechanism, address comparator, 140・Boundary value address storage mechanism.

Claims (1)

[Claims] 1. A shared memory, at least one large CPU having an address reach that can access all areas of the shared memory, and an address necessary to access all areas of the shared memory. In a memory mapping method for a shared memory in a multi-CPU system equipped with a plurality of small CPUs having no reach, the small CPU
a first means for storing a boundary value address for dividing an address space for the shared memory of the CPU into first and second spaces in each of the CPUs; and a first means for storing a boundary value address and an access address to the shared memory in each of the CPUs; and third means for converting the access address according to the determination result of the means. A memory mapping method for a shared memory, characterized in that access from the small CPU to the shared memory is performed using an address generated by the third means. 2. The shared memory memory mapping method according to claim 1, wherein the boundary value address of the first means can be rewritten by an execution unit of the small CPU. 3. The shared memory memory mapping method according to claim 1 or 2, wherein the access address conversion method by the third means can be rewritten from an execution unit of the small CPU. 4. The sharing device according to claim 1 or 3, wherein the third means comprises a storage means for storing an offset address, and an address addition means for adding the offset address and the access address and outputting the result. Memory mapping method for memory. 5. A shared memory, at least one large CPU that has an address reach that can access all areas of the shared memory, and a CPU that does not have the address reach necessary to access all areas of the shared memory. In a multi-CPU system including a plurality of small CPUs, each of the small CPUs has a first memory that stores a boundary value address for dividing the address space for the shared memory of the CPU into first and second spaces. means for comparing the boundary value address and the access address to the shared memory to determine whether the access address is in the first or second space; and address conversion means for converting the access address according to the determination result and generating an address for accessing the shared memory.
PU system.