JPH0488445A - Program memory switching circuit - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a memory by assigning the program address area of a microprocessor specifically to specific program memory addresses. CONSTITUTION:The switching signal of the address area of a program memory 5 are brought under the gate control of gate circuits 2 and 3 with the most significant digit bit of the address bus of the microprocessor 1. Consequently, when the program address of the microprocessor 1 enters a specific area including an interruption process start address, the address area of a specific program memory 5 is accessed. For the purpose, the most significant digit bit of the access bus of the microprogram 1 is operated to execute the program in the specific program area regardless of whether or not the address area is switched. Consequently, an interruption processing program can be stored only in a specific area at one place and the use efficiency of the memory is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a program memory switching circuit for expanding a program memory in a microprocessor to a capacity larger than the memory space originally possessed by the microprocessor.

(Prior Art) FIG. 2 is a circuit diagram of a conventional example. This conventional example is an example of an expansion circuit for the program memory 25 in the microprocessor 21.

The illustrated circuit consists of a microprocessor 1, an address latch circuit 4, and a program memory 5.

Microprocessor 1 has a 16-bit memory address. This microprocessor 1 outputs a memory bank switching signal 11, an address latch signal 9, and a program memory read signal 10.

Address latch circuit 4 separates the microprocessor address from the time-shared address data bus.

Program memory 5 is 128 bytes of memory.

P2.7 to P2.0 of the microprocessor 1 output the upper eight bits (A15-P-A8-P) of the memory address and are connected to addresses A15 to A8 of the program memory. PO17 to PO of microprocessor 1
40 is the lower 8 bits of the memory address (A7-P-AO
-P) and inputs memory data, and is a time-division address data bus that outputs inputs ID to 8D of the address latch circuit 4 and outputs 07 of the program memory 5.
~oo is connected.

Outputs IQ to 8Q of the address latch circuit 4 are connected to A7 to AO of the program memory 5, and provide program addresses A7-P to AO-P of the microprocessor 1 to the program memory 5. The address latch signal (ALE-P) 9 output from the microprocessor 1 is the time-sharing address data bus PO1
It is a signal that outputs an active high pulse indicating that an address is being output to 7 to P0.0, and is connected to the latch enable terminal EN-N of the address latch circuit 4. Read signal (PSEN-N) 10 indicates that the microprocessor 1 uses the time-sharing address data buses PO17 to P
This is a signal that outputs an active low pulse indicating the timing to take in program data from 0.0, and is connected to the output enable terminals 0E-N of the program memory 5. Pl,7 to P1.0 of the microprocessor 1 are general-purpose output ports, and only Pl,0 is connected to address A16 of the program memory.

FIG. 3 is a diagram showing a conventional program memory map. Program memory 5 is 128 bytes and 6
It is divided into 4 byte BANK O and BANK 1. Each program BANK is a microprocessor
The maximum address width of 64 corresponds to a byte address. Here, microprocessor 1 selects BANK O
Whether to select BANK 1 or BANK 1 is instructed to the program memory 5 by setting the value of 0-N to 0 or 1 in the bank switching signal PB.

The procedure for reading program data from the program memory 5 by the microprocessor 1 is as follows. First, the microprocessor 1 sets the PBKO-N signal to O or 1 to select a program bank. Next, the microprocessor 1 performs P2,7~P2.0 and PO37~
The program address to be read is output to PO10. At this time, an active bipulse is simultaneously output to ALE-P, 9, and the lower 8 bits of the address are latched by the address latch circuit 4 and given to the program memory 5.

Next, when the microprocessor 1 sets PSEN-N and 10 to low level, the program memory 5 outputs the data at the specified address of the specified bank from 07 to OO, and transfers this program data to the microprocessor 1.
is input from PO17 to PO30, PSEN-N, 1
The program data read cycle is completed by returning the 0 signal to high level.

(Problems to be Solved by the Invention) However, the circuit with the above configuration has the following problems.

That is, when an interrupt process occurs, the program of the microprocessor 1 automatically starts processing from a predetermined program address, so it is not possible to switch to the program BAN. Therefore, the same interrupt processing program must be loaded into all program BANs.

For this reason, there was a problem that the program memory was used inefficiently.

The present invention has been made with attention to the above points, and by allocating the program address area of a specific microprocessor including the interrupt processing address to a specific program memory address, the interrupt processing program is consolidated in one place, and the memory It is an object of the present invention to provide a program memory switching circuit that improves usage efficiency.

(Means for Solving the Problems) The program memory switching circuit of the present invention uses a switching signal for an address area of a program memory of a microprocessor to
A gate circuit is provided that performs gate control using the most significant bit of the address bus of the microprocessor, and when the program address of the microprocessor enters a specific area that includes the interrupt processing start address, the control is performed without using the address area switching signal. This is characterized in that the address area of the specific program memory is accessed.

(Function) According to the program memory switching circuit of the present invention, the switching signal of the address area of the program memory is gate-controlled by the most significant bit of the address bus of the microprocessor. As a result, when the program address of the microprocessor enters a specific area including the interrupt processing start address, the address area of the specific program memory is accessed. Therefore, by manipulating the most significant bit of the address bus of the microprocessor, the program in the particular program area is executed regardless of whether or not the address area is switched. As a result, the interrupt processing program can be stored only in one specific area, and memory usage efficiency can be improved.

(Example) FIG. 1 is a circuit diagram of an embodiment of the present invention.

The illustrated circuit includes a microprocessor 1 and a gate circuit 2.
and 3, an address latch circuit 4, and a program memory 5.

The microprocessor 1 is similar to the conventional one shown in FIG. 2, and executes programs stored in a program memory 5 to perform various data processing and control. A memory bank switching signal (PBKO-N) 7 is output from the general-purpose output port P1.0 of the microprocessor 1.

In addition, the general-purpose output port P1.1 of the microprocessor 1
A memory bank switching signal (PBKI-N) 8 is output from the memory bank switching signal (PBKI-N).

Gate circuit 2 consists of an AND gate. Gate circuit 2
A memory bank switching signal 8 is input to one input terminal of the memory bank switching signal 8. The other input of the gate circuit 2 is the most significant bit (
Al5-P)6. On the other hand, the output terminal of the gate circuit 2 is connected to the address port A16 of the program memory 5.

The gate circuit 3 consists of an AND gate. Gate circuit 3
A memory bank switching signal 7 is input to one input terminal of the memory bank switching signal 7. The other input of the gate circuit 3 is the most significant bit (
A15-P) 6 is connected. On the other hand, the output terminal of the gate circuit 3 is connected to the address port A15 of the program memory 5.

The address latch circuit 4 is similar to the conventional one shown in FIG. 2, and separates the microprocessor address from the time-shared address data bus.

The program memory 5 is similar to the conventional one shown in FIG. 2, and stores programs to be executed by the microprocessor 1.

FIG. 4 is a diagram showing a program memory map in an embodiment of the present invention.

As shown, program memory 5 has 128 bytes. This program memory 5 consists of 32 bytes of 4
It is divided into two program banks.

BANKO corresponds to addresses 0000 to 7FFF of the program address of the microprocessor 1. Ban
KO is the most significant bit (A15-P) When 6 becomes O, bank switching signal (PBKI-N) 8 and (PBK
O-N) is selected regardless of the value of 7.

BANK 1.2.3 correspond to addresses 8000 to FFFF of the program address of the microprocessor 1, respectively. BANK 1.2.3 is selected by a combination of bank switching signals 8.7 when the most significant bit is "1". That is, the bank switching signal 8.7 is "0"
and "1", BANK 1 is selected. When the bank switching signal 8.7 is '1' and '0', the BAN
K2 is selected. When the bank switching signal 8.7 is "1" and "1", BANK3 is selected.

Here, setting the bank switching signals 8.7 to "0" at the same time is prohibited in terms of programming. Also, the start address of interrupt processing is program address 0.
It should be within the range 000 to 7FFF.

The procedure for specifying the program bank and reading memory is as follows.
This is essentially the same as the conventional example, but the difference from the conventional example is that the program bank designated by the states of bank switching signals 8 and 7 becomes valid only when the program address is 8000.
This is limited to the case of addresses ˜FFFF. When the program address is from 0000 to 7FFF, that is, when the most significant bit becomes "O", bank switching signals 8 and 7
are gate-controlled by gate circuits 2 and 3. As a result, addresses A15 and A1 of the program memory 5
6 are both O, and data is read from 0 to BAN regardless of the value of the bank switching signal 8.7.

Therefore, when an interrupt occurs and the program address automatically enters addresses 0000 to 7FFF, the BA
NKO will be accessed.

(Effects of the Invention) As explained above, according to the program memory switching circuit of the present invention, when an interrupt process occurs, a specific program bank is always selected regardless of the program bank specification. Therefore, there is no need to have multiple identical interrupt processing programs, and program memory usage efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional example, Fig. 3 is a diagram showing a conventional program memory map, and Fig. 4 is a diagram showing a program memory map in an embodiment of the present invention. FIG. 1...Microprocessor, 2.3...Gate circuit, 4...Address latch circuit, 5...Program memory. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] A gate circuit is provided for gate-controlling a switching signal for an address area of a program memory of a microprocessor using the most significant bit of an address bus of the microprocessor, and the program address of the microprocessor is set to an interrupt processing start address. 1. A program memory switching circuit characterized in that when a program memory enters a specific area containing a program memory, the address area of the program memory is accessed without using an address area switching signal.