JPH0488437A - Information processor - Google Patents

Abstract

PURPOSE:To speed up large-amount data access from an SVP to the main body of the information processor by scanning data in and out continuously between one buffer and the internal registers or flip-flop of the processor. CONSTITUTION:Buffers 15-0 and 15-1 are so controlled by a switching circuit 17 that one buffer is used for writing and the other is for reading; and data writing to the former and data reading from the other are performed in parallel. Further, a scan control circuit 3 has a function for continuous writing to the buffer 15-0 from the internal registers 4 - 6 and 8 or flip-flop of the processor by indicated word length or the reading from the read-only buffer 15-1 and continuous scan-in processing to the internal registers 4 - 6 and 8 or flip-flop of the processor by indicated word length according to the indication from the service processor (SVP). Consequently, the access from the SVP to the main device to which processors of the same constitution are connected is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention comprises a main unit in which a large number of processing devices of the same configuration are connected, such as parallel computers, and a service processor (hereinafter abbreviated as SvP) connected to the main unit. ).

[Conventional technology]

For maintenance, diagnosis, etc. of the main body of information processing equipment, Sv
It is common practice to provide a dedicated processor called P for processing. The method of providing SvP separately from the main body of a parallel computer is thought to be basically followed, but in the case of an information processing device such as a parallel computer in which many processing devices with the same configuration are connected, the configuration There are several problems caused by the above characteristics.

For example, if each processing device operates under microprogram control, it is necessary to load the microprogram as many times as there are processing devices when starting up the system, and the more devices there are, the longer it takes to load. There is a problem. Conventionally, this problem has been solved by making it possible to load microprograms into a plurality of processing devices at the same time, as described in Japanese Unexamined Patent Publication No. 63-78234.

If SvP processing is classified into write-type processing and read-type processing, it is possible to speed up write-type processing by using the simultaneous write method as in the example above, but read-type processing So, a method that can be called simultaneous reading cannot be adopted unless multiple SVPs are provided.
Also, no other speed-up methods are known.

For example, when reading out the internal states of a plurality of processing devices in the event of a failure, the procedure is as follows.

FIG. 3 is a diagram showing the overall configuration of an information processing device, where 20 is an svp, 21-O to 21-n are processing devices with the same configuration, and 1-0 to 1-n are for connecting these. This is the SvP interface unit (IF) of Figure 2 shows this SvP interface unit (
IF), 2 is a svp interface control circuit (SIFCNTL), 3 is a scan control circuit (SCAN CNTL), 4 is a command register (CMD) that gives commands to the scan control circuit, and 5 is a scan control circuit. 6 is an address register (SAR), 6 is a scan data register (SDR), and 7 is a selector.

The unit selection register (
USR) has a 1-bit storage area corresponding to each of the plurality of processing devices 2l-0=n.

The SvP interface unit includes 5VP20 and 5
They are connected by signal lines: an STRB line indicating the start of access from the VP 20, an RW line indicating write or read, a 5VPBUS for transmitting and receiving scan addresses and scan data, and an ACK line indicating the end of access.

The 5VP 20 first writes '1' to the bit position corresponding to the processing device in the unit selection register (USR) in the SvP interface control circuit 2 via the 5VPBUS in order to select the processing device to be accessed. That is, in order to access the processing device 121-0, '1' is written in the 0th bit of the unit selection register, and in order to access the processing device 21-1, gll is written in the 1st bit. From SvP to processing devices 21-0 to 21-
Access to n is made possible by writing '1' to the corresponding bit of this unit selection register USH.

When the svp reads the internal state of the processing device 21-O (held in internal registers and flip-flops within the processing device), the svp interface unit 1-O
0 and instructs the SvP interface control circuit 2 to start via the 5TRB line. Upon receiving the start instruction, the svp interface control circuit 2 selects 5VP.
20 receives the scan address of the internal register or flip-flop that it wishes to access via 5VPBUS, and writes it into the scan address register 5. In order to start up the scan control circuit 3, data '1' indicating scan out is written to the command register 4 from the 5VPBUS. Here, since SvP interfaces 1-1 to 1-n are not selected, writing to their registers 4 and 5 is not performed.

When activated, the scan control circuit 3 performs scan out based on the data in the command register 4. The SE line indicates that scan is valid, and the S line indicates whether the access for scan-in is for scan-out.
I line, and each scan control line and scan address (SA) line of the ST line, which instructs writing to internal registers or flip-flops of the processing unit, and scan-in data or scan-out data (DB
) line to read data from a desired internal register or flip-flop of the processing device 21-o and store it in the scan data register 6. After the storage in the scan data is completed, the svP interface control circuit 2 is permitted to release the 5VPBUS and enters a waiting state.

When the SvP interface circuit 2 receives permission to release the 5VPBUS, it returns an access end signal to the SVP 20 via the ACK line.

In the svp, the 5VPBtJS line is released, the scan data register 6 is read, and - times of main body accesses are completed.

To read the values of other internal registers or FFs of processing bag [21-0, store data "2" meaning scan in from SvP in command register 4, change the scan address, and perform the above procedure. Just repeat the steps. Furthermore, in order to read the internal state of the processing device 21-1,
After selecting the processing device 21-1, processing is performed in the same manner as the processing device 21-O. In this way, in order to read out the internal states of a plurality of processing devices, the processing devices are selected one after another and scan-out is repeated for each processing device.

[Problem to be solved by the invention]

In the above conventional technology, when attempting to read a large amount of data from multiple processing devices, it is necessary to select the processing devices one by one and repeatedly set the scan address and instruct the scan out for each of them. , and S
Since vP cannot perform effective processing until an access completion signal is returned after scanning, there is a problem in that it takes too much time.

For example, when hardware malfunctions, the key to determining the cause is often to stop the operation of the hardware when a specific condition is met, and to read and examine the internal state of the hardware at that time.

Furthermore, even when a hardware failure occurs, it is important to read out the internal state of the hardware at that time in order to identify the location of the failure. However, in such cases, before reading the internal state of the hardware, it is difficult to specify in detail which part of the hardware's internal state is to be read, and it takes a lot of time to read over a wide range. become.

An object of the present invention is to speed up access of large amounts of data from SvP to the main body of an information processing apparatus to which a large number of processing apparatuses of the same configuration are connected.

[Means to solve the problem]

The above purpose is to overlap the access from SvP to the SvP interface unit (IF) and the access from the SvP interface unit to the processing unit when it is necessary to perform a large amount of access from SvP to one processing unit. In order to enable processing, there is a buffer inside the SvP interface unit that can be written to from either the SvP or the scan control circuit in the SvP interface unit, and a buffer that can be read from the other side. A circuit is provided to switch the surface buffer from writing to reading or vice versa according to specific conditions, and the scan control circuit has a circuit that switches the buffer from writing to reading or vice versa according to specific conditions, and the scan control circuit has the following functions: This is achieved by adding a function to continuously access the processing device instead of SvP after booting from svp.

When reading a large amount of data from each processing device to svp for multiple processing devices with the same configuration, SvP supports continuous access to the target processing devices.
After activating the interface units (IF) at the same time, select the corresponding SvP interface units one by one from SvP, read the data in the read buffer, and repeat this as many times as necessary, with the above as one cycle. This is achieved by adopting a reading method.

[Effect]

The two-sided buffer is controlled by a switching circuit so that one side is used for writing and the other side is used for reading, and it is possible to write data to the former and read data from the latter in parallel.

The scan control circuit has the function of scanning in units of one word in the conventional manner, as well as scanning and scanning from the internal registers or flip-flops of the processing device according to instructions from the SVP.
Output and write to a buffer that is used for writing continuously for the specified word length, or scan from a buffer that is used for reading into an internal register or flip-flop of the read processing unit. It also has a function (referred to as a continuous access function) to perform processing continuously for a specified word length.

Through these operations, in at least one SvP interface unit, the scan control circuit writes scan-out data to one buffer, and writes the scan-out data to the other buffer holding the data scanned out in the previous cycle. , or scan-in by the scan control circuit of data in one buffer that holds the scan-in data written from SvP in the previous cycle, and scan-in by SvP to the other buffer. Writing can be done simultaneously.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, 8 is a scan word length register (S) for setting the word length for continuous scanning.
WL), 9 compares the value held in the scan word length register (SWL) with 0, and if they match, a comparison circuit (CMP) instructs the scan control circuit 3 to end continuous scanning, 10 a decrementer, and 11 a 12.13.14°18, 19.20 and 21 are selectors, 15-0 and 15-1 are buffers y (BUFa and BUFb), 16
-0 or 16-1 is buffer 15-0.15 respectively
Pointers (Pa and pb) that hold the addresses of data in -1 and 17 control buffers 15-0 and 15-1 so that one is for writing and the other is for reading, and can be used for writing under specific conditions. This is a circuit (SW) for switching between and for reading, and the other parts are the same as in FIG. Moreover, the system configuration is the same as that shown in FIG. 3 except for the SvP interface unit.

First, the case of reading out the internal state of one processing device will be explained in order. Here, the internal registers or flip-flops of the processing unit have scan addresses from 0 to 511. Furthermore, each processing device has an internal register or flip-flop that has a common function, and the same scan address is given to the internal register or flip-flop that has a common function in each processing device. shall be. (The internal register or flip-flop of which processing unit is accessed is determined by the selection of the SvP interface unit.) Also, the depth of buffer BUF a15-0 and buffer BUF b 15=1 is 64 words. .

(1) In order to select the processing device to be accessed, the SVP writes '1' to the bit position corresponding to the device number of the unit selection register (USR) in the SvP interface control circuit 2.

(2) S V P is a value indicating the word length for consecutively reading out the first value of the scan address, 'O1, into the scan address register 5 (in this example, the buffer depth is 64, so it is '64'). ') to the scan word length register 8, write the continuous scan word length to the command register 4 in order to start the scan control circuit 3.
Data '3' indicating out is written.

(3) When activated, the scan control circuit 3 instructs the switching circuit 17 to switch the write buffer, and
Permits the P interface control circuit 2 to release the 5VPBUS. Here, it is assumed that the buffer BUFb15-1 is for writing.

(4) SVP interface control circuit 2 has 5VPB
When the receiver receives US release permission, it sends A to SvP via the ACK line.
Returns CK signal.

On the other hand, the scan control circuit 3 compares the value of the scan word length register 8 (current value '64') with '0' by the comparison circuit 9, but since they are not equal, the scan
Scans out the value of the internal register or flip-flop of the processing unit pointed to by the value of address register 5 (current value '0'), and scans out the value of buffer BUFb.
15-1. After storage, the pointer 16-1 is advanced by l.

(5) SvP receives and accepts the ACK signal, but since there is no data to read at this time, it waits for the completion of the previously started continuous scan out by time monitoring.

On the other hand, the scan control circuit 3 decrements the value of the scan word length register 8 by 1 using the decrementer 10 and sets a new value. Also scan address
Add 1 to the value of register 5 by incrementer 11 to set a new value.

(6) The scan control circuit 3 converts the value of the scan word length register 8 (current value '63') into the comparison circuit 9.
However, since they are not equal, the value of the internal register or flip-flop of the processing unit pointed to by the value of scan address register 5 (current value '1') is scanned out, and the value of the internal register or flip-flop of the processing unit is scanned out and
b Store in 15-1. After storage pointer 16-1 is 1
You can proceed.

(7) The scan control circuit 3 decrements the value of the scan word length register 8 by 1 using the decrementer 10 and sets a new value. Also scan address
Add 1 to the value of register 5 by incrementer 11 to set a new value.

(8) The scan control circuit 3 is configured as described in (6) and (7) above.
This process is repeated until the value of the scan word length register 8 is not equal to t Oj , and when it becomes equal, the continuous access (in this case, continuous scan out) is terminated and the wait state is entered.

(9) SVP waits for the completion of the previous continuous scan-out by time monitoring, and then writes '64' in the scan address register 5 (the previous continuous scan-out ended up to scan address 163'). ) and the word length '64 is stored in scan word length register 8.
' After writing data 1 to command register 4.
Write 3' to activate continuous scan out.

(10) When activated, the scan control circuit 3 instructs the switching circuit 17 to change the write buffer to the buffer BU.
Switch to Fa15-1, give permission to SVP interface control circuit 2 to release 5VPBUS, and send AC to SVP.
Returns K signal. After that, scan address 164'
From '127', the same process as the second continuous scan out is performed.

(11) When the SVP receives the ACK signal, it transfers the data read in the -th consecutive scan out to the buffer BU.
Read one word from Fb 15-1 64 times. Reading from this buffer BUFb 15-1 is performed by the SvP interface control circuit 2 using the selectors 19 and 21 and the pointer Pb16-1.5VPBU.
S, ACK line is controlled and executed.

(12) S V P ha, buffer yBUFb 15-
1 to 0') When all reading is completed and the monitoring time is exceeded, the third continuous scan-out is prepared and started, and when the ACK signal is returned, the second continuous scan-out is started. Read out data from BUFa15-0.

(13) The SVP repeats preparation and startup of a new continuous scan out, then reads out the data that was previously scanned out, and then starts the continuous scan out for the seventh time.
It even reads out the data that has been written out.

(14) When the reading of the data that was continuously scanned out for the 7th time is completed and the monitoring time is exceeded, SVP performs a dummy continuous scan in order to read the data that was continuously scanned out for the 8th time.・Prepare for out,
Start and switch buffers.

That is, data '3' indicating continuous scan out is written to command register 4. However, since the value of the scan word length register 8 remains '0' at the end of the eighth consecutive scan out, the process ends simply by switching the buffers. Sv
When P receives the ACK signal, it reads out the data that has been continuously scanned out for the eighth time, and finishes reading the values of all internal registers or flip-flops in the processing device.

Regarding the above processing, the processing by the scan control circuit 3 is shown as a state transition in FIG. 4, and the flow of the entire processing is shown as a time chart in FIG. 5(a).

Next, the case of writing to consecutive addresses in one processing device differs from the case of continuous reading described above in the following points.

That is, the svp writes to the buffer, the scan control circuit 3 reads it and scans it into the processing device, the buffer is switched at the start of continuous scan-in, and at the end of the process, the buffer is This means that there is no need to activate dummy continuous access just for switching. Note that here, data '4' indicating continuous scan-in is stored in the command register 4.

Regarding the above processing, the processing by the scan control circuit 3 is shown as a state transition in FIG. 4, and the flow of the entire processing is shown as a time chart in FIG. 5(b).

Finally, a case will be described in which consecutive addresses are accessed for a plurality of processing devices. However, in the case of writing, it is only necessary to select a plurality of processing apparatuses and perform the same processing when writing to consecutive addresses for one processing apparatus, so a description thereof will be omitted.

The case of reading data from consecutive addresses to a plurality of processing devices will be explained with reference to FIG. Here, select the processing device, S
Preparation and activation of continuous scan out by vP, continuous scan out by scan control circuit 3 and SvP
The detailed contents of each read from the buffer by 1
This is the same as when reading data from consecutive addresses to one processing device. Also, the address is from O to 511,
The buffer depth is assumed to be 64 words.

(1) SVP has n+1 SVP interfaces
Select units 1-0 to 1-n and prepare and start the first continuous scan out.

(2) When activated, the scan control circuit 3 of each SVP interface unit 1-0 to 1-n processes continuous scan out after switching buffers and permitting SV and PBUS release. .

(3) Even if the SVP receives the ACK signal, since there is no data to read at this time, it waits for the monitoring time for the end of continuous scan-out to elapse. If the monitoring time is exceeded, n
Prepare and start the second continuous scan out for +1 processing device.

(4) Each Svp interface unit 1-〇~1
When activated, the -n scan control circuit 3 performs buffer switching and permission to release 5VPBUS, and then processes continuous scan out.

(s) When s v p receives the ACK signal, it reads out the data stored in the buffer, so it reads the data stored in the buffer one by one.
A vP interface unit is selected, one word is read out 64 times, and this is repeated n+1 times.

When the data from the previous continuous scan out has been read from all processing devices and the monitoring time has exceeded,
Select n+1 SVP interface units and prepare and start the next continuous scan out.

(6) When the above (4) and (5) are repeated and the data reading by the 7th consecutive scan-out is completed and the monitoring time is exceeded, the SvP performs the 8th consecutive scan-out. To read data, n +
After selecting one SVP interface unit, prepare and activate a dummy continuous scan out and switch buffers.

When the SvP receives the ACK signal, it selects the SvP interface units one by one and reads the data from the 8th consecutive scan out.

With the above steps, the process of reading out the internal states from the n+1 processing devices is completed.

The case of continuous access has been explained above, but the conventional one
It is clear from FIGS. 1 and 4 that word-by-word access is possible.

In this example, the processing device and the SVP interface unit are connected on a one-to-one basis, but the present invention is applicable even when one SvP interface is connected to a plurality of processing devices.

Further, the present invention is effective regardless of the scanning method of the SVP interface unit.

〔Effect of the invention〕

As described above, according to the present invention, when accessing consecutive addresses from svp to a main unit to which a large number of processing devices of the same configuration are connected, scan addresses or scan·
There is no need to set up data, start a scan, or wait for the end of a scan.
Since the time required is only to write scan-in data to the buffer in the unit or read scan-out data from the buffer in the SVP interface unit, high-speed processing is possible, and in the event of a malfunction, etc. This is effective in improving maintenance and diagnostic functions, such as when reading out the internal status of a processing device.

[Brief explanation of drawings]

FIG. 1 shows the SVP interface of one embodiment of the present invention.
Unit configuration diagram, Figure 2 is a configuration diagram of a conventional SvP interface unit, Figure 3 is a configuration diagram of the entire information processing device, Figure 4 is a state transition diagram of the scan control circuit, and Figure 5 is a single unit. FIG. 6 is a time chart when continuous scanning is performed for n processing devices. FIG. 6 is a time chart when continuous scanning is performed for n processing devices. 1...SvP interface unit, 2...
SvP interface control circuit, 3... Scan control circuit, 4... Command register, 5... Scan address register, 6... Scan data register.
Register X, 7, 12, 13, 14, 18, 19, 2
0,21·f L/ )y 5 . 8...Scan word length register, 9...
...Comparison circuit, 10...Decrementer, 11...Ink IJ Mentor, 15-0, 15-1-...Buff -
7y, 16-0.16-1...pointer, 17...
・Switching circuit. Collection 1 Figure patent applicant Director of the Agency of Industrial Science and Technology

Claims (1)

[Claims] 1. Information processing comprising a plurality of processing devices having the same configuration, each including a plurality of internal registers or flip-flops each having a scan address set therein, and a service processor connected to the processing device. The apparatus is provided with an interface unit arranged corresponding to one processing device or a group of plural processing devices and serving as a medium for accessing the processing device from the service processor, each interface unit having two interface units. one buffer,
The buffer is connected to the processing device on one side and the service on the other side.
a switching means connected to a processor; and a switching means connected to a processor; and a switching means for successively generating a specified number of scan addresses from said service processor to continuously transfer data between said one buffer and an internal register or flip-flop of the processing device; and an interface control circuit that accesses a plurality of data between the other buffer and the service processor. 1. An information processing apparatus characterized in that the switching means is controlled to switch the connections of the respective buffers when a number of scan addresses have been successively generated. 2. In the information processing device according to claim 1, when the service processor simultaneously scans out data from the processing devices via a plurality of interface units, the data is divided into several blocks in each processing device. Divide all target interfaces/
After the service processor instructs the unit to scan out one block of data, if there is a block that has already been read out in the interface unit's buffer, all target interfaces are scanned out. A service processor access method characterized by reading blocks sequentially from a unit.