JPH0487659U - - Google Patents

Info

Publication number
JPH0487659U
JPH0487659U JP13079890U JP13079890U JPH0487659U JP H0487659 U JPH0487659 U JP H0487659U JP 13079890 U JP13079890 U JP 13079890U JP 13079890 U JP13079890 U JP 13079890U JP H0487659 U JPH0487659 U JP H0487659U
Authority
JP
Japan
Prior art keywords
circuit board
metal base
gnd line
circuit pattern
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13079890U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13079890U priority Critical patent/JPH0487659U/ja
Publication of JPH0487659U publication Critical patent/JPH0487659U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
JP13079890U 1990-11-30 1990-11-30 Pending JPH0487659U (me)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13079890U JPH0487659U (me) 1990-11-30 1990-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13079890U JPH0487659U (me) 1990-11-30 1990-11-30

Publications (1)

Publication Number Publication Date
JPH0487659U true JPH0487659U (me) 1992-07-30

Family

ID=31878113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13079890U Pending JPH0487659U (me) 1990-11-30 1990-11-30

Country Status (1)

Country Link
JP (1) JPH0487659U (me)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017005170A (ja) * 2015-06-12 2017-01-05 富士電機株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017005170A (ja) * 2015-06-12 2017-01-05 富士電機株式会社 半導体装置

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