JPH0486997A - Filter circuit - Google Patents

Filter circuit

Info

Publication number
JPH0486997A
JPH0486997A JP20299890A JP20299890A JPH0486997A JP H0486997 A JPH0486997 A JP H0486997A JP 20299890 A JP20299890 A JP 20299890A JP 20299890 A JP20299890 A JP 20299890A JP H0486997 A JPH0486997 A JP H0486997A
Authority
JP
Japan
Prior art keywords
period
frequency
circuit
mean
average
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20299890A
Other languages
Japanese (ja)
Other versions
JP3031970B2 (en
Inventor
Masakazu Kobayashi
正和 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marelli Corp
Original Assignee
Kansei Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kansei Corp filed Critical Kansei Corp
Priority to JP2202998A priority Critical patent/JP3031970B2/en
Publication of JPH0486997A publication Critical patent/JPH0486997A/en
Application granted granted Critical
Publication of JP3031970B2 publication Critical patent/JP3031970B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To secure a quick responsiveness by finding frequencies from the average movement of periodic signals outputted from a period measuring section in time series and a mean frequency from the found frequencies, and then generating an output proportional to the output signal of the mean frequency. CONSTITUTION:A period measuring section 3 measures periods Tn of input signals fn at every edge of the signals fn by using a clock ck. A period averaging circuit 5 finds a mean period T0 by taking the sum of past m+1 pieces of periods Tn and dividing the sum by m+1 synchronously to the measurement by the section 3 and stores the mean period in a register 6. The circuit 5, on the other hand, samples mean periods T0 at fixed time intervals Ts asynchronously to the measurement and finds frequencies Fa by means of an inverse operation circuit 8. Then the circuit 5 takes are sum of the n+1 pieces of the so far found frequencies Fa and finds a mean frequency F0 by dividing the sum by n+1 by means of a frequency averaging circuit 10. A drive circuit 11 decides a deflection angle against the value of the found mean frequency F0 and drives an analog meter 12.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

この発明は周期計測をしてアナログメータを駆動するシ
ステムのフィルタ回路に関する。
The present invention relates to a filter circuit for a system that measures periods and drives an analog meter.

【従来の技術】[Conventional technology]

従来のフィルタ回路としては例えば第3図および第4図
に示すようなものがある。第3図において、lはパルス
カウント方式〇カウンタで、このカウンタ1はセンサ(
図示せず)が検出した入力周波数fを一定のゲート時間
T、たけ計数するものである。 すなわち、パルスカウント方式は第5図(a)に示すよ
うにゲート信号(パルス)の立上りから立下りまでの時
間Tsにカウンタ1に入力される入力周波数fの計数結
果を計測値出力としてアナログメータを駆動する信号処
理方式である。 また、第4図において、2は周期計測方式〇カウンタで
、このカウンタ2は一定の周波数のクロック信号ckを
センサ(図示せず)が検出した入力信号fの周期時間T
sだけ計数するものである。 周期計測方式は第5図(b)に示すように入力信号fの
周期時間T8に入力されるクロック信号ckを計数した
計数結果を計測値としてアナログメータを駆動する信号
処理方式である。
Examples of conventional filter circuits include those shown in FIGS. 3 and 4. In Fig. 3, l is a pulse count type counter, and this counter 1 is a sensor (
(not shown) counts the detected input frequency f for a certain gate time T. That is, in the pulse counting method, as shown in FIG. 5(a), the count result of the input frequency f input to the counter 1 during the time Ts from the rise to the fall of the gate signal (pulse) is used as the measurement value output by the analog meter. This is a signal processing method that drives the In addition, in FIG. 4, 2 is a period measurement method counter, and this counter 2 is a period time T of an input signal f that a sensor (not shown) detects a clock signal ck of a constant frequency.
It counts only s. As shown in FIG. 5(b), the period measurement method is a signal processing method in which the clock signal ck input during the period T8 of the input signal f is counted and the result of counting is used as a measurement value to drive an analog meter.

【発明が解決しようとする課題】[Problem to be solved by the invention]

しかしながら、第3図に示すような従来のフィルタ回路
にあっては、入力周波数を積分するため周波数変動(周
期変動)に対する針振れ(サンプリングエラー)は小さ
いが、応答性がゲート時間で制限されるため、扱う周波
数が低いときは応答性が遅くなるという問題点があった
。 また、第4図に示すような従来のフィルタ回路は入力周
波数の一周期毎にデータが更新されるため、応答性は早
いが周期変動があった場合(第5図(1))参照)、針
振れ(サンプリングエラー)となるという問題点があっ
た。 この発明は上記のような問題点を解消するためになされ
たもので、周期計測により早い応答性を確保し、サンプ
リングエラーを防止し、さらに周期を周波数に変換した
後、平均化処理を行うようにするフィルタ回路を得るこ
とを目的とする。
However, in the conventional filter circuit shown in Fig. 3, since the input frequency is integrated, the stylus runout (sampling error) against frequency fluctuations (periodic fluctuations) is small, but the responsiveness is limited by the gate time. Therefore, there was a problem in that the response was slow when the handled frequencies were low. In addition, in the conventional filter circuit shown in Fig. 4, data is updated every cycle of the input frequency, so the response is fast, but if there is a periodic fluctuation (see Fig. 5 (1)), There was a problem that needle runout (sampling error) occurred. This invention was made in order to solve the above problems.It ensures quick response through period measurement, prevents sampling errors, and furthermore performs averaging processing after converting the period to frequency. The purpose is to obtain a filter circuit that provides

【課題を解決するための手段】[Means to solve the problem]

この発明に係るフィルタ回路はセンサから出力されるパ
ルス信号の周期を求める周期計測部と、この周期計測部
から時系列的に出力される周期信号の移動平均を求める
周期平均化処理回路と、この周期平均化処理回路で求め
た周期平均を逆算し、周期平均に対する周波数を求める
周波数算出回路と、この周波数算出回路からの出力信号
の周波数平均を求める周波数平均化処理回路と、この周
波数平均化処理回路の出力信号に比例した出力を発生し
、振れ角を決定する駆動回路とで構成されている。
The filter circuit according to the present invention includes a period measuring section that calculates the period of the pulse signal output from the sensor, a period averaging processing circuit that calculates the moving average of the periodic signal outputted in time series from the period measuring section, and A frequency calculation circuit that calculates the frequency with respect to the period average by inversely calculating the period average obtained by the period average processing circuit, a frequency averaging processing circuit that calculates the frequency average of the output signal from this frequency calculation circuit, and this frequency averaging processing. It consists of a drive circuit that generates an output proportional to the output signal of the circuit and determines the deflection angle.

【作用】[Effect]

この発明におけるフィルタ回路はセンサから出力される
パルス信号の周期を周期計測部により求め、この周期計
測部から時系列的に出力される周期信号の移動平均を求
めると共に、求めた周期平均を逆算し、周期平均に対す
る周波数を求め、求めた周波数から周波数平均を求めて
その出力信号に比例した出力を発生し、振れ角を決定し
てメータを駆動するようにしたことにより早い応答性を
確保し、サンプリングエラーを防止すると共に、周波数
の平均化により適度な応答性と滑らかなムーブメントの
動きが得られる。
The filter circuit in this invention determines the period of the pulse signal output from the sensor by a period measuring section, calculates a moving average of the periodic signal outputted in time series from this period measuring section, and back-calculates the determined period average. , find the frequency for the periodic average, calculate the frequency average from the calculated frequency, generate an output proportional to the output signal, determine the deflection angle, and drive the meter to ensure quick response. In addition to preventing sampling errors, frequency averaging provides appropriate responsiveness and smooth movement.

【実施例】【Example】

以下、この発明を図面に基づいて詳細に説明する。 第1図はこの発明の一実施例を示すブロンク図、第2図
は第1のフローチャートである。まず構成を説明すると
、3は入力信号f7の周期計測部、4は周期計測部3で
周期計測されたm+1個のデータを保持するシフトレジ
スタ、5はシフトレジスタ4が保持するm+1個のデー
タを加算し、その結果をm+1で割算する周期平均化処
理回路、6は周期平均化処理回路50周期平均T。を保
持するレジスタで、これら周期計測部3、シフトレジス
タ4、周期平均化処理回路5およびレジスタ6により周
期フィルタ7を構成する。 8は一定時間Ts毎に周期T0をサンプリングして周波
数Faに変換する周波数算出回路である逆算回路、9は
逆算回路8の演算結果を保持するシフトレジスタ、lO
はシフトレジスタ9が保持するn個の周波数を加算し、
その結果をnで割り算する周波数平均化処理回路、11
は周波数平均化処理回路10よりの周波数平均F。に比
例した出力を発生し、アナログメータ12を駆動する駆
動回路で、逆算回路8、シフトレジスタ9、周期平均化
処理回路工0および駆動回路IIにより周波数フィルタ
13を構成する。 次に動作について説明する。 まず、周期計測部3において入力信号f7のエツジ毎に
クコツクckによりその周期T1を計測する。この周期
計測と同期して周期平均化処理回路5により過去m+1
個の周期T7を加算し、その結果をm、+1で割り算し
て周期平均化処理して周期平均T0を求める。この結果
はレジスタ6にストアしておく。 一方、これとは非同期に一定時間T5おきに周期平均T
0をサンプリングし、逆算回路8により周期を逆算して
周波数F、を求める。そして、今まで求めたn+1個の
周波数F1を加算し、その結果を周波数平均化処理回路
10によりn+1で割り算して平均化処理して周波数平
均F0を求める。駆動回路11は求めた周波数平均F0
の値に対し振れ角を決定し、アナログメータ12を駆動
する。 なお、上記実施例では周期平均化処理回路5により求め
る周期平均T。の求め方を としたが、 m        m であっても良い。 また、上記実施例では周波数平均化処理回路10により
求める周波数平均F。の求め方をとしたが、 n        n であっても良い。
Hereinafter, the present invention will be explained in detail based on the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a first flowchart. First, to explain the configuration, 3 is a period measuring section for the input signal f7, 4 is a shift register that holds m+1 pieces of data whose period has been measured by the period measuring section 3, and 5 is a shift register that holds m+1 pieces of data held by the shift register 4. A cycle averaging processing circuit which adds the sum and divides the result by m+1; 6 is a cycle averaging processing circuit 50 and a cycle averaging T; The period measurement unit 3, shift register 4, period averaging processing circuit 5, and register 6 constitute a period filter 7. Reference numeral 8 denotes an inverse calculation circuit which is a frequency calculation circuit that samples the period T0 at fixed time intervals Ts and converts it into a frequency Fa; 9 a shift register that holds the calculation result of the inversion circuit 8; lO
adds n frequencies held by shift register 9,
A frequency averaging processing circuit that divides the result by n, 11
is the frequency average F from the frequency averaging processing circuit 10. The frequency filter 13 is a drive circuit that generates an output proportional to , and drives the analog meter 12. The inverse calculation circuit 8, the shift register 9, the period averaging circuit 0, and the drive circuit II constitute a frequency filter 13. Next, the operation will be explained. First, the cycle measuring section 3 measures the cycle T1 for each edge of the input signal f7 using the clock ck. In synchronization with this cycle measurement, the cycle averaging processing circuit 5 calculates the past m+1
The period T7 is added, the result is divided by m, +1, and period averaging processing is performed to obtain the period average T0. This result is stored in register 6. On the other hand, asynchronously, the cycle average T
0 is sampled, and the period is inversely calculated by the inverse calculation circuit 8 to obtain the frequency F. Then, the n+1 frequencies F1 obtained so far are added, and the result is divided by n+1 by the frequency averaging processing circuit 10 to perform averaging processing to obtain the frequency average F0. The drive circuit 11 uses the determined frequency average F0
The deflection angle is determined based on the value of , and the analog meter 12 is driven. In the above embodiment, the period average T is determined by the period average processing circuit 5. , but m m may also be used. Further, in the above embodiment, the frequency average F is determined by the frequency averaging processing circuit 10. , but n n may also be used.

【発明の効果】【Effect of the invention】

以上説明してきたようにこの発明によれば、その構成を
センサから出力されるパルス信号の周期を求める周期計
測部と、この周期計測部から時系列的に出力される周期
信号の移動平均を求める周期平均化処理回路と、この周
期平均化処理回路で求めた周期平均を逆算し、周期平均
に対する周波数を求める周波数算出回路と、この周波数
算出回路からの出力信号の周波数平均を求める周波数平
均化処理回路と、この周波数平均化処理回路の出力信号
に比例した出力を発生し、振れ角を決定する駆動回路と
したため、周期計測による応答性の改善を可能とし、周
期データの平均化によるサンプリングエラーを防止し、
周波数の平均化による適度な応答性と滑らかなムーブメ
ントの動きが可能となるという効果が得られる。
As explained above, according to the present invention, the configuration includes a period measuring section that calculates the period of the pulse signal output from the sensor, and a moving average of the periodic signal outputted in time series from the period measuring section. A period averaging processing circuit, a frequency calculation circuit that calculates the frequency with respect to the period average by inversely calculating the period average obtained by this period averaging processing circuit, and a frequency averaging process that calculates the frequency average of the output signal from this frequency calculation circuit. The drive circuit generates an output proportional to the output signal of the frequency averaging processing circuit and determines the deflection angle, making it possible to improve responsiveness through periodic measurement and eliminate sampling errors caused by averaging periodic data. prevent,
The effects of frequency averaging enable appropriate responsiveness and smooth movement.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すブロック図、第2図
は第1図の動作を説明するフローチャート、第3図は従
来のフィルタ回路の一例を示すブロック図、第4図は従
来のフィルタ回路の他の例を示すブロック図、第5図(
a)は第3図の動作を説明するフローチャート、同図(
b)は第4図の動作を説明するフローチャートである。 3・・・周期計測部   5・・・周期平均化処理回路
8・・・周波数算出回路 10・・・周波数平均化処理回路 11・・・駆動回路
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an example of a conventional filter circuit, and FIG. A block diagram showing another example of a filter circuit, FIG.
a) is a flowchart explaining the operation of FIG.
b) is a flowchart explaining the operation of FIG. 4; 3...Period measurement unit 5...Period averaging processing circuit 8...Frequency calculation circuit 10...Frequency averaging processing circuit 11...Drive circuit

Claims (1)

【特許請求の範囲】[Claims]  センサから出力されるパルス信号の周期を求める周期
計測部(3)と、この周期計測部から時系列的に出力さ
れる周期信号の移動平均を求める周期平均化処理回路(
5)と、この周期平均化処理回路で求めた周期平均を逆
算し、周期平均に対する周波数を求める周波数算出回路
(8)と、この周波数算出回路からの出力信号の周波数
平均を求める周波数平均化処理回路(10)と、この周
波数平均化処理回路の出力信号に比例した出力を発生し
、振れ角を決定する駆動回路(11)とを備えたフィル
タ回路。
A period measuring section (3) that calculates the period of the pulse signal output from the sensor, and a period averaging processing circuit (3) that calculates the moving average of the periodic signal outputted in time series from the period measuring section (3).
5), a frequency calculation circuit (8) that calculates the frequency with respect to the period average by inversely calculating the period average obtained by this period average processing circuit, and a frequency averaging process that calculates the frequency average of the output signal from this frequency calculation circuit. A filter circuit comprising a circuit (10) and a drive circuit (11) that generates an output proportional to the output signal of the frequency averaging processing circuit and determines the deflection angle.
JP2202998A 1990-07-31 1990-07-31 Filter circuit Expired - Fee Related JP3031970B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2202998A JP3031970B2 (en) 1990-07-31 1990-07-31 Filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2202998A JP3031970B2 (en) 1990-07-31 1990-07-31 Filter circuit

Publications (2)

Publication Number Publication Date
JPH0486997A true JPH0486997A (en) 1992-03-19
JP3031970B2 JP3031970B2 (en) 2000-04-10

Family

ID=16466639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2202998A Expired - Fee Related JP3031970B2 (en) 1990-07-31 1990-07-31 Filter circuit

Country Status (1)

Country Link
JP (1) JP3031970B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0861995A (en) * 1994-08-18 1996-03-08 Tech Res & Dev Inst Of Japan Def Agency Ship passage detecting method and its device through hydraulic pressure variation
JP2020053842A (en) * 2018-09-27 2020-04-02 沖電気工業株式会社 Communication device aggregation device communication system and control program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0861995A (en) * 1994-08-18 1996-03-08 Tech Res & Dev Inst Of Japan Def Agency Ship passage detecting method and its device through hydraulic pressure variation
JP2020053842A (en) * 2018-09-27 2020-04-02 沖電気工業株式会社 Communication device aggregation device communication system and control program

Also Published As

Publication number Publication date
JP3031970B2 (en) 2000-04-10

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