JPH0485948A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid defective cutting of a redundant fuse element by a method wherein the redundant fuse element is composed of the same conductor layer as the plate electrode of the stacked structure information storing capacitance element of a memory cell to which a fixed potential is applied. CONSTITUTION:A semiconductor integrated circuit device has a DRAM composed of a memory cell M which is composed of a series circuit of a memory cell selecting MIS-FET Qs and a stacked structure information storing capacitance element C and a redundant fuse element F, which is cut by a laser cutting method, of a redundant circuit which helps the memory cell. The redundant fuse element F is composed of the same conductive layer as the plate electrode 14 of the stacked structure information storing capacitance element C of the memory cell M to which a fixed potential is applied. With this constitution, the plate electrode 14 of the stacked structure information storing capacitance element C of the memory cell M is made of the mate material of an uppermost layer in a DRAM manufacturing process and the redundant fuse element F can be isolated from the main surface of a p--type semiconductor substrate 1, so that the defective cutting of the redundant fuse care be avoided and, further, damages against the semiconductor substrate side can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a redundant fuse element, and in particular to a DRAM,
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having a random access memory) and a redundant fuse element thereof.

[Conventional technology]

A DRAM is provided with a redundant circuit for repairing defective parts in order to prevent the entire product from becoming defective due to the occurrence of a defect in a part of a memory cell of several bits, and to increase the yield in the manufacturing process. A redundant fuse element is arranged in the redundant circuit to determine whether or not to operate this circuit.

The redundant fuse element is formed of a gate material such as a polycrystalline silicon film. A polycrystalline silicon film is an optimal material for a fuse element because it has a higher resistance value than, for example, an aluminum film used as another conductive layer. The redundant fuse element is covered with a passivation film (protective film), and the cut region of the redundant fuse element is exposed through an opening formed in the passivation film. It is common practice to cut this redundant fuse element by an electric cutting method.

Recently, research and development has been progressing on a laser cutting method that uses laser light to cut the redundant fuse element. This laser cutting method can align the laser beam with high precision to the cutting area of the redundant fuse element, which has been miniaturized due to high integration. In other words, the laser cutting method has advantages over the electric cutting method in that it can reduce the circuit area for cutting mounted on the DRAM, has high controllability of cutting conditions, and has extremely little re-welding after cutting. be. Also, in the laser cutting method, polycrystalline silicon films are advantageous over metal films such as aluminum films in terms of low reflectance and high absorption.

A DRAM developed by the present inventor and having a memory cell configured with a series circuit of a memory cell selection MOSFET and a planar structure information storage capacitor element has a two-layer gate structure. The first layer gate material forms a plate electrode to which a fixed potential of the planar information storage capacitor element of the memory cell is applied, and is formed of a polycrystalline silicon film. The second layer gate material is MO8 for memory cell selection.
FET gate electrode and word line, peripheral circuit MOSF
Each of the gate electrodes of the ET is formed, for example, from a polycrystalline silicon film. In the peripheral circuit, a resistor element of a delay circuit is formed using a second layer of gate material, and a redundant fuse element of the redundant circuit is formed in the same manufacturing process as this resistor element.

In the case of a DRAM having a large capacity of 1 to 16 [Mbit], which is currently being developed by the present inventor, a stacked structure (STC structure) is adopted for the information storage capacitive element of the memory cell. This stacked structure information storage capacitor element has a structure in which a lower layer electrode, a dielectric film, and a plate electrode serving as an upper layer electrode are sequentially laminated on the step of the gate electrode of the MO8FET for memory cell selection.

In other words, the stacked structure information storage capacitor element has the feature that the charge storage area can be increased in the height direction of the semiconductor substrate, and the occupied area can be reduced. DRAM with this large capacity
By adopting the above-mentioned stacked structure, - boat fishing is constructed with a three-layer gate structure.

The first layer of gate material forms the gate electrode of the MO8FET for memory cell selection and the gate electrode of the MOSFET of the word line 1 peripheral circuit. The second layer of gate material forms the lower electrode of the information storage capacitive element in the stacked structure.
The gate material of each layer forms a plate electrode. The redundant fuse element of the redundant circuit has been developed in accordance with the flow of technology.
It is made of layers of gate material.

Regarding the redundancy relief method, for example, see Japanese Unexamined Patent Publication No. 1983
It is described in No. 10228.

[Problem to be solved by the invention]

The inventor of the present invention discovered the following problems prior to developing the above-mentioned DRAM having a large capacity.

The redundant fuse element of the redundant circuit mounted on the DRAM is formed of the first layer gate material, that is, the lowest layer gate material closest to the main surface of the semiconductor substrate, based on the stacked structure. .

On the other hand, in the laser cutting method, in order to prevent cutting defects, there is a range (margin) in the depth of focus of the laser beam in the depth direction of the semiconductor substrate, and it is necessary to set the power of the laser beam excessively. Therefore, when cutting the redundant fuse element using the laser cutting method, especially if the power of the laser beam is too high, an opening will be formed that will penetrate through the passivation film and the redundant fuse element and reach the surface of the semiconductor substrate. (Causes damage to the surface of the semiconductor substrate).

The opening formed during this laser cutting becomes a route for contaminants such as resin in the resin-sealed package to enter the MOSFET.
This causes deterioration of device characteristics, such as fluctuations in the threshold voltage of ET.

Furthermore, when cutting the redundant fuse element using the laser cutting method, if the power of the laser beam is too low, the redundant fuse element cannot be completely cut, resulting in a cutting failure.

An object of the present invention is to prevent defective cutting of the redundant fuse element in a semiconductor integrated circuit device having a redundant fuse element cut by a laser cutting method, and to reduce damage to the semiconductor substrate side. The goal is to provide technology.

Another object of the present invention is to provide a technique that achieves the above object and can reduce the number of manufacturing processes for semiconductor integrated circuit devices.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) A DRAM comprising a memory cell formed by a series circuit of a memory cell selection MISFET and a stacked information storage capacitor element, and a laser cutting method of a redundant circuit for saving the memory cell. In a semiconductor integrated circuit device having a redundant fuse element that is cut,
The redundancy fuse element is formed of the same conductive layer as the plate electrode to which a fixed potential of the information storage capacitor element of the stacked structure of the memory cell is applied. The stacked structure information storage capacitive element is connected to the memory cell selection MI.
a first electrode connected to one semiconductor region of the 5FET;
It is constructed by sequentially laminating a dielectric film and a second electrode, which is the plate electrode.

(2) In a semiconductor integrated circuit device having a redundant fuse element cut by a redundant circuit laser cutting method on a semiconductor substrate, between a region of the redundant fuse element cut by a laser beam and the semiconductor substrate, A shielding film that absorbs or reflects the laser beam is provided.

(3) The redundant circuit of the means (2) is used as a relief circuit for a memory cell constituted by a series circuit of a DRAM memory cell selection MISFET and a stacked information storage capacitor element, and the redundant circuit is redundant. The fuse element is formed of the same conductive layer as one upper layer electrode (plate electrode) of the stacked information storage capacitor element, and the shielding film is formed of the same conductive layer as the other lower layer electrode or the gate electrode of the memory cell selection MISFET. It is formed of the same conductive layer.

[For production]

According to the above-mentioned means (1), (A) the plate electrode of the stacked-structure information storage capacitor element of the memory cell of the DRAM is formed of the uppermost layer gate material in the DRAM manufacturing process, and the redundant fuse Since the element can be separated from the main surface of the semiconductor substrate, the amplitude of the focal depth fluctuation of the laser beam during laser cutting can be separated from the main surface of the semiconductor substrate, and damage to the main surface of the semiconductor substrate caused by the laser beam can be prevented.

(B) Since the redundant fuse element can be separated from the main surface of the semiconductor substrate and brought close to the surface of the final protective film, the power of the laser beam can be reduced and the damage to the main surface of the semiconductor substrate of the effect (A) can be avoided. More preventable.

(C) The plate electrode of the stacked structure information storage capacitor needs only to be applied with a fixed potential, and conditions such as film thickness and resistance value can be relatively freely set, making it ideal for the redundant fuse element. According to the above-mentioned means (2), the plate electrode of the information storage capacitive element can be formed under the following conditions.
When cutting the redundant fuse element with a laser, excess laser light reaching the semiconductor substrate side can be absorbed or reflected by the shielding film, so damage to the main surface of the semiconductor substrate caused by the laser light can be prevented.

According to the above-mentioned means (3), a redundant fuse element can be formed with one electrode of the information storage capacitor element of the stacked structure of the memory cell of the DRAM, and a shielding film can be formed with the other electrode or the gate electrode. , the number of conductive layers is reduced by the amount corresponding to each of the redundant fuse element and the shielding film,
The structure of a semiconductor integrated circuit device can be simplified. Further, the number of manufacturing processes for the semiconductor integrated circuit device can be reduced by the amount corresponding to the redundant fuse element and the shielding film.

Hereinafter, regarding the configuration of the present invention, MIS for memory cell selection will be explained.
An embodiment will be described in which the present invention is applied to a DRAM configured with a series circuit of an FET and a stacked information storage capacitive element.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example 1) The main parts of a DRAM having a large capacity, which is Example I of the present invention, are shown in FIG. 1 (cross-sectional view) and FIG. 2 (plan view). 1st
The figure shows a memory cell portion on the right side and a redundant fuse element of a redundant circuit on the left side. FIG. 2 shows the redundant fuse element.

As shown in Figure 1, DRAM is made of single crystal silicon.
It is composed of a - type semiconductor substrate 1. n-channel MIS of a complementary MISFET in a memory cell M (memory cell array) formation region of a p-type semiconductor substrate 1 and a peripheral circuit (not shown)
A P-type well region 2 is formed on the main surface of the FET formation region. The complementary MISFET of the P-type semiconductor substrate 1
An n-type well region is formed in the main surface of the p-channel MISFET formation region.

An element isolation insulating film (field insulating film) 3 is formed on each of the inactive regions of the p-type well region 2 and the n-type well region. A p-type channel stopper region 4 is formed on the main surface of the p-type well region 2 under the element isolation insulating film 3 .

The memory cell M of the DRAM is a memory cell selection MI
It is composed of a series circuit of S F E T Q s and a stacked information storage capacitive element C.

The MISFET Qs for memory cell selection is formed on the main surface of the P-type well region 2 in a region defined by the element isolation insulating film 3 and the p-type channel stopper region 4 . M1.5FETQs for memory cell selection is mainly p
It is composed of a type well region 2, a gate insulating film 5, a gate electrode 7, and a source region and a drain region 18.

The gate insulating film 5 is formed of, for example, a silicon oxide film formed by oxidizing the main surface of the p-type well region 2.

The gate electrode 7 is provided on the gate insulating film 5 . The gate electrode element is formed of a laminated film in which a polycrystalline silicon film and a refractory metal silicide film are sequentially laminated, for example. The lower layer polycrystalline silicon film is deposited by the CVD method, and an n-type impurity (P is As) is introduced to reduce the resistance value. This polycrystalline silicon film is formed to have a thickness of, for example, about 200 to 300 [nm]. The upper layer high melting point metal silicide film is formed by sputtering or CV
A six-gate electrode 7 deposited by the D method and formed to have a film thickness of, for example, about 200 to 300 nm is formed integrally with a word line (WL) 7 in the gate width direction. This gate electrode 7 and word line 7 are the first
It is formed by a step of forming gate material in layers.

The source region 18. Each of the drain regions 18 is composed of an n-type semiconductor region with a lower impurity concentration on the channel formation region side. Further, each of the source region 18 and the drain region 18 is formed of an n° type semiconductor region with a high impurity concentration in a region connected to another conductor film (12 or 17). In other words, the memory cell selection MISFETQs is LDD
(Lightly opened and rain) structure.

An insulating film 8 is formed on each of the gate electrode element and word line 7, and an insulating sidewall spacer 9 is formed on each side wall.

The information storage capacitive element C of the stacked (STC) structure of the memory cell M has a structure in which a lower layer electrode 12, a dielectric film 13, and a plate electrode 14, which is an upper layer electrode, are laminated in sequence.

The center portion of the lower electrode 12 is the memory cell selection M.
It is connected to one source region 18 or drain region 18 of ISFETQs. This connection is made within a region defined by the opening 11 formed in the glabella insulating film 10 and the sidewall spacer 9, and through the region. The peripheral portion of the lower electrode 12 is drawn out onto the gate electrode 7 and the word line 7 through the sidewall spacer 9, the insulating film 8°, and the glabellar insulating film 10, respectively. The lower electrode 12 is formed of a polycrystalline silicon film deposited, for example, by the CVD method, and has a thickness of about 250 to 500 [nm1]. In addition, this polycrystalline silicon film has n
The six lower layer electrodes 12 into which type impurities are introduced are formed in the second layer gate material forming step in the manufacturing process.

Dielectric film 13 is formed on the surface of lower electrode 12 .

The dielectric film 13 is formed of, for example, a silicon oxide film, a silicon nitride film, or a laminated film that is a combination of both.

The plate electrode 14 is formed as a common electrode on the lower electrode 12 of all the memory cells M of the memory cell array of the DRAM. A fixed potential (for example, a potential half of the operating potential of the circuit applied within the memory cell array) is applied to the plate electrode 14. The plate electrode 14 is formed of a polycrystalline silicon film deposited by, for example, a CVD method, and an n-type impurity is introduced into this polycrystalline silicon film to obtain conductivity.

This polycrystalline silicon film is formed to have a thickness of, for example, about 200 [nml]. The plate electrode 14 is formed in the step of forming the third layer of gate material in the manufacturing process. Since the DRAM of this embodiment has a three-layer gate structure, the plate electrode 14 is made of the gate material of the uppermost layer of the DRAM.

In the memory cell M of the DRAM configured in this manner, a complementary data line (DL) 17 is connected to the other drain region 18 or source region 18 of the memory cell selection MISFETQs. This connection is made using the interlayer insulating film 15.
This is done through a connecting hole 16 formed in the. The complementary data line 17 is formed of, for example, an aluminum alloy film,
It is formed with a film thickness of about 00 [nm1.

The aluminum alloy film is Si, Cu, or aSX, which is an aluminum film added with Si and Cu, can reduce the alloy spike phenomenon. Cu can improve electromigration breakdown voltage. The complementary data line 17 is formed in the first layer wiring formation step in the manufacturing process.

Said complementarity data I! A final passivation film (final protective film) 19 is formed on the film 17. The final passivation film 19 is mainly formed of, for example, a silicon nitride film in order to improve the temperature resistance. Although not shown in the drawings, in actuality, a shunt word line and the like are formed on the complementary data line 17 using the second layer wiring in the manufacturing process.

The DRAM is provided with a redundant fuse element F of a redundant circuit for relieving the word line 7 or complementary data line 17 connected to the defective memory cell M (defective bit). As shown in FIGS. 1 and 2, this redundant fuse element F includes an element isolation insulating film 113, an interlayer insulating film 10. Insulating film 13
It is constructed by interposing each of them. The redundant fuse element F is composed of a polycrystalline silicon film 14 formed in the third layer gate material forming step in the manufacturing process. In other words, the redundant fuse element F is made of the same conductive layer (same manufacturing process) as the plate electrode 14 of the information storage capacitive element C of the stacked structure of the memory cell M, and is made of the gate material of the uppermost layer. A wiring 17 is connected to one end and the other end of the fuse element F. This line 1li17 is made of the same conductive layer as the complementary data line 17.

The redundant fuse element F is cut (fused) at its center by a laser cutting method, that is, by irradiation with a laser beam, when a defective bit is to be repaired or when there is no defective bit.

The plate electrode 14 of the information storage capacitive element C in the stacked structure of the memory cell M can be relatively freely set in terms of its film thickness, resistance value, etc. by simply applying a fixed potential. The gate material of the third layer can be constructed under optimal conditions (film thickness, resistance value, etc.) for the redundant fuse element F. On the other hand, the first layer of gate material is used for the word line 7 and the gate electrode 7 of the MISFET (for example, Qs).
It is used as a redundant fuse element F because it is formed with a thick film and a low resistance value in order to increase the access speed. What is the second layer of gate material?

Stacked structure information storage capacitive element C of memory cell M
It is used as the lower electrode 12 of the lower layer electrode 12, and is formed with a thick film thickness in order to increase its charge storage amount (increase the m! wall area of the lower layer l! electrode 12), so it is not suitable for the redundant fuse element F. The first-layer wiring (17) and the second-layer wiring are basically wiring materials with too small a resistance value, and the laser beam is reflected, so they are not suitable for the redundant fuse element F. Furthermore, a high melting point metal film or a high melting point metal silicide film as a gate material is not suitable for the redundant fuse element F because it has a small resistance value.

In this way, the DRAM includes a memory cell M formed by a series circuit of a memory cell selection MISFET QS and a stacked information storage capacitor C, and a redundant circuit for relieving the memory cell M. In a semiconductor integrated circuit device having a redundant fuse element F cut by a laser cutting method, the redundant fuse element F is replaced with a stacked information storage capacitor element C of the memory cell M.
It is made of the same conductive layer as the plate electrode (top layer gate material) 14 to which a fixed potential of is applied. This configuration allows (
A) The plate electrode 14 of the information storage capacitive element C of the stacked structure of the memory cell M of the DRAM is formed of the gate material of the uppermost layer in the DRAM manufacturing process, and the redundant fuse element F is formed of the p-type semiconductor substrate. 1 (p-type well region 2), the amplitude of the fluctuation B of the depth of focus of the laser beam (indicated by the symbol LB in FIG. 1) during laser cutting can be reduced.
M can be separated from the main surface of the P-type semiconductor substrate 1, and damage to the main surface of the P-type semiconductor substrate 1 due to laser light can be prevented. (B) Since the redundant fuse element F can be separated from the main surface of the P-type semiconductor substrate 1 and brought close to the surface of the final protective film, the power of the laser beam can be reduced and the P
Damage to the main surface of the - type semiconductor substrate 1 can be further prevented.

(C) The plate electrode 14 of the stacked structure information storage capacitive element C only needs to be applied with a fixed potential, and conditions such as film thickness and resistance value can be relatively freely set. The plate electrode 14 of the information storage capacitive element C can be formed under conditions optimal for F.

(Actually, Flow Side (■)) This embodiment (2) is a second embodiment of the present invention in which a shielding film is provided below the redundant fuse element that is cut by the laser cutting method.

FIG. 3 (cross-sectional view) shows the main part of a DRAM having a large capacity, which is Embodiment (2) of the present invention.

As shown in FIG. 3, a shielding film 7 is formed under the redundant fuse element F of the redundant circuit mounted on the DRAM, at least in the region to be cut. As in Example I, the redundant fuse element F is made of the same conductive layer as the plate electrode 14 of the information storage capacitive element C of the stacked structure. The shielding film is MISF for memory cell selection.
It is composed of the same conductive layer as the gate electrode 7 (first layer, bottom layer gate material) of E T Q s. In other words, the shielding film 7
In the case of a polycrystalline silicon film, it can actively absorb laser light, and in the case of a high melting point metal silicide film, it can actively reflect laser light.

Further, the shielding film 7 may be formed of the same conductive layer as the lower electrode 14 of the information storage capacitive element C of the stacked structure, or the DRAM may be configured with a four-layer gate structure, and the additional gate It can be constructed from materials.

In this way, in a semiconductor integrated circuit device having a redundant fuse element F on a p-type semiconductor substrate 1 which is cut by a redundant circuit laser cutting method, the redundant fuse element F
A shielding film 7 that absorbs or reflects the laser beam is provided between the region to be cut by the laser beam and the P~ type semiconductor substrate 1. With this configuration, when cutting the redundant fuse element F with the laser, the shielding film 7 can absorb or reflect excess laser light that reaches the p-type semiconductor substrate 1 side. Damage to the main surface can be prevented.

Further, a redundant fuse element F can be formed by the plate electrode 14 of the stacked information storage capacitor C of the memory cell M of the DRAM, and the gate electrode 7 (or the lower layer electrode 1
2) because the shielding film 7 can be formed.

The number of gate structures corresponding to the redundant fuse element F and the shielding film 7 can be reduced, and the structure of the semiconductor integrated circuit device can be simplified. Further, the redundant fuse element F
, and the shielding film 7, the number of manufacturing processes for the semiconductor integrated circuit device can be reduced.

Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course there is.

For example, the present invention provides a semiconductor integrated circuit device equipped with an SRAM, in which a redundant fuse element may be formed of the same conductive layer as the uppermost gate material of the gate materials forming each element of the memory cell of the SRAM. good.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a redundant fuse element cut by a laser cutting method, defective cutting of the redundant fuse element can be prevented and damage to the semiconductor substrate side can be reduced.

In addition, the above effects can be achieved and the number of manufacturing processes for the semiconductor integrated circuit device 5 can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a DRAM which is Embodiment 2 of the present invention. FIG. 2 is a plan view of the main part of the DRAM, and FIG. 3 is a plan view of the main part of the DRAM which is Embodiment 2 of the present invention. In the figure, 1... semiconductor region, F... gate electrode, word line or shielding film, 12... lower layer electrode, 14... plate electrode or redundant fuse element, M... memory cell, QS . . . MISFET for memory cell selection, C . . . capacitive element for information storage, F . . . redundancy fuse element.

Claims (1)

[Scope of Claims] 1. A redundant circuit that has a DRAM composed of a memory cell formed by a series circuit of a memory cell selection MISFET and a stacked information storage capacitor element, and that rescues the memory cell. In a semiconductor integrated circuit device having a redundant fuse element that is cut by a laser cutting method, the redundant fuse element is the same as a plate electrode to which a fixed potential of a stacked information storage capacitor element of the memory cell is applied. A semiconductor integrated circuit device comprising a conductive layer. 2. The stacked structure information storage capacitive element is configured by sequentially stacking a first electrode connected to one semiconductor region of the memory cell selection MISFET, a dielectric film, and the plate electrode. The semiconductor integrated circuit device according to claim 1, characterized in that: 3. In a semiconductor integrated circuit device having a redundant fuse element cut by a redundant circuit laser cutting method on a semiconductor substrate, between the area of the redundant fuse element cut by the laser beam and the semiconductor substrate, the A semiconductor integrated circuit device comprising a shielding film that absorbs or reflects laser light. 4. The redundant circuit is an MIS for selecting DRAM memory cells.
It is used as a relief circuit for a memory cell composed of a series circuit of an FET and a stacked information storage capacitive element, and the redundant fuse element of the redundant circuit is connected to the upper layer electrode of one of the stacked information storage capacitive elements. 4. The semiconductor integrated circuit according to claim 3, wherein the shielding film is formed of the same conductive layer as the other lower electrode or the gate electrode of the memory cell selection MISFET. Device.