JPH0485646A - Bus interface controller - Google Patents

Abstract

PURPOSE:To prevent the deterioration of bus utilization efficiency by providing a slave operation control means, a bus contention recognition means, a write access storage means, and a master operation control means. CONSTITUTION:When a bus contention recognition means 33 recognizes that both first and second busses 21-1, 21-2 perform the access to the other bus, a slave operation control means 31-1 requires the release of the bus against a bus master trying to perform write access through a master operation control means 32-1. At this time, the write information is held in a write access storage means 34, and the execution of the write access which was not executed is performed after releasing the bus to which the slave to be written is connected by a master operation control means 32-1. Thus, the deterioration of the bus efficiency caused by invalidating either of bus access so as to prevent from turning to the state of dead lock is restrained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides an information processing device such as a computer that has two buses and performs operations across both buses. This invention relates to a bus interface control device that guarantees smooth operation even when attempting to access a bus slave connected to another bus at the same time.

(Prior art) Conventionally, this type of bus interface control device has
For example, there was something like Figure 2. The configuration will be explained below using figures.

FIG. 2 is a fifji block diagram showing an example of the configuration of an information processing device including a conventional bus interface control device.

This information processing device has a 17th and a 2nd bus 1-1.1.
-2, each of which has a processor 2-1 and a processor
．． 2-2, main storage device 3-1, 3-2, and bus monitoring devices 4-1 and 4-2 are connected. The connection between the first and second buses 1-1.1-2 is via the bus interface control device ]-0. They are connected to each other.

The bus interface control device 210 controls the bus interface controller 210.
] to control access to bus 1-2 side l\: slave operation: ln)-1°7-ra1. , ]-1 and the master operation controller 12-1, and the slave operation controller 1 that controls access from the bus 11''7 setters 2 to 2 to the bus ]-1 side.Roller 1F-2 and the master operation controller 12-1.
It is composed of 2.

In the following configuration C; 2, for example, the processors 2 to 1 are connected to the bus ink face control device 10L, ``for''
C + gg memory storage device 3-2 requests access to write-in, slave operation controller] 1-1 recognizes this, master operation controller / controller], 2-1 (, Z
However, it requests access to bus]-2. Then, when the bus monitoring device 4-3 monitors the bus 1-3,
When -2 is released, the master operation controller) -1:::y-
121, predetermined data is stored in the main memory bag'$3-
2 '\Written.

In this type of bus interface control device 104.7, the bus master (processor 2-1, 2-2) connected to both buses ], -], ... When trying to access the bus slave (main memory bag W3 2, 3 1) connected to the other bus,
In order to prevent a situation in which both bus masters wait for the other side's bus to be released and the information processing equipment stops operating (this state is referred to as a "deadlock state"), the following steps are taken: In other words, when the bus masters (processors 2-14, 2-2) connected to both buses 11.1=2 recognize that they are both trying to access the other bus, which one Deadlock is avoided by requesting the bus masters 1 to 1 to release buses i-1 and 1-2.

(Problem to be Solved by the Invention) However, in the device with the above configuration, in order to avoid deadlock, the bus master (processor 22) that is requested to release the bus, for example 1-2, releases the other bus 1-2. -1 (processor 2-1)
After the access to the bus slave (main memory 3.-1) of own bus 1-1 in 1) is completed, the same access must be executed again, so the bus]-
There is a problem that the usage efficiency of -1 and 1-2 is low.
It was difficult to solve it.

The present invention provides a bus interface control device for an information processing device that solves the problem of the prior art, which is a decrease in bus utilization efficiency.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides two different first
and has a function of accessing a second bus slave connected to the second bus in response to a request from a first bus master connected to the first bus. , a second bus connected to the second bus.
A bus interface control device for an information processing device having a function of accessing a second bus slave connected to the first bus in response to a request from a bus master, comprising at least the following means. .

That is, the bus ink face control device of the present invention recognizes that the first or second bus master is attempting to access the second or first bus, and a slave operation control 'l1 that responds to access from the above-mentioned bus master or the second bus master;
7- The slave operation means 2' recognizes that access is being made from the first and second bus masters based on the output of the non-troll means, and the recognition result C
Based on the slave operation: 1) to the roll means 5, when the access from either the first bus master or (J second bus master) is a write, the access is transferred to the corresponding second bus master. or a bus conflict recognition means for normally terminating only the first bus; and a line I for storing the address and data of the write access.
- access storage means, and the second or first . a master operation of participating in the bus arbitration CJ of the bus, and performing the speculative access using the address and data in the write access storage means after the C bus access is permitted and the second or second bus is released; control means.

(Function) According to the present invention C, ``L'', the G cobus interface 1.゛: When the bus conflict recognition means recognizes that an attempt is made to access the other bus, the recognition result is 4=M, and the slave operation controller I.1'?- is used to operate as a bus slave.
Master operation: C1
A request is sent to the bus master attempting to perform write access to release the bus. At this time, write information is held in the write access storage means.

Then, the unexecuted six-write access is executed by the master operation controller 1 stage after the bus to which the slave to which the write is to be written is connected is released.

This (from this), when the bus masters connected to both buses simultaneously try to access the bus slave connected to the other bus 6J, and both bus masters wait for the other bus to be released, the GZ dead 1-7 It is possible to suppress the decrease in bus efficiency caused by disabling bus access to either of the following states. Therefore, the above-mentioned problem can be solved.

Embodiment FIG. 1 shows an embodiment of the present invention, and is a functional block diagram of an information device including a bus interface control device.

This information processing device has first and second buses 211.21
-2, each of which has a processor 22-1 .
．． 22-2 and main storage device 231.23-2 are connected. and the first and second buses 21-1.21-2
are interconnected by a bus interface control device 30.

The bus interface control device 30 operates when the 11':l processor 22-1 becomes the first bus master of the first bus 21-1 and accesses the main storage device 23-2 of the second bus 21-2. , a slave operation control means 31-1 for becoming a slave for the first bus 21-1, and a master operation control means 32 for acting as a bus master for the second bus 21-2. -1.Furthermore, C=, the processor 22-2 has the first- bus 21.
Slave operation control for becoming a slave for the second bus 212 when becoming the bus master for the second bus 212 and accessing the first bus 2], the main memory bag for the second bus 23-] It has means 31-2, and a master operation controller/troller U132-2 for becoming a bus master for the first bus 21-1.

Slave operation control means 31-1. , ,31-
2 is connected to bus conflict recognition means 33 for recognizing that the WE is operating as a bus slave for both the first and second buses.

Furthermore, the slave operation control means 311.3]
-2, master operation control means 321, . 32-2
, and the bus conflict recognition means 33 are connected to a write access storage means 34, which is composed of a register or the like that stores the address and data of the access when the access from the bus master is a write.

Note that arrows a to ) in FIG. 1 indicate signal transmission directions, and a and d are signals ACKI at the time of reading.

DATAI, b, and c are signals BSYI during writing.

ASI,DSL,,,ADH8I,DATAl,,,e
h is the signal BSY2. AS2, DS2. ADR, S2゜D
ATA2, f, and g are the signals ACK2°DAT during reading.
A2,i are signals ADR,S1. DATA1 and j are signals ADR82 and DATA2.

The signal BSYI indicates that the bus 21-] is in use, the signal ASI indicates that the address signal is being applied to the bus 21-], and the signal DSL indicates that the bus 21-] is in use during writing.
-1 indicates that the bus master may output data and that the bus slave may output data to the bus 21-]- during reading. Signals ADH and SF are on bus 21-1
The signals D-TAU indicate the data on the bus 21-1, and the signal ACKI indicates that the bus slave on the bus 21-1 may terminate the bus access to the bus master.

Similarly, signal BS\2 indicates that bus 2]-2 is in use, and signal AS2 indicates that the address is output on bus 21-2. Signal 1] S2 indicates that the bus master may output data to bus 2], -2 during writing, and that the bus slave may output data to bus 21-2 during reading. . Signal ADR32 is on bus 21
-2 address, the signal DAi''A2 indicates the data on the bus 21-2, and the signal ACK2 indicates that the bus slave on the bus 21-2 may terminate the bus access to the bus master.

In addition, A and No. 1 C output from the bus conflict recognition f stage 33
0NF1. = ICT1, 2 are connected to both buses 21-1.2
This indicates that accesses from 1 and 2 are being made at the same time.

Signal WRI output from write access storage means 34
1"I:, ], 2 is a write signal.

FIG. 3 is a timing diagram showing the operation of the bus ink face control device 30 of FIG. 1, and the normal operation timing diagram of the bus signal of FIG. 3 is shown in FIG. There is.

As shown in FIG. 4, the normal operation of the bus signal is to
After asserting (aSSert, assertion or activation) SY to indicate that bus 21-1, 21-2 is in use, address signal ADR8 is output and signal AS is asserted. Furthermore, while asserting the signal DS,
If the access is for writing, a data signal DATA is output. When the slave asserts signals A and CK to indicate that it may terminate the bus access, it accepts the data in the case of a read and negates signals AS and DS (6n
egate, cancel), stop the output of the signal ADR8 and the signal DATA in the case of an interpolation, and output the signal l3.
Negate SY.

FIG. 5 shows a timing diagram in a normal case where there is no access conflict when the processor 22-2 connected to the bus 21-2 writes to the main storage device 23-1 connected to the bus 21-1. Shown below.

As shown in FIG. 5, processor B is BSYB, AS-
B,ADR,=B,DS-B is asserted to the bus interface controller to transmit the bus 22-2! When a request is made to write access to the connected main storage device 23-1, the slave operation control means 31-2 in the bus interface control device 30 recognizes this and requests the master operation control means 32-2. 21-1, and requests access to bus 21-1. Master operation:
1 (~roll means 32-2 receives signal B of bus 21-1)
SY1. AS1. ADH3I, DSL, and DATA1 are asserted to access the main storage device 23-1.

The main memory device 23-1 asserts the signal ACKI, and the bus interface control device 3 indicates that the write has been performed.
0, the master operation control means 3
2-2 is the signal ASI, ADR3I, DSL, DATA
It negates I and asserts signal ACK2 to notify processor 22-2 that writing has been performed. Processor 22-2 receives signal AS2. ADR
32, DS2, and DA'l'A2, and further negates the signal BSY2, the processor 2
2-2's access to the bus 21-2 ends. Further, the master operation control means 32-2 outputs the signal BSY.
By negating I), the bus interface control device 30's access to the bus 211 is terminated.

Next, for example, processor 22-1 accesses the ζ bus interface controller 30 via bus 2]-1, and further accesses the main Jj4 memory connected to bus 21-2. #23
2 and the operation of writing access to processor 22-2.
accesses the bus interface control device 30 via the bus 2]-2, and further performs read access to the main storage device 23-1- connected to the bus 2]-1.
The operation of the bus interface control device 30 when simultaneous occurrences (access conflicts) will be described.

First, the processor 22-1 outputs the signals BSYI, AS 1
, ADR81, I',',, )S 1 , DATA
] is asserted by the bus interface controller 30.
The main storage device 23 connected to the bus 21-2
At the same time as requesting write access to 2,
Processor 22-2 receives signal BSY2. AS2, Al moon S2. DS2 is asserted to request the bus interface control device 30 to access the main storage device 23-1 connected to the bus 2]-2 for reading 7.

Slave operation within bus interface control device 30: 1
control means 31-1 and 3]- to -2+, i, 1 for bus conflict recognition means 33, first and second bus 21-
1. Notify that access from 21-2 has failed. Bus conflict identifier “U, 33 is 1 for both buses 2]
When it is recognized that accesses from -1 and 21-2 are being made together, a signal C0 indicating that accesses from buses 21-]4 and 21-2 of both nodes j are being made.
NFL, ICT] as slave operation control means 3
1-1 and write access storage means 34 =
1. Do it.

The slave operation control means 31-1 is connected to the bus 2]-
The signal ACKI is asserted to the processor 22-1, which is the bus master of No. 1, to notify that the writing has been completed. Then, the write access storage means 22-1 holds the address and data to be written, and further asserts the signals WR and ITE2 to request the master operation control means 321 to write to the main memory 23-2/\. is requested to be performed using the address and data in the write access storage means 34.

The slave operation control means 31-1 receives the signal ACKI.
When the processor 22-1 asserts this to indicate that writing has been performed to the processor 22-1, the processor 22-1 immediately releases the bus 21-1.

As a result, the master operation control means 322 outputs the signals BSY 1 , AS 1 , ADR8,1, II)
S] is asserted to become the bus master of the bus 21-1, and the main memory 2 requested by the processor 22-2 is
3-1. The main storage device 23-1 outputs the signal DATAI, and the signals A, CK, 1
When the bus interface control device 30 is notified that writing has been performed by asserting the
) R81, 1) St- is negated)-, and further signal DA
It outputs 'l'A2 and asserts signal ACK2 to notify processor 22-2 CZ that reading has been performed.

The PX7 setter 22-2 receives the signal AS2. Al1) R, S2
゜I) By setting S2 to negation 1 and further negating signal BSY2, the access of the processor 22-2 to the bus 212 is terminated. Further, when the master operation control means 32-2 negates the signal BSY1, the access of the bus interface control device 30 to the bus 21-2 ends.

When processor 22-2 releases bus 21-2, master operation control stage 32-1 sends signals BSY2. AS2. ADR32, DS2. D.A.
Asserts TA2 to become the bus master of the bus 21-2, and performs the write access to the main memory 23-2 requested by the processor 22-1 using the address and data in the write access storage means 34. . When the main memory device 23-2 generates a signal ACK2 and notifies the bus interface control device 30 that writing has been performed, the master operation control means 3
2-1 is the signal AS2, ADR32゜]S2.1m)
By negating A'l''1' A2, the bus interface control device 30's access to the bus 21-2 is terminated.

Therefore, not only the bus utilization efficiency is improved, but also the bus access can be terminated without causing access contention, making the bus master wait, or requiring the same access to be made again.

It should be noted that the present invention is not limited to the embodiments described above, but can be modified in various ways. Examples of such modifications include the following.

(a,) The above embodiment is applied when at least one of the accesses is a write operation, and the above-described operations and effects can be obtained.

([)> FIG. 6 shows another embodiment of the present invention, and is a configuration block diagram of an information processing device including a bus interface control device.

As shown in this figure, in the embodiment of FIG.
Memory Access) transfer device 24-4.2
This also applies to devices with a bus master function such as 4-2. Furthermore, the bus slaves of the first and second buses 21121-2 include the disk devices 25-1 and 25-2 other than the main storage device 23-123-2 and the input/output device 26-1.
, 26-2, etc., which have a bus slave function.

(Effects of the Invention) As described in detail below, according to the present invention, there is provided a slave operation control means, a bus contention recognition means, a write access storage means, and a master operation control means. Therefore, even when accesses from the first and second bus masters conflict, the bus access can be terminated without making the bus masters wait or requesting them to perform the same access again. Therefore, it is possible to accurately prevent a decrease in bus utilization efficiency caused by disabling one of the bus accesses in order to prevent a deadlock state, thereby improving bus utilization efficiency.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of an information processing device including a bus interface control device according to an embodiment of the present invention, FIG. 2 is a functional block diagram of an information processing device including a conventional bus interface control device, and FIG. 3 is a timing diagram of the bus interface control device in Fig. 1, and Fig. 4 (a) and (b) are timing diagrams of the bus interface control device in Fig.
FIG. 5 is a timing diagram of the bus interface control device of FIG. 3 when there is no contention for access, and FIG. 6 is a bus interface control diagram showing another embodiment of the present invention. 1 is a configuration block diagram of an information processing device including the device. FIG. 21-1.21-2...1st. second bus, 2
2-1. ,． 22-2... Processor, 23-
1-. 23-2... Main storage device, 24-1.2
4-2...1,'l MA transfer device, 25-
1.25-2...Disk device, 30...
...Bus interface control device, 31-1 31-2
......Slave operation: 1-in-I roll means, 32
-1.32-2... Master operation control l-roll means, 33... Bus conflict recognition means, 34...
...Write access storage means.

Claims (1)

Claims: Connected to two different first and second buses, at the request of a first bus master connected to said first bus,
It has a function of accessing a second bus slave connected to the second bus, and is connected to the first bus at the request of a second bus master connected to the second bus. In an information processing device having a function of accessing a second bus slave, the first or second bus master may access the second or first bus slave.
slave operation control means that recognizes that the bus is about to be accessed and responds to the access from the first or second bus master; and based on the output of the slave operation control means, It recognizes that access is being made from the first and second bus masters, controls the slave operation control means based on the recognition result, and controls access from at least one of the first and second bus masters to write. bus conflict recognition means for normally terminating the access only for the corresponding second or first bus when the access occurs; write access storage means for storing the address and data of the write access; and the second access destination. or a master that participates in bus arbitration of a first bus, is granted bus access, and performs the write access using the address and data in the write access storage means after the second or first bus is released; A bus interface control device comprising: operation control means.