JP3237569B2 - Memory access control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory access control device, and more particularly to a memory access control device for controlling an inter-processor synchronization instruction in a multiprocessor system.

[0002]

2. Description of the Related Art As a method of controlling access from a plurality of processing units (processors) to a memory having a plurality of banks, a state of a bank is determined to avoid access to a busy bank, and other than a busy state. A method of prioritizing access to a bank is known. An example is shown below.

[0003] Access to the memory is a read instruction,
It is classified into three types: a write instruction and a clear instruction. The read command reads data from the memory, and the write command writes data to the memory. The clear instruction is an instruction used for synchronous control in a multiprocessor system, and performs an operation of reading from a memory and writing immediately after that.
In a multiprocessor system, a technique is known in which a desired shared area is locked in advance in order to guarantee a memory update order. A clear command is used to secure this lock. More specifically, reading is performed from a specified address in the memory, the read data is returned to the request source, and the address is cleared to zero. The request source checks the read data, and if the value is not zero, determines that the lock was successfully secured. if,
If the value is zero, it is determined that the area is locked and cannot be updated.

Referring to FIG. 6, a bank access period is shifted between a read instruction and a write instruction. this is,
This is because a read instruction performs memory access when an address is transferred, whereas a write instruction performs memory access after data is transferred. During the access period in FIG. 6, the corresponding memory bank is busy and cannot receive another access. In order to avoid access to a busy bank, a method is used in which a bank busy flag is provided, and when this flag is set, issue of an instruction to the corresponding bank is suppressed.

Referring to FIG. 7, a conventional memory access control device is applied to a module in each processor in a multiprocessor system. In each module, the storage queue 201 stores read, write, and clear transactions. The storage queue 201 has a FIFO structure, and issues a transaction located at the head of the queue using the request line 203.

The request masking section 205 masks a read request for a bank which has been notified of the busy state by the read bank busy signal 215, and outputs other read requests by a read issue request signal 208. The request mask units 206 and 207 mask the write and clear requests for the banks for which the busy is notified by the clear bank busy signal 216, and request the other banks for the write issue request signal 209 and the clear issue request signal 210. Output as

The bus request control unit 211 takes in the transaction issue request signals 208 to 210, selects the bus with the highest issue priority for the bus, and notifies the request register 219 and the transaction register 218 respectively. Request register 219
Is notified to all modules on the bus via the bus request line 224.

[0008] The bus arbiter 212 gives a bus use right to any of the modules which have made a request by the request input registers 220 and 221. The bus arbiter 212 notifies the bank busy control unit 214 of the type of transaction issued to the bus and the access bank via the notification line 213.

The bank busy control unit 214 determines the period during which bank access occurs according to the type of transaction issued to the bus, makes a bank busy determination for read and clear transactions, and reads a read bank busy signal 215 and a clear bank busy signal. 216 is output.

Referring to FIG. 8, in order to guarantee the bank access timing of FIG. 6, it is necessary to follow a predetermined bank busy signal. In the example of FIG. 8, two types of memory bank busy flags are used: a read bank busy for inhibiting the issuance of a read instruction and a clear bank busy for inhibiting the issuance of a write instruction and a clear instruction. Here, one bus cycle is assumed to be four clocks. Therefore, the timing at which a request can be issued in FIG. 8 is the clocks T1, T5, T9, T11 and the like.

However, according to this method, the memory bank busy flag to be referred to at the time of issuing the write instruction is
Since the same flag as the flag to be referred to at the time of issuing the clear instruction is set, there is a problem that the issuance of the write instruction is suppressed although the write instruction can be issued originally.

Referring to FIG. 9, in this example, as a memory bank busy flag, a read bank busy for inhibiting issuance of a read instruction, a clear bank busy for inhibiting issuance of a clear instruction, and issuance of a write instruction. Use light bank busy to ban. According to this method, since the clear bank busy period is longer than the other two instructions, the issue of the clear instruction is prohibited, but the issue of the read instruction or the write instruction may be possible.
The issue of these two instructions causes a problem that the clear bank busy period is continued and the clear instruction cannot be issued on the bus for a long time.

Referring to FIG. 10, as an example in which a clear instruction for a specific bank cannot be issued for a long time, a case where a read instruction and a write instruction are issued alternately is shown. When a read instruction is issued at T1, the bank becomes a read / clear bank busy. When the write instruction is issued at T4, the clear instruction cannot be issued because the clear bank busy is continued. Further, at T9, a read command is issued by canceling the read bank busy, and the clear bank busy is further continued. Thereafter, the read command and the write command are alternately issued to a specific bank in this manner, and the clear bank busy is not released, so that a case where the clear command cannot be issued may occur.

[0014]

In the above-mentioned prior art,
When the bank busy of the memory is determined for each of the three types of memory access instructions, if a read instruction and a write instruction continue for a specific bank, the bank busy state for the clear instruction is continued as described above, and the clear operation is performed. Instructions may not be issued. To prevent this, it is conceivable to use the same bank busy signal when determining the bank busy for the write instruction and the clear instruction. However, in this case, there is a possibility that the issuance of a write instruction to a non-busy bank may be suppressed, and the bus cannot be used efficiently.

It is an object of the present invention to improve the performance by efficiently issuing a memory access instruction on a bus by optimizing a memory bank busy determination condition at the time of issuing a memory access instruction.

[0016]

In order to solve the above problems, a memory access control device according to the present invention is a multiprocessor system having a plurality of processors and a shared memory, wherein the shared memory has a plurality of memory banks. Each of the plurality of processors monitors a read transaction for reading from the memory, a write transaction for writing to the memory, and a clear transaction for reading from the memory and writing immediately after the read transaction. a bank busy control unit for managing the status of said plurality of memory banks for each transaction, when the clear transaction in the processor is in the predetermined period issues waiting for the bank busy memory bank to be accessed, wherein Ba
Other than the clear transaction of the link busy control unit
Said clear transaction for the transaction of
The management status of the memory bank
A pseudo-request control unit for issuing a request for making a busy state .

In another memory access control device of the present invention, when the request is issued by the pseudo request control unit, the bank busy control unit prohibits access of a transaction other than the clear transaction. I do.

In another memory access control device according to the present invention, when the request is issued by the pseudo-request control unit, the bank busy control unit, when the processor issues the request, relates to the request. For a bank, access to a read transaction and a write transaction is prohibited until the next clear transaction is issued, and when another processor issues the request, the next clear transaction is issued for the bank related to the request. Until the access, read transaction, clear transaction, and write transaction access is prohibited

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the memory access control device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an embodiment of the memory access control device according to the present invention is applied to a multiprocessor system including modules 301 to 303 included in n processors and a memory 311 shared by these modules. Applied. Memory 311 includes n banks. A shared bus 310 exists between the modules 301 to 303 and the memory 311.

When there is a transaction using the common bus 310 in each module, each module uses the bus request lines 304 to 306 to send the transaction to be issued to all the modules on the bus. The type and the bank number to be accessed are notified. In each module connected on the shared bus, a determination is made by a bus arbiter existing in the module, and only one module in the system secures the right to use the bus.
The module which has secured the right to use the bus issues a transaction on the bus 310. Here, the operation via the bus is called a transaction, but these are also called instructions in the processing in the processor. A transaction issued from a processor is also called a request.

Referring to FIG. 2, an embodiment of the memory access control device of the present invention exists in each module. Here, a description will be given of a system having two modules, a module 0 and a module 1. The storage queue 101 stores a read transaction, a write transaction, and a clear transaction. The storage queue 101 has a FIFO structure, and outputs at most one transaction at the same time via the request line 103. As a result, the order in which valid transactions are issued within the storage queue 101 is guaranteed. Here, the request line 103 includes a request enable signal and a memory bank number to be accessed.

The request mask units 105 to 107 take in the request lines 103 and 104, the read bank busy line 121, the write bank busy line 122, and the clear bank busy line 123, and thereby store the memory for the busy bank. Mask the access transaction request. The request mask unit 105 performs a request mask of a read transaction by the read bank busy signal 121. Similarly, the request mask units 106 and 107 mask a write transaction and a clear transaction, respectively.

The pseudo-busy request control unit 112 monitors the request line 103 to determine if a clear transaction to the same bank has been requested for a certain period or more (for example, several tens to several hundreds of bus cycles). Determines that the issuance of the same clear transaction is still pending. In this case, the pseudo busy request control unit 112
The pseudo busy request line 113 outputs the pseudo busy request and the bank number. The pseudo busy request has a function of, when a clear instruction for a certain memory bank cannot be issued for a certain period of time or more, for other than the clear instruction, determining that the memory bank is busy. This pseudo busy request is issued regardless of the state of the bank busy signals 121 to 123, that is, is issued preferentially.

When the clear instruction is issued after the pseudo busy request is issued, the pseudo busy state is released. The pseudo busy request register 116 holds the pseudo busy request output from the pseudo busy request control unit 112 and the bank number, and notifies the modules 0 and 1 via the notification line 136.

The bus request control unit 111 performs arbitration between transactions by the request lines 108 to 110, and notifies all the modules on the bus that a transaction is issued from the module. The transaction selected by the bus request control unit 111 is held in the transaction register 114, and the type and bank number of the transaction are held in the request register 115. The request register 115 notifies all the modules of the transaction for which the own module has issued the issuance request and the bank number thereof via the notification line 134.

Request input registers 126 and 127
Holds requests from its own module (module 0) and another module (module 1) and notifies the bus arbiter 117 using the notification lines 130 and 131. The bus arbiter 117 arbitrates the requested transaction on the bus 310 and determines a module having the right to use the bus. The arbitration in the bus arbiter 117 gives the bus requesting the module requesting the highest priority transaction. Further, when transactions having the same priority are requested from a plurality of modules, the right to use the bus is given to the module having the highest module priority.

The module priority is determined by simple round robin for each bus arbitration. That is, the module that has acquired the bus last time has the lowest module priority among all the modules next time. The priority of transactions in the bus arbiter is highest for clear transactions, second for read transactions, and lowest for write transactions.

When it is determined that the module has acquired the right to use the bus by arbitration in the bus arbiter, the output enable line 118 is asserted,
A transaction is issued from the transaction register 114 onto the bus 310. In addition, bus arbiter 1
Reference numeral 17 notifies the bank busy control unit 120 of the type of transaction issued to the bus and the bank number to be accessed via the notification line 119.

The bank busy control unit 120 determines the type of the transaction issued to the bus and the bank number.
The access period of the transaction to each bank is determined, and a bank busy determination is performed for each memory access transaction. In addition, the bank busy control unit 12
0 is the pseudo busy request input registers 124 and 1
Monitor 25. As a result, after the module itself issues the pseudo busy request, the bank related to the pseudo busy request is imitated for the read transaction and the write transaction until the next clear instruction is issued. It is determined that it is busy. On the other hand, after the other module has issued the pseudo busy request, the bank related to the pseudo busy request is kept until the next clear instruction is issued.
It is determined that the read transaction, the clear transaction, and the write transaction are in a pseudo busy state.

Referring to FIG. 3, the bank busy control unit 1
20 includes a pseudo busy request determination unit 401 and a transaction access busy determination unit 402. The pseudo busy request determination unit 401 monitors the pseudo busy request input registers 124 and 125,
It is detected that the pseudo busy request is notified by the module 0 or the module 1, and in that case, the bank is determined to be in a busy state, and the busy signals 408 and 4
09, the corresponding bank busy signal is asserted. When the pseudo busy request determination unit 401 recognizes that the own module has issued the pseudo busy request, the pseudo request request unit 4 indicates that the pseudo module is the own module at the same time as the busy lines 408 and 409.
Assert any one of 06 and 407. The busy signals 408 and 409 and the own request signals 406 and 407 are signals corresponding to each bank constituting the memory. The assertion of the busy lines 408 and 409 and the own request lines 406 and 407 of each bank to which the pseudo busy request has been made is notified by the notification line 405 that a clear transaction has been issued to the bank for which busy determination is being performed. Continue until

Transaction access busy determination section 4
02 receives the notification of the type of transaction and the bank number issued from the bus arbiter 117 to the bus 310 via the notification line 119, makes a busy determination of the corresponding bank, and makes a busy signal 410 to 415 for each bank and each transaction. Assert Busy signals 410 to 411 are busy signals for each bank for a read transaction, and 412 to 413 are busy signals for each bank for a clear transaction.
5 is a busy signal of each bank for a write transaction. A signal that is the logical sum of the busy signal of each bank for the read transaction, the clear transaction, and the write transaction and the busy signal of each bank by the pseudo busy request determination unit 401 is:
The request mask unit 1 includes read bank busy signals 416 and 417, clear bank busy signals 418 and 419, and write bank busy signals 420 and 421.
05 to 107 are notified. However, the clear bank busy signal for the bank to which the pseudo busy request has been made is masked by the own request signals 406 and 407.

Next, the operation of the above embodiment of the present invention will be described.

Referring to FIGS. 2 and 4, module 0
Read transaction at the head of the storage queue 101,
Next, when a clear transaction is stored and a write transaction is stored at the head of the storage queue 101 of the module 1, arbitration is performed in the bus request control unit 111 in each module. When the module 0 secures the right to use the bus, the read transaction is stored in the request register at T1 and notified to the modules on the bus 310. The request for this read transaction is T
2 is stored in the request input register 127. The bus arbiter 117 in the module 0 performs arbitration of the request stored in the request input register 127 at T2, determines that it has the right to use the bus itself, and asserts the output enable line at T3 to store the request in the transaction register. The issued read transaction is issued on the bus 310. Further, the bus arbiter 117 notifies the bank busy control unit 120 of the type of transaction issued to the bus and the bank number to be accessed at T3.

Receiving the notification from the bus arbiter 117, the bank busy control unit 120 makes a busy determination for the relevant bank, and asserts the busy lines 119 and 121 from T4. As a result, the request for the bank to which the busy state is notified is masked at T4, and the request is not output to the bus request control unit 111. At time T4, there is a clear transaction in module 0, but the clear transaction is masked by clear bank busy signal 121. on the other hand,
In the module 1, the bus request control unit 111
Is notified of a write transaction request. Thus, the write transaction request is notified to all modules at T5. This write transaction is issued on the bus at T7.

Since the clear bank busy state continues, the request for the clear transaction remains masked, and the request from the module 0 disappears. Since clear bank busy is released at T20,
A request for a clear transaction is made at T21, and issued on the bus at T23.

Referring to FIGS. 2 and 5, as another example,
If a clear transaction comes to the head of the storage queue 101 of any module on the bus 310 while read and write transactions for the same bank are continuously issued, the request for the clear transaction continues to be masked. The pseudo busy request control unit 112 of the module determines that the clear transaction is still pending at T81, and makes a pseudo busy request. The pseudo busy request is
The notification is sent to the bus 310 at T82, and is stored in the pseudo busy request input register of each module at T83.

The bank busy control units 120 of all the modules on the bus 310 other than the module that has made the pseudo busy request receive the pseudo busy request and
From 4, the read bank busy, clear bank busy, and write bank busy of the corresponding bank are asserted. Also, the bank busy control unit 120 of the module that has issued the pseudo busy request starts to assert read bank busy and write bank busy for the bank.
As a result, in the former case, the request of each transaction of read, clear, and write to the corresponding bank is masked, and in the latter, the request of each transaction of read and write to the corresponding bank are masked. As a result, the memory access transaction for the bank is not issued after the pseudo busy request, and the clear bank busy is deasserted at T90 only in the module that has made the pseudo busy request.
As a result, the mask of the pending clear transaction is released, and a clear transaction for the corresponding bank or a write transaction for another bank is output to the bus request control unit 111.

The bus request control unit 111 selects a clear transaction according to the priority of the request, and issues a clear transaction request to the bus 310 at T94. If there is no other module requesting a clear transaction at T94, a clear transaction can always be issued at T97 based on the transaction priority in the bus arbiter. When a request for a clear instruction to a bank other than the bank concerned is issued after T94, the bus may be robbed by other modules. Since the priority time always comes, a clear transaction can always be issued at that time.

As described above, according to the embodiment of the present invention, if a clear transaction is not issued at the head of the storage queue 101 for a certain period, the pseudo busy request control unit 112 issues a pseudo busy, thereby allowing other transactions to be executed. And the clear transaction can be issued preferentially.

[0046]

As apparent from the above description, according to the present invention, a clear transaction can be saved from a deadlock by issuing a pseudo busy request. Further, it is possible to suppress the issuance of the write transaction due to the bank busy only when the bank is actually busy, and the bus use efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a multiprocessor system to which a memory access control device of the present invention is applied.

FIG. 2 is a diagram illustrating a configuration of an embodiment of a memory access control device of the present invention.

FIG. 3 is a diagram showing a configuration of a bank busy control unit in the memory access control device of the present invention.

FIG. 4 is a diagram showing the timing of a normal request in the memory access control device of the present invention.

FIG. 5 is a diagram showing the timing of a pseudo busy request in the memory access control device of the present invention.

FIG. 6 is a diagram showing a bank access period for a normal request in the memory access control device of the present invention.

FIG. 7 is a diagram illustrating a configuration of a conventional memory access control device.

FIG. 8 is a diagram showing timing when two types of bank busy signals are used.

FIG. 9 is a diagram showing timing when three types of bank busy signals are used.

FIG. 10 is a diagram for explaining a problem when three types of bank busy signals are used.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Storage queue 105-107 Request mask part 111 Bus request control part 112 Pseudo busy request control part 120 Bank busy control part 117 Bus arbiter 301-303 Module 310 Shared bus 311 Memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16-13/18 G06F 15/16-15/177

Claims (3)

(57) [Claims] 1. A multiprocessor system having a plurality of processors and a shared memory, wherein the shared memory has a plurality of memory banks, each of the plurality of processors has a read transaction for reading from a memory,
A write transaction for writing to memory,
A bank busy control unit that monitors a clear transaction that reads from a memory and writes immediately after that, and manages the state of the plurality of memory banks for each transaction; and the clear transaction attempts to access the processor in the processor. If that is the predetermined period issues waiting for the bank busy memory bank, the bank
Other than the clear transaction,
The clear transaction for a transaction
The management status of the memory bank
A pseudo-request control unit for issuing a request to set the memory access state. 2. The bank busy control unit, when the request is issued by the pseudo request control unit,
2. The memory access control device according to claim 1, wherein access of a transaction other than the clear transaction is prohibited. 3. The bank busy control unit, when the request is issued by the pseudo request control unit,
When the own processor issues the request, the access of the read transaction and the write transaction is prohibited until the next clear transaction is issued for the bank related to the request, and the other processor issues the request. And prohibiting access of a read transaction, a clear transaction, and a write transaction for a bank related to the request until a next clear transaction is issued.
A memory access control device according to claim 1.