JPH0484458A - Memory cell - Google Patents

Abstract

PURPOSE:To obtain low consumption SRAM by forming an insulation film which is a capacitor and a conductor film which is an electrode of said capacitor on the upper layer of the conductor film which is a gate electrode of a memory transistor and connecting electrically a part of the conductor film which is the electrode of the capacitor with GND. CONSTITUTION:After the formation of memory transistors 6 and 7 with access transistors 9 and 10, the gate electrodes of the memory transistors are formed with a Poly - Si film where an SiO2 is further formed on the upper layer based on a thermal oxidation method. Then, a Poly - Si film is formed so as to serve as an electrode of a capacitor. Only the portion which can be used as the electrode of the capacitor on the upper layer of the gate electrodes of the memory transistors 6 and 7 are patterned. As it is arranged that the electric charge required to write in memory be stored in the capacitor 18, it is possible to expand the margin capable of maintaining the level of H for a connection point 5. This construction makes it possible to obtain a memory cell which reduces standby current and low consumption power of SRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory cell, and particularly to a memory cell of a static type memory (hereinafter referred to as SRAM).

[Conventional technology]

FIG. 2(a) is an equivalent circuit diagram of a memory cell of a high resistance load type SRAM according to the prior art, FIG. 2(b) is a pattern layout diagram within the cell, and FIG. 2(C) is a diagram of the pattern layout diagram. It is a sectional view taken along the line aa'.

In the figure, 1 is a power supply (Vcc), 2.3 is a high resistance element, 4.5 is a high resistance element 2.3 and a memory transistor 6.
7 and the connection point with access transistor 9゜10, 8
is GND (Vs s), 11 is the word line, 12.
13 is a bit line, 20 is a silicon substrate, 21 is a field oxide film for element isolation, 22 is a source/drain region of a memory transistor 6.7 and an access transistor 9.10, and 23 is a memory transistor 6.7 and an access transistor 910 is a 5in2 film which becomes a gate oxide film, and 24 is a polysilicon Il! which becomes a gate electrode of a memory transistor 6.7 and an access transistor 9.10. (hereinafter referred to as Pol!ySi film), 27
is an interlayer insulating film, and is made of, for example, a SiO□ film. 28
Pony-3i is a conductive film for wiring the power supply (Vcc) wiring and the gate electrode of the memory transistor 6 and the source/drain region of the memory transistor 7.
Consists of a membrane. 29 is an insulating film between the eyebrows, for example, StO□
Consists of a membrane. 30 is Po1ly-3i which is a high resistance element
The film 31 is an interlayer insulating film, for example, phosphorus silicate glass (Phospho-5 silicate glass).
32 is an aluminum film for the bit lines 1-2, 13, etc.

Next, the manufacturing method will be explained using FIG. 3.

First, field oxidation 1121 for isolation between elements is formed on a silicon substrate 20 using the LOCO3 method, for example.
After forming the gate oxide film 23 to a thickness of
For example, Pofy-Si824 is formed to a thickness of 250 mm using a thermal oxidation method, and then Pofy-Si824 is formed using a CVD method to a thickness of 300 mm.
The resist layers are laminated to a thickness of 0.0 mm, and a resist pattern is formed using photolithography only on the portion that will become the gate electrode of the transistor (FIG. 3(a)).

Next, use Poi as a resist mask! , the Y-81 film 24 is etched using dry etching technology to form Pany-3.
Using ion implantation technology on the entire surface using the i film as a mask, As
is implanted to form an N° diffusion layer which will become the source/drain region of the transistor (FIG. 3(b)).

Next, a 5iOz film 27, which will become an interlayer insulating film, is coated with, for example, 3000 oz.
For example, the N layer of the transistor is formed with a thickness of about 20 mm
After forming a contact hole for electrical connection with the Pofy-3iWA28 with a thickness of 0.00 mm using photolithography and dry etching technology, the Pofy-3iWA28 is
A 1ly-3i film 28 is deposited over the entire surface, and a resist pattern is formed only in the areas necessary for wiring (Fig. 3(C)).
).

Next, a 5iOz film 29 that will become an insulating film between the eyebrows is laminated to a thickness of, for example, 3,000 layers using the CVD method, and a resist pattern is formed in the part that will become a high-resistance element (FIG. 3(d)).
.

Next, using the resist pattern as a mask, P01! ,y
-3i film 31 is deposited to a thickness of, for example, 1,500 by CVD, and then Af#32, which will become wiring, is deposited by sputtering.
For example, a resist pattern is formed in the areas necessary for wiring (Fig. 3(e)).
.

Finally, the A1 film 32 is dry etched as shown in FIG.
) to form a conventional memory cell with a cross-sectional structure.

In addition, the operation of such a high resistance load type SRAM is
This will be explained using figures.

First, the read operation is as follows.

That is, when reading data from a memory cell, the bit line (Ilo, l10) connected to the power supply and load is charged to an appropriate potential in advance, and a positive voltage is applied to the word line to open the access gates Q3 and Q4. The “L” side drive transistor Ql (or Q
By discharging the charge charged to the bit line in 2),
The potential of the bit line connected to the "L" side is made lower than the potential of the focus line connected to the H side, and the data of the memory cell is transmitted to the bit line.

At this time, load transistors Q5 and Q6 connected to the bit line
has a lower resistance than the memory cell load R1 (R2),
Even if the "L" side drive transistor Q1 (Q2) is discharged, the potential of the node Nl (N2) does not reach the initial "L" level (!=:OV) but becomes slightly higher. Therefore,
Q2 (Ql) is also slightly conductive, and node N2 on the "'H" side
The level of (Nl) also becomes slightly lower. That is, node N
The potential difference between 1 and N2 becomes smaller. However, when the read is completed and the word line is set to O■ and the access gate is closed,
The flip-flop circuit of the memory cell automatically
1 is a complete “L” side (“H”) side, N2 is a complete “H” side
('°L'') and the contents of the memory are not destroyed. That is, in this case, non-destructive reading is performed.

Then, the write operation is as follows. That is,
To write data to memory cells, use the access game)Q
3. Q4 is made conductive, and Ql5°Ql6 or Ql7.
By forcing one of the bit lines to the "L" level using a write data driver composed of QlB, the potentials of the storage nodes Nl and N2 of the cell are forcibly set.

For example, when the node N1 is in the "H" state and the node N2 is in the "L" state as an initial state, in order to rewrite this data, Q15. The potential of the node N1 is forcibly lowered to "L" by pulling down the bit line connected to the access gate Q3 to the "L" level (1V or less) using the write driver formed by Q16.

On the other hand, the bit line connected to the access gate Q4 is
Since it is at precharge level (high potential), node N1
When the driver transistor Q2 becomes non-conductive due to the decrease in the potential of the node N2, the potential of the node N2 rises to 11H''.
/F is inverted and writing is completed. Access gate Q3 again. After closing Q4, this new cell state is maintained as a stable state.

In the above-described high resistance load type SRAM memory cell, power consumption during memory retention is determined by the resistance value of the high resistance element 23. In other words, the higher the resistance value, the lower the standby current, making it possible to create a memory with low power consumption. Therefore, in order to increase the capacity in a small area, it is necessary to further increase the resistance value.

[Problems to be Solved by the Invention] A conventional high resistance load type SRAM memory cell is configured as described above, and its resistance value is, for example, IOTΩ to 50 TΩ. By the way, this high resistance load type SR
In AM, in order to reduce the current (standby current) during memory retention and obtain a memory with low power consumption, it is necessary to increase the resistance value of the high resistance element 2.3.

However, if the high resistance element 2.3 is made too high, the standby current flowing through the high resistance element will decrease due to leakage current from the memory transistor, making it impossible to hold the memory. Therefore, there is a problem that the value of the high resistance element can only be increased to a certain extent.

This invention was made to solve the above-mentioned problems, and by forming a capacitor in the memory cell to store charge for holding the memory, even if the standby current approaches the leakage current of the memory transistor. , the purpose is to obtain a memory cell that can hold memory.

[Means to solve the problem]

A memory cell according to the present invention has an insulating film that becomes a capacitor and a conductive film that becomes an electrode of the capacitor formed on an upper layer of a conductive film that becomes a gate electrode of a memory transistor, and one part of the conductive film that becomes an electrode of the capacitor. electrically connect to GND
It is designed to connect to the

[Function] In the memory cell according to the present invention, an insulating film serving as a capacitor and a conductive film serving as an electrode of the capacitor are formed on the gate electrode of the memory transistor, so that the charge during memory storage can be increased. Memory can be retained even if the standby current is reduced by increasing the resistance value of the high-resistance element.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figure (a) shows a high resistance load type SRA according to an embodiment of the present invention.
FIG. 1(b) is an equivalent circuit diagram of a memory cell of M, FIG. 1(b) is a pattern layout diagram in the cell, and FIG. 1(C) is a sectional view taken along line a-a' of the pattern layout diagram.

In the figure, the same symbols as in Figure 2 indicate the same things, and 1
7. 18 is a capacitor for storing charge during memory storage; 25 is an insulating film for forming the capacitor;
For example, it is made of S 10 z film.

Reference numeral 26 denotes a conductive IIT film serving as an electrode of the capacitor, and is made of, for example, a Pony-3i film.

Next, a method for manufacturing the capacitor portion will be explained. Memory transistor 6.7 and access transistor 9.
After forming the gate electrode 10, the gate electrode of the memory transistor is formed using, for example, a Pofy-3i film, and then a SiC2 film is formed on the upper layer thereof by a thermal oxidation method.

Next, a Pony-3i film to be used as a capacitor electrode is formed, and only the portion of the upper layer of the gate electrode of the memory transistor 6.7 that is desired to be used as the capacitor electrode is patterned. Thereafter, a memory cell is manufactured by forming the same as a conventional memory cell.

In this embodiment, a conventional high-resistance load type is used to increase the capacity in a small area, and a high-resistance element with a high resistance value is used to reduce standby current and enable a memory with low power consumption.
In order to obtain the potential of the memory transistors 6.7 that enables memory retention even if the memory transistors 6.
For example, there are 3,000 people in the upper layer of 7, and 5 with a depth of 2,000 people.
102M25. Pol! By stacking the capacitors 17 and 18 made of the y-3i film 26, the cell area does not increase.

Next, the memory operation of the high resistance load type SRAM according to this embodiment will be explained in detail. For example, memory transistor 6 is ON
Assuming that the memory transistor 7 is in the OFF state, the standby current of the memory cell is determined by the current value that can flow through the high resistance element 2. On the other hand, since the memory transistor 7 is in the OFF state, the potential at the connection point 5 between the high resistance element 3 and the memory transistor 7 is determined by resistance division based on the leakage current of the memory transistor 7 to GND 8 and the current value that the high resistance element 3 can flow. be done.

In order to continue to maintain the ON state of the memory transistor 6, the leakage current value of the memory transistor must be controlled by the high resistance element 3.
Do not exceed the current value that can flow. However, recently, efforts have been made to reduce the standby current more and more, and the leakage current of the memory transistor 7 and the current value that can flow through the high resistance element 3 are approaching each other. Therefore, in order to maintain this state, the charge at the time of writing into the memory is also stored in the capacitor 18, so that the margin for maintaining the H level of the connection point 5 can be expanded.

In this embodiment, a capacitor is formed between the memory transistor and the high resistance element in the memory cell of the high resistance load type SRAM, so that the ON state of the memory transistor can be maintained for a long time. , a memory cell with reduced standby current can be obtained, and an SRAM with lower power consumption can be obtained without changing the cell area.

〔Effect of the invention〕

As described above, according to the memory cell according to the present invention, since the memory cell is configured by forming an insulating film and a conductive film serving as the gate electrode of the capacitor on the upper layer of the gate electrode of the memory transistor, the area of the memory cell can be reduced. Nothing to change (
, an SRAM with less standby current and lower power consumption can be obtained.

[Brief explanation of drawings]

FIG. 1 shows a high resistance load type SRA according to an embodiment of the present invention.
1(a) is its equivalent circuit diagram, FIG. 1(b) is a pattern layout diagram in the cell, and FIG. 1(C) is a-a of the pattern layout diagram. a
Figure 2 is a diagram showing a memory cell of a conventional high resistance load type SRAM, and Figure 2 (a) is its equivalent circuit diagram.
FIG. 2(b) is a pattern layout diagram inside the cell, FIG. 2(C) is a cross-sectional view taken along the line a-a" of the pattern layout diagram, and FIG. 3 is a process flow showing the manufacturing process of a conventional memory cell. 4 are diagrams showing a schematic configuration of an SRAM. In the figure, 1 is a voltage fi (Vcc), 2.3 is a high resistance element, 6.7 is a memory transistor, 9°10 is an access transistor, 11 is a word line, 12.13 is a bit line, 1718 is a capacitor, 20 is a silicon substrate, 21 is a field oxide film, 22 is a source/drain region, 23 is a gate oxide film, 24, 26, 28, 30 are P
off1y-3i film, 25, 27.29 is 5iCh#,
31 is a PSG film, and 32 is an AI2 film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) An insulating film that will become a capacitor and a conductive film that will become an electrode of the capacitor are formed on the upper layer of the gate electrode of a memory field effect transistor formed on a silicon substrate, and a conductive film that will become the electrode of the capacitor is formed. A memory cell characterized in that a part of a body membrane is formed so as to be electrically connected to ground.