JPH0482091A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate overwriting by comparing outside writing data with inside readout data and performing writing operation again to a selection memory transistor in which a comparison signal indicating the unmatch is detected when at least one comparison signal indicates unmatch. CONSTITUTION:Latches 24, corresponding to a normally written memory transistor 1 at the time of rewriting, are all reset. As the result, since the output of a boosting circuit 13 is turned to be L by outputting 1-bit latch data S24 to a boosting circuit 13, the rewriting is not performed to the normally written memory transistor 1, and the rewriting is performed only to the memory transistor 1 in which writing fault is detected. Therefore, the rewriting can be performed only to the memory transistor in which the faulty writing is detected when the writing of 0 can not be normally performed. Thus, the overwriting can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electrically writable nonvolatile semiconductor memory devices such as EPROM and EEPROM.

[Conventional technology]

FIG. 2 is a circuit diagram showing the basic configuration of a conventional EPROM. As shown in the figure, memory cells (memory transistors) 1 are arranged in a matrix (only 2 rows and 6 columns are shown in the figure). The memory transistor 1 has a floating gate and can perform nonvolatile storage. The drains of the memory transistors 1 are connected to a bit line 2 in common for each column, the control gates are connected to a word line 3 in common for values in a row, and the sources are connected to a word line 3 for a predetermined number of columns (3 in the figure).
(column) units are commonly connected to the source line 4.

Each bit line 2 is commonly connected to an I10 line 7 via a Y gate transistor 6 in units of a predetermined number of columns (three columns in the figure). The outputs of the column decoders 5 are applied to the gates of the Y-gate transistors 6, and the word lines 3 are connected to the row decoders 8. Column decoder 5 selectively sets its output to H level or high voltage VPP level based on the column address signal obtained from address buffer 9. On the other hand, the row decoder 8
The word line 3 is selectively set to the H level or the high voltage VPP level based on the row address signal obtained from the row address signal.

Each 110 line 7 is connected via a read transistor 10 to a sense amplifier 11 and via a write transistor 12 to a high voltage source VPP. A read signal R is applied to the gate of the read transistor 10, and a booster circuit 13 is applied to the gate of the write transistor 12.
The output of is given. The sense amplifier 11 outputs 1-bit output data S11, which will be described later, to the human output buffer]4,
The boost circuit 13 is supplied with a write signal W and 1-bit write data 514. This booster circuit] 3 becomes active when the write signal W is H, and outputs a high voltage VPP to the gate of the write transistor 12 when the 1-bit write data 514 is H, and when the 1-bit write data S14 is L , outputs L level to the gate of the write transistor 12. Note that the write signal W and the read signal R are output based on the control signal generation circuit 15 or an external control signal (not shown).

At the time of writing, the turnout buffer 14 simultaneously outputs L/H 1-bit write data S14 to each booster circuit 13 in 1-hyde (8-bit) units in response to external write data "1"/"0". , sense amplifier simultaneously in units of 1 Hyde at the time of reading] 1-bit output data Sll latched to 1 is taken in, and this 1-bit output data Sll is
Outputs an external readout flag of "0"/"1" corresponding to the H/L. Note that the sense amplifier 1.1 (boost circuit 13
) is generally 8 or more (8n pieces (n≧2)), and in order to capture the bit data stored in all the sense amplifiers 11 at the time of reading, it is necessary to output one bit for one hide. It is necessary to divide the data S11 into n times and sequentially import them into the crowd buffer 14.

A data write operation to the memory transistor of the EFROM having such a configuration will be explained.

Note that it is necessary to perform an erase operation in advance before performing a write operation.

The erasing operation is performed by irradiating ultraviolet light from above the EFROM chip. When irradiated with ultraviolet rays, the electrons accumulated in the floating gates of all memory transistors 1 are released, and the threshold voltage becomes as low as about 1V (
The threshold voltage at this time is Vthl). This state is “
]′ Corresponds to the memory state.

After performing the above erase operation, a write operation is performed. During a write operation, the read signal R is set, the write signal W is set to H, the sense up 11 and the I10 line 7 are electrically cut off, and the booster circuit 13 is activated. Then, by grounding the source line 4 and selectively raising the output of the column decoder 5 to high voltages V and P, the bit line 2 is selected, and the row decoder 8 selectively raises the word line 3 to a high voltage. Launch to VPP. With this setting, if the 1-bit write data S14 fetched from the human output buffer 14 is H, high voltage VPP is applied to the gate of the write transistor 12, and if it is L, L is applied to the gate of the write transistor 12. .

As a result, the selected memory transistor 1 at the intersection of the selected word line 3 and bit line 2
1-bit write data fetched from 4 514 or “0”
In the case of H, which instructs writing, a high voltage VPP is applied to the train and control gate, and hot electrons generated by avalanche collapse near the train are injected into the floating gate, so that the threshold voltage becomes as high as 6 to 8 V. Become. (The threshold voltage at this time is assumed to be Vth2 (>Vthl)). This state of the memory transistor 1- corresponds to the "0" storage state.

On the other hand, when the 1-bit write data S14 fetched from the human output buffer 14 instructs to write "1", the drain becomes floating, so no avalanche collapse occurs near the drain, and the threshold voltage maintains Vthl. ] “Maintain memory state. In this way, data is written to the memory transistor.

Next, the operation of reading out the memory contents written in the memory transistor will be explained.

During a read operation, the read signal R is set to H1, and the write signal W is set to L, the sense amplifier 11 and the I10 line 7 are electrically connected, and the booster circuit 13 is inactivated. and,
The bit line 2 is selected by grounding the source line 4 and selectively setting the output of the column decoder 5 to H, and the row decoder 8 selectively applies the read voltage VR (Vthl) of about 5V to the word line 3. <VR<Vth2)
give. With this setting, when "0" is stored in the selected memory transistor 1, a current flows from the I10 line 7 to the source line 4 via the bit line 2 because the selected memory transistor 1 maintains an off state. figure,
When “1” is stored in selected memory transistor 1, memory transistor 1 is turned on, so bit line 2
A current flows from the I10 line 7 to the source line 4 via the I10 line 7. The presence or absence of this current flow is sensed by the sense amplifier 11, and 1-bit output data Sll, which becomes H when current is detected and becomes H when no current is detected, is output to the human output buffer 14. Then, by outputting external read data from the turnout buffer 14 to the outside in 1-byte units, the memory contents of the selected memory transistor are read out.

By the way, the pulse width (high voltage V
There are variations in the writing characteristics, such as variations in the PP application time. Therefore, it is difficult to accurately write to all memory transistors in one write operation, and it is necessary to detect memory transistors that require rewriting. Therefore, after writing,
A verify operation is generally performed to confirm that writing (0'') has been executed normally.

Verify operation is performed every time a write operation is executed in 1-byte units while an EPROM write operation is being executed.
Read the data stored in the memory transistor to the outside,
This is an operation to check whether the data has been written normally by comparing it with the written data. Then, if a writing abnormality is detected through this verify operation, rewriting is performed. A write operation having such a verify function is performed by a dedicated external device called a FROM writer.

[Problem to be solved by the invention]

Conventional non-volatile semiconductor memory devices, such as EPROMs, which need to perform a write operation with a heli-fi function, are configured as described above, and the verify operation ensures that only one bit in one byte is insufficiently written. Even if there is a write operation, the rewrite operation is performed in 1-byte units just like the write operation, so even if the memory transistor has been written normally, the rewrite operation will be performed, which may lead to overwriting and unreliability. There was a problem that the quality decreased.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can perform writing with a veri-to-eye function without fear of overwriting.

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention includes a memory cell consisting of a memory transistor having a floating gate and performing nonvolatile storage, and in an active state, a plurality of memory cells selected in units of a predetermined number based on an external address signal are provided. write means for non-volatile writing in accordance with external write data to the selected memory transistor; read means for respectively outputting the memory contents of the selected memory transistor as internal read data when in an active state; data comparison means for comparing the external write data and the internal read data in each of the selected memory transistors and outputting a comparison signal indicating whether they match/mismatch, and activating the write means at the time of writing; After writing to the selected memory transistors, the reading means is activated to internally read out the stored contents of the plurality of selected memory transistors, and then the data comparing means is activated to write the data in each of the selected memory transistors. If a verify write operation is performed to compare external write data and the internal read data, and at least one of the comparison signals indicates a mismatch,
and write control means for performing the J-phi write operation again only on the selected memory transistor in which the comparison signal indicating a mismatch has been detected.

[Effect]

The write control means in this invention activates the write means to perform writing to a plurality of selected memory transistors, then activates a read means to internally read the stored contents of the plurality of selected memory transistors, and then compares the data. activating the means to execute a verify write operation for comparing external write data and internal read data in each of the selected memory transistors, and if at least one comparison signal indicates a mismatch, perform the verify write operation again; Since the rewriting is performed only on the selected memory transistor for which the comparison signal has been detected, rewriting is not performed for the selected memory transistor for which the comparison signal indicating a match has been detected.

〔Example〕

FIG. 1 is a circuit diagram showing the basic configuration of an EFROM which is an embodiment of the present invention. As shown in the figure, a write verify control circuit 21, a comparator 22, an OR gate 23, and a latch 24 are newly added. The write verify control circuit 21 receives the write signal W from the control signal generation circuit 15 and the output signal 523 of the OR gate 23, and outputs a write signal W2, a read signal R, and a verify signal C. Specifically, when a write signal W at H level is applied, it becomes active, and normally the write signal W2, which is at L level, the read signal R, and the verify signal C are sequentially raised to H level, and the write operation with verify function is performed. Take control.

Note that these signals W2. The H level output time of R and C is set to a predetermined time using an internal timer.

Further, the write verify control circuit 21 has an OR gate 2
3, and if it is determined based on this signal 523 that rewriting is necessary, a rewriting operation to be described later is executed.

The comparators 22 and latches 24 are provided corresponding to the sense amplifiers 11. In other words, the number of comparators 22 and latches 24 is the same as that of the sense amplifiers 11 (boosting circuits 13).
), generally 8n pieces (only two are shown in the figure) are provided. The comparator 22 receives the 1-bit latch data S24 from the verify signal C1 latch 24 and the 1-bit output data Sll from the sense amplifier 11, becomes active when the verify signal C is H, and locks the 1-bit output data 31.1 and the 1-bit latch. The data S24 are compared, and if they match, H1 and if they do not match, the comparison result S22 of L is output to each corresponding latch 24.

The latch 24 latches the 1-bit write data S14 of the human output buffer 714 as 1-bit latch data S24, and transfers this 1-bit latch data S24 to the boost circuit 13,
It is output to the input section of the comparator 22 and the OR gate 23. Further, upon receiving the comparison result S22 of the comparator 22, a reset is applied only when the comparison result S22 is H, and the 1-bit latch data S24 is fixed at L. Note that when the comparison result S22 is L, there is no change in the 1-bit latch data S24.

The OR gate 23 is 1 of 1 byte (only two are shown in the figure).
It takes in the bit latch data S24 and outputs the output signal S2B, which is the logical sum thereof, to the write verify control circuit 21. Note that the other configurations are the same as the conventional example shown in FIG. 2, so explanations will be omitted.

Data writing to the memory transistor of the EPROM having such a configuration is performed after an erase operation is performed. As in the conventional erasing operation, ultraviolet rays are irradiated from above the EFROM chip, and the threshold voltage of all memory transistors 1 is set to Vt.
This is done by setting it to hl (“1” storage state).

The write operation is started by applying an H write signal W from the control signal generation circuit 15 to the write verify control circuit 21 . Then, the write verify control circuit 21 becomes active and sets the write signal W2 to H.
and set the read signal R and verify signal C to L.
Then, the sense up circuit 11 and the I1010 line 7 are electrically cut off, and the booster circuit 13 is activated. The bit line 2 is selected by selectively raising the output of the column decoder 5 to the high voltage VPP, and the word line 3 is selectively raised to the high voltage VPP by the row decoder 8. Then, if the 1-bit write data S14 fetched from the human output buffer 14 is H, that is, the 1-bit latch data S2 latched in the latch 24
When 4 is H, high voltage VPP is applied to the gate of the write transistor 12, and when it is L, it is applied only to the gate of the write transistor 12.

As a result, the selected memory transistor 1 at the intersection of the selected word line 3 and bit line 2 is connected to the output buffer 1
1-bit write data S fetched from 4], when 4 is at H level to instruct "0" writing, high voltage VPP is applied to its drain and control gate,
Ho-node electrons generated by avalanche collapse near the drain are injected into the floating gate, and its threshold voltage becomes Vih2 (>Vthl). This state of memory transistor 1 corresponds to the "0" storage state.

On the other hand, when the 1-bit write data 514 is at the L level that instructs to write "1", the drain becomes floating, so no avalanche collapse occurs near the drain, and the threshold voltage maintains Vthl, resulting in a "1" storage state. keep it.

In this way, data is written to the selected memory transistor 1.

After that, the write signal W2 falls to L, and the read signal R rises to H. Then, the sense amplifier 11 and the I10 line 7 are electrically connected, and the booster circuit 13 becomes inactive. Then, by selectively setting the output of the column decoder 5 to H, the bit line 2 is selected, and the row decoder 8 selectively sets the output of the word line 3 to 5V.
Readout Lt pressure VR (Vthl < VR < Vth2
) is given. Then, if "0" is stored in the selected memory transistor 1, the selected memory transistor 1 maintains the off state, so the I1 is connected via the bit line 2.
If no current flows from the 0 line 7 to the source line 4 and "1" is stored in the selected memory transistor 1, the memory transistor 1 is turned on, so a current flows from the I10 line 7 to the source line 4 via the bit line 2. Current flows. The sense amplifier 11 senses the presence or absence of this current flow, and outputs 1-bit output data Sll, which becomes H when the L1 current is not detected, to the human output buffer 14 and to the comparator 22 at the time of current detection.

After that, the read signal R falls to L, and the verify signal C rises to H. When the verify signal C becomes H, the comparator 22 becomes active, and the 1-bit output data Sll of the sense amplifier 11 and the human output buffer 14 are
It compares the 1-bit write data S14 outputted from the 1-bit write data S14, and outputs a comparison result S22 of H when 5ll-S14 and L when Sll≠314. In other words, if the comparison result S22 is L, it means that writing to the selected memory transistor could not be performed normally. The latch 24 to which the comparison result S22 of H is applied is reset, and its 1-bit latch data S24 becomes L.

On the other hand, the 1-bit latch data S24 of the latch 24 to which the L comparison result S22 is applied does not change. The above steps are a write operation with a verify function that is executed in units of 1 byte.

1-bit latch data S taken into OR gate 23
If 24 is H at even one location, that is, the 1-bit write data 514 is at the H level that instructs writing of "O", but the 1-bit output data Sll is at the L level that instructs the "1' storage state." If there is even one memory transistor 1 read as
The output signal 523 of No. 3 becomes H. On the other hand, when all the 1-bit latch data S24 are L, the output signal S23 of the OR gate 23 becomes L. Write verify control circuit 2
1, when this output signal 523 is L, the write operation is completed, and when it is H, the write operation with verify function is executed again.

At the time of rewriting, all latches 24 corresponding to memory transistors 1 to which data has been written normally are reset. Therefore, by outputting the L 1-bit latch data S24 to the booster circuit 13, the output of the booster circuit 13 becomes L, so the memory transistor 1 that is always written to the IF is not rewritten, and a write failure is detected. Rewriting is performed only to memory transistor 1.

Therefore, if "0" cannot be written normally in at least one memory transistor during writing, rewriting can be performed only to the memory transistor in which defective writing has been detected. Therefore, when rewriting is performed, rewriting is not performed to memory transistors that have been normally written, and there is no risk of overwriting. As a result, even if there are variations in the write characteristics of memory transistors, FRO
EPROM without connecting to external devices such as M writer
By using only the internal components of the device, it is possible to write without compromising reliability. Note that the read operation is performed in the same manner as in the conventional case, so a description thereof will be omitted.

Note that in this example, E is used as a nonvolatile semiconductor memory device.
FROM is shown, but is not limited to FLASH EE.
It is applicable to all nonvolatile semiconductor memory devices that require a heli-fi operation after writing, such as FROM.

〔Effect of the invention〕

As explained above, according to the present invention, the write control means activates the write means to perform writing to the plurality of selected memory transistors, and then activates the read means to read the stored contents of the plurality of selected memory transistors. After performing an internal read, a verify write operation is performed in which the data comparison means is activated to compare the external write data and the internal read data in each selected memory transistor, and if at least one comparison signal indicates a mismatch, the data comparison means is activated again. The verify write operation is performed only on the selected memory transistor for which the comparison signal indicating a mismatch has been detected, and the selected memory transistor for which the comparison signal indicating a match has been detected, that is,
Since only rewriting is performed on memory transistors that have been written normally, writing with a verify function can be performed without fear of overwriting.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the basic configuration of an EPROM which is an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the basic configuration of a conventional EFROM. In the figure, 1 is a memory transistor, 11 is a sense amplifier, 21 is a write verify control circuit, 22 is a comparator, 23 is an OR gate, and 24 is a latch. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A nonvolatile semiconductor memory device including memory cells each having a floating gate and consisting of a memory transistor that performs nonvolatile storage, in which a plurality of memory cells selected in units of a predetermined number based on an external address signal in an active state are provided. a write means for performing non-volatile writing in the selected memory transistor according to external write data; a read means for outputting the stored contents of the plurality of selected memory transistors as internal read data when in an active state; data comparing means for comparing the external write data and the internal read data in each of the selected transistors and outputting a comparison signal indicating whether the data match/mismatch, respectively; After that, the reading means is activated to internally read out the storage contents of the plurality of selected memory transistors, and then the data comparing means is activated to compare the external write data and the internal read data in each of the selected memory transistors. If a verify write operation for comparison is executed and at least one of the comparison signals indicates a mismatch, the verify write operation is performed again only for the selected memory transistor in which the comparison signal indicating a mismatch has been detected. A nonvolatile semiconductor memory device comprising a control means.