JPH0480823A - Conversion system for machine language instruction train - Google Patents

Conversion system for machine language instruction train

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Publication number
JPH0480823A
JPH0480823A JP19446290A JP19446290A JPH0480823A JP H0480823 A JPH0480823 A JP H0480823A JP 19446290 A JP19446290 A JP 19446290A JP 19446290 A JP19446290 A JP 19446290A JP H0480823 A JPH0480823 A JP H0480823A
Authority
JP
Japan
Prior art keywords
instruction
machine language
program
language instruction
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19446290A
Other languages
Japanese (ja)
Inventor
Yuji Ogawa
雄司 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19446290A priority Critical patent/JPH0480823A/en
Publication of JPH0480823A publication Critical patent/JPH0480823A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To describe the machine language instructions as conventional regardless of the limitation of an RISC system by rearranging the instruction trains while maintaining a program function consisting of the instruction trains turned into the blocks. CONSTITUTION:A machine language instruction train block forming means 1 divides a described machine language instruction train 3 into the block instruction trains 4, 5 and 6 at the inlet and the outlet of the train 3 with no consciousness of an RISC system. Meanwhile a block instruction train rearrangement means 2 rearranges the trains 4 - 6 into the block instruction trains 7, 8 and 9 that comply with the limitation of the RISC system.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は縮小命令セット計算機(Reduced In
5truction Set Computer、以下
RISCという。)のように機械語原始プログラム中の
命令列の組み合わせにいくつかの制約を有する計算機シ
ステムにおける機械語命令列変換方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reduced instruction set computer (Reduced Instruction Set Computer).
5 truction set computer, hereinafter referred to as RISC. ) This paper relates to a method for converting machine language instruction strings in computer systems that have some restrictions on the combination of instruction strings in machine language source programs, such as the following.

〔従来の技術〕[Conventional technology]

近年、より高性能な計算機に対する需要からRISCシ
ステムが出現してきた。このようなシステムは今までの
計算機の中央処理装置(CentoraProcess
ing Unit 、以下CPUと称する。)の中で定
義されていた命令の種類を削減したり各機械語命令令列
の制御を取り除いたりして、CPUの処理負担を緩和す
ることによって高性能なシステムを実現している。この
ため、言語処理系等、RISCシステムを機械語レベル
で使用するためにはCPUから欠落したいくつかの機能
の肩代わりをしなくてはならない。
In recent years, RISC systems have emerged due to the demand for higher performance computers. Such a system is based on the central processing unit (CentoraProcess) of conventional computers.
ing Unit, hereinafter referred to as CPU. ), and by removing control over each machine language instruction sequence, a high-performance system is realized by easing the processing load on the CPU. Therefore, in order to use a RISC system at the machine language level, such as a language processing system, it is necessary to take over some of the functions missing from the CPU.

たとえは、ある命令の結果をそのすく次の命令て利用す
ることができない1分岐命令の次の命令はその分岐の正
否に関わらす実行されるといったことである。そのため
命令の同期をとるための無動作命令(No−0Pera
tion命令、以下NOP命令と称する。)を挿入した
り、別の命令をNOP命令の代わりに移動したりして使
用しなければらならい。
An example of this is that the instruction following a branch instruction is executed regardless of whether the branch is successful or not. Therefore, a no-operation instruction (No-0Pera) is used to synchronize instructions.
tion instruction, hereinafter referred to as a NOP instruction. ) or move another instruction in place of the NOP instruction.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したようにRISCシステムはCPUの単純化によ
り、機械語を利用するためには従来の計算機システムと
同様に処理の流れを設計どおりに逐次的に記述すること
ができず、命令を移動したりNOP命令を挿入したりし
なくてはならない。
As mentioned above, due to the simplification of the CPU in the RISC system, in order to use machine language, it is not possible to describe the processing flow sequentially as designed, as in conventional computer systems, and it is difficult to move instructions or It is necessary to insert a NOP instruction.

したかって、言語処理系等のように機械語命令を生成す
るシステムにとって大きな負担となっていた。
This has therefore placed a heavy burden on systems that generate machine language instructions, such as language processing systems.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の機械語命令列変換方式は、機械語原始プログラ
ムの命令列をそれぞれ制御の入口と出口かたた一つとな
るようにフロック分割する機械語命令列ブロック化手段
と、ブロック化された命令列が構成しているプロクラム
機能を維持したまま前記命令列を並び換えるブロック命
令列並び換え手段とを有する。
The machine language instruction string conversion method of the present invention includes a machine language instruction string blocking means that divides the instruction string of a machine language source program into flocks so that there is only one control entry and one exit, and a machine language instruction string blocking means. and block instruction sequence rearranging means for rearranging the instruction sequence while maintaining the program functions that the sequence constitutes.

また、本発明の機械語命令列変換方式は、RISCを意
識せずに記述した原始プログラムをRISCに適応する
プログラムに変換するとき、前記原始プログラムの機械
語命令列を制御の入口および出口がそれぞれ一つとなる
ようにブロック分割し、ブロック化された前記機械語命
令列が構成しているプログラム機能を維持したまま前記
機械語命令列を並び換えてRISCに適応させるように
して構成させる。
Further, in the machine language instruction string conversion method of the present invention, when converting a source program written without being aware of RISC into a program that is compatible with RISC, the machine language instruction string of the source program is converted into a control entry and an exit, respectively. The block is divided into one block, and the machine language instruction sequence is rearranged while maintaining the program function constituted by the machine language instruction sequence so as to be adapted to RISC.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す説明図である。同図に
おいて機械語命令列ブロック化手段1はRISCシステ
ムを意識せずに記述された機械語命令列3を命令列の入
口および出口で区切ってブロック命令列4,5.6とに
分割する。また、ブロック命令列並び換え手段2はブロ
ック命令列4,5.6をRISCシステムの制約を満た
した命令ブロック7.8.9に並び換えを行つ。
FIG. 1 is an explanatory diagram showing one embodiment of the present invention. In the figure, a machine language instruction string blocking means 1 divides a machine language instruction string 3, which has been written without being aware of the RISC system, into block instruction strings 4, 5, and 6 by dividing the instruction string at the entrance and exit of the instruction string. Further, the block instruction sequence rearranging means 2 rearranges the block instruction sequences 4, 5.6 into an instruction block 7.8.9 that satisfies the constraints of the RISC system.

今、次のような命令セットを仮定する。LD命令は2つ
のオペランドをとり、第二オペランドに指定されたレジ
スタに格納されたアドレスから1語を読み、第一オペラ
ンドのレジスタに格納する。ただし、LD命令とその結
果を参照する命令の間には最低1つの命令がなくてはな
らす、LD命令のすぐ次の命令でその結果を参照した場
合の遅れは不定である。このように命令の結果に1命令
の遅れを生しることを「1命令の遅延がある」という。
Now, assume the following instruction set. The LD instruction takes two operands, reads one word from the address stored in the register specified by the second operand, and stores it in the register of the first operand. However, there must be at least one instruction between the LD instruction and the instruction that refers to its result, and the delay when the result is referenced by the instruction immediately following the LD instruction is indefinite. When a one-instruction delay occurs in the result of an instruction in this way, it is said that there is a "one-instruction delay."

ADD命令は3つのオペランドをとり、第二オペランド
のレジスタの内容と第三オペランドのレジスタの内容も
しくは即値との和を第一オペランドのレジスタに格納す
る。
The ADD instruction takes three operands and stores the sum of the contents of the register of the second operand and the contents or immediate value of the register of the third operand in the register of the first operand.

SUB命令は3つのオペランドをとり、第二オペランド
のレジスタの内容と第三オペランドのレジスタの内容も
しくは即値の差を第一オペランドのレジスタに格納する
The SUB instruction takes three operands and stores the difference between the contents of the register of the second operand and the contents or immediate value of the register of the third operand in the register of the first operand.

BEQ命令は第一、第二オペランドのレジスタの内容が
等しい場合に第三オペランドが示すラベルへ分岐する。
The BEQ instruction branches to the label indicated by the third operand when the contents of the registers of the first and second operands are equal.

B命令は第一オペランドで示されるラベルへ分岐する。The B instruction branches to the label indicated by the first operand.

BEQ命令およびB命令には1命令の遅延があり、制御
が転移する前にすぐ次の命令を実行する。NOP命令は
特にそれ自身は何の働きもしないが遅延命令の同期をと
るために使用される。
The BEQ and B instructions have a one instruction delay and execute the next instruction immediately before control is transferred. The NOP instruction does nothing in particular by itself, but is used to synchronize delayed instructions.

レジスタは4つあり、それぞれ$0.$1゜$2.$3
と記述する。特に$0の内容は0で、それを変更するこ
とはできない。また、ラベルはラベル名の後に、“:゛
を付与する。
There are four registers, each with $0. $1゜$2. $3
It is described as follows. In particular, the content of $0 is 0 and cannot be changed. Also, for labels, add ":" after the label name.

以上のような命令セットで第2図の命令列を考える。こ
れは0から記憶領域のある値に1を加えた値までの整数
の総和を求めるプログラムで、特にRISCシステムを
意識せずに記述したプログラム例である。当然、このま
ま実行したら誤動作を起こすため命令列の変換を行う。
Consider the instruction string shown in FIG. 2 with the instruction set described above. This is a program that calculates the sum of integers from 0 to a value in the storage area plus 1, and is an example of a program written without being particularly aware of the RISC system. Naturally, if executed as is, a malfunction will occur, so the instruction sequence must be converted.

まず、2つのラベルLABELI : (201)およ
びLABEL2: (205)が゛それぞれ制御の入口
を示しBEQ命令(207)およびB命令(209>が
それぞれ制御の出口を示している。
First, two labels LABELI: (201) and LABEL2: (205) each indicate a control entry, and a BEQ instruction (207) and a B instruction (209>) each indicate a control exit.

そこでこの命令列は第3図に示すように3つのブロック
命令列に分けられる。ブロック化されたそれぞれの命令
列は、入口と出口がそれぞれ1つしかないため、入口時
点での資源の状態と出口時点での資源の状態さえ満足し
ていれば途中の状態がどうであろうとプログラム全体に
対して何の影響も与えない。このことを利用して次に各
ブロック命令列の並び換えを考える。
Therefore, this instruction string is divided into three block instruction strings as shown in FIG. Each blocked instruction sequence has only one entrance and one exit, so as long as the state of the resources at the time of entry and the state of the resources at the time of exit are satisfied, it does not matter what the state is in the middle. It has no effect on the overall program. Taking advantage of this fact, we next consider rearranging each block instruction sequence.

第3図(a)のブロック命令列を見るとLD命令の次の
ADD命令でLD命令の結果を参照しているため、この
間にNOP命令が必要となる。
Looking at the block instruction sequence in FIG. 3(a), since the ADD instruction following the LD instruction refers to the result of the LD instruction, a NOP instruction is required during this period.

しかし3番目のSUB命令はこれら2命令と何の依存関
係も持たないため、NOP命令を挿入する代わりにSU
B命令を移動する。
However, the third SUB instruction has no dependency on these two instructions, so instead of inserting a NOP instruction,
Move the B command.

第3図(b)では、BEQ命令の分岐か成立した場合て
もすぐ次の命令を実行してしまうので、差し障りのない
NOP命令を挿入することが考えられるが、ADD命令
はBEQ命令の後で実行しても問題ないので、この2命
令を入れ換える。
In Figure 3(b), even if the branch of the BEQ instruction is taken, the next instruction will be executed immediately, so it is possible to insert a NOP instruction that does not cause any problem, but the ADD instruction is inserted after the BEQ instruction. There is no problem if you execute it with , so swap these two instructions.

第3図(C)のブロック命令列についても同様である。The same applies to the block instruction sequence shown in FIG. 3(C).

結果として第4図の命令列か求められるが、この命令列
は保守する立場から考えた場合非常に理解しにくいプロ
グラムである。
As a result, the instruction sequence shown in FIG. 4 is obtained, but this instruction sequence is a program that is very difficult to understand from a maintenance standpoint.

上記のようにしてプログラム作成者は従来どおりの命令
列を記述するだけでRISCシステムでも正しく動作し
、かつその性能を十分発揮てきる命令列に変換すること
ができる。すなわち、プログラム作成者はRISCシス
テムの制約を意識することなく常に従来どおりのプログ
ラム記述を行えばよい。
As described above, the program creator can simply write a conventional instruction sequence and convert it into an instruction sequence that operates correctly even on a RISC system and fully exhibits its performance. In other words, the program creator can always write the program in the conventional manner without being aware of the limitations of the RISC system.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の機械語命令列変換方式はR
ISCシステムの制約にとられれず従来どおりの機械語
命令記述を可能にするとともに、RISCシステムの性
能を十分発揮することが可能になるという効果がある。
As explained above, the machine language instruction string conversion method of the present invention is R
This has the effect that it is possible to write machine language instructions as before without being bound by the limitations of the ISC system, and it is also possible to fully utilize the performance of the RISC system.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す説明図、第2図は機械
語命令列の例を示す説明図、第3図は命令列ブロック化
の結果を示す説明図、第4図は命令列並べ換えの結果を
示す説明図である。 1・・・機械語命令列ブロック化手段、2・・・ブロッ
ク命令列並べ換え手段、3・・・機械語命令列、4〜9
・・・ブロック命令列。
FIG. 1 is an explanatory diagram showing one embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a machine language instruction sequence, FIG. 3 is an explanatory diagram showing the result of instruction sequence blocking, and FIG. It is an explanatory diagram showing the result of column rearrangement. 1... Machine language instruction string blocking means, 2... Block instruction string rearranging means, 3... Machine language instruction string, 4 to 9
...Block instruction sequence.

Claims (1)

【特許請求の範囲】 1、機械語原始プログラムの命令列をそれぞれ制御の入
口と出口がただ一つとなるようにブロック分割する機械
語命令列ブロック化手段と、ブロック化された命令列が
構成しているプログラム機能を維持したまま前記命令列
を並び換えるブロック命令列並び換え手段とを有するこ
とを特徴とする機械語命令列変換方式。 2、RISCを意識せずに記述した原始プログラムをR
ISCに適応するプログラムに変換するとき、前記原始
プログラムの機械語命令列を制御の入口および出口がそ
れぞれ一つとなるようにブロック分割し、ブロック化さ
れた前記機械語命令列が構成しているプログラム機能を
維持したまま前記機械語命令令列を並び換えてRISC
に適応させることを特徴とする請求項1記載の機械語命
令列変換方式。
[Scope of Claims] 1. Machine language instruction string blocking means for dividing the instruction string of a machine language source program into blocks so that each control has only one entry and exit; and the blocked instruction string. 1. A machine language instruction sequence conversion method, comprising block instruction sequence rearranging means for rearranging the instruction sequence while maintaining program functions. 2. Convert the original program written without being aware of RISC to R
When converting into a program that is compatible with ISC, the machine language instruction sequence of the source program is divided into blocks such that there is one control entry and one control exit, and the program is constituted by the machine language instruction sequence that has been divided into blocks. RISC by rearranging the machine language instruction sequence while maintaining functionality.
2. The machine language instruction string conversion method according to claim 1, wherein the method is adapted to the following.
JP19446290A 1990-07-23 1990-07-23 Conversion system for machine language instruction train Pending JPH0480823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19446290A JPH0480823A (en) 1990-07-23 1990-07-23 Conversion system for machine language instruction train

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19446290A JPH0480823A (en) 1990-07-23 1990-07-23 Conversion system for machine language instruction train

Publications (1)

Publication Number Publication Date
JPH0480823A true JPH0480823A (en) 1992-03-13

Family

ID=16324964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19446290A Pending JPH0480823A (en) 1990-07-23 1990-07-23 Conversion system for machine language instruction train

Country Status (1)

Country Link
JP (1) JPH0480823A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100371927B1 (en) * 1992-03-31 2003-02-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100371927B1 (en) * 1992-03-31 2003-02-12

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