JPH0479366A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0479366A JPH0479366A JP2195310A JP19531090A JPH0479366A JP H0479366 A JPH0479366 A JP H0479366A JP 2195310 A JP2195310 A JP 2195310A JP 19531090 A JP19531090 A JP 19531090A JP H0479366 A JPH0479366 A JP H0479366A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- electrode
- insulating film
- forming
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000003860 storage Methods 0.000 abstract description 20
- 238000005452 bending Methods 0.000 abstract description 8
- 230000001154 acute effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- XUIMIQQOPSSXEZ-IGMARMGPSA-N silicon-28 atom Chemical compound [28Si] XUIMIQQOPSSXEZ-IGMARMGPSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体基板上に設けた多結晶シリコンを記憶
素子の電極として使用する半導体装置およびその製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device using polycrystalline silicon provided on a semiconductor substrate as an electrode of a memory element, and a method for manufacturing the same.
従来の技術
近年、半導体装置の微細化、集積化が進む中で、半導体
記憶素子１個当りの面積は小さ（なり、記憶素子容量を
確保するために、従来の半導体基板上に形成したブレー
ナ型記憶素子に代わって半導体基板上の大きな段差を利
用して、多結晶シリコンを電極とし、この電極上に容量
絶縁膜を形成する積層型記憶素子が採用されている。Background of the Invention In recent years, as semiconductor devices have become smaller and more integrated, the area per semiconductor memory element has become smaller. Instead of a memory element, a stacked memory element is used that uses a large step on a semiconductor substrate, uses polycrystalline silicon as an electrode, and forms a capacitive insulating film on the electrode.
以下に、従来の積層型記憶素子とその製造方法について
説明する。A conventional stacked memory element and its manufacturing method will be described below.
第３図は、従来の製造方法により形成した積層型記憶素
子の概略断面図であり、第４図は、従来の積層型記憶素
子の製造方法を示した工程順断面図である。第３図、第
４図を通じて、１が半導体基板、２がＬＯＧＯ３酸化膜
、３がゲート酸化膜、４がゲート電極、５がサイドウオ
ール、６がｎ十拡散層、７が酸化珪素膜、８がストレー
ジノード電極、９が容量絶縁膜、１０が上部多結晶シリ
コン電極、１１が多結晶シリコン膜である。以下に、工
程順に説明する。FIG. 3 is a schematic cross-sectional view of a stacked memory element formed by a conventional manufacturing method, and FIG. 4 is a step-by-step cross-sectional view showing a conventional method for manufacturing a stacked memory element. 3 and 4, 1 is a semiconductor substrate, 2 is a LOGO3 oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is a side wall, 6 is an n+ diffusion layer, 7 is a silicon oxide film, 8 is a storage node electrode, 9 is a capacitor insulating film, 10 is an upper polycrystalline silicon electrode, and 11 is a polycrystalline silicon film. The steps will be explained below in order.
半導体基板１上に周知の方法によりＬＯＧＯ３酸化膜２
．ゲート酸化膜３．ゲート電極４．サイドウオール５．
ｎ＋拡散層（ソース、ドレイン拡散層）６を形成した後
、化学的気相成長（以下、ＣＶＤと略す）により酸化珪
素膜７を堆積する（第４図（ａ））。続いて、ホトレジ
ストをマスクにして酸化珪素膜７をエツチングし、半導
体基板１表面のｎ＋拡散層６上にコンタクトホールを形
成する（第４図（ｂ））。次に、ＣＶ Ｄ法により多結
晶シリコン膜１１を堆積する（第４図（Ｃ））。この後
、多結晶シリコン膜１１に不純物拡散し導電性を高めた
後、ホトレジストをマスクにして多結晶シリコン膜１１
をエツチングしストレージノード電極８を形成する。そ
のストージノード電極８上に窒化珪素膜と酸化珪素膜か
ら成る容量絶縁膜９を形成し、ＣＶＤ法により容量絶縁
膜９上に多結晶シリコン膜を堆積し、リンの不純物拡散
により導電性を高め、ホトレジストをマスクとしてエツ
チングし上部多結晶シリコン電極１０を形成する（第４
図（ｄ）〉。以上のようにして、従来の積層型記憶素子
が形成される。A LOGO3 oxide film 2 is formed on a semiconductor substrate 1 by a well-known method.
．． Gate oxide film 3. Gate electrode 4. Side wall 5.
After forming the n+ diffusion layer (source, drain diffusion layer) 6, a silicon oxide film 7 is deposited by chemical vapor deposition (hereinafter abbreviated as CVD) (FIG. 4(a)). Subsequently, the silicon oxide film 7 is etched using a photoresist as a mask to form a contact hole on the n+ diffusion layer 6 on the surface of the semiconductor substrate 1 (FIG. 4(b)). Next, a polycrystalline silicon film 11 is deposited by the CVD method (FIG. 4(C)). After that, impurities are diffused into the polycrystalline silicon film 11 to increase its conductivity, and then the polycrystalline silicon film 11 is
is etched to form a storage node electrode 8. A capacitive insulating film 9 made of a silicon nitride film and a silicon oxide film is formed on the storage node electrode 8, a polycrystalline silicon film is deposited on the capacitive insulating film 9 by the CVD method, and conductivity is increased by diffusion of phosphorous impurities. The upper polycrystalline silicon electrode 10 is formed by etching using the photoresist as a mask (the fourth
Figure (d)〉. In the manner described above, a conventional stacked memory element is formed.
発明が解決しようとする課題
しかしながら、上記従来の製造方法では、第３図もしく
は第４図（ｄ）に示すように、半導体基板に対し平行な
ストレージノード電極面と側面部の角度は９０”以下で
あり、かつ断面形状において電極表面に屈曲点が存在す
る。また、素子の微細化が進むと電極面積に対する屈曲
点部分の占める割合が無視できないものとなる。従って
、このような屈曲点の存在する電極表面上に容量絶縁膜
を形成すると、容量絶縁膜に応力が加わりウィークスポ
ット等の原因となり容量絶縁膜の信頼性を確保する上で
問題を有していた。Problems to be Solved by the Invention However, in the conventional manufacturing method described above, as shown in FIG. 3 or 4(d), the angle between the storage node electrode surface parallel to the semiconductor substrate and the side surface is 90" or less. , and there is a bending point on the electrode surface in the cross-sectional shape.Also, as elements become smaller, the ratio of the bending point to the electrode area cannot be ignored.Therefore, the existence of such a bending point When a capacitive insulating film is formed on the surface of an electrode, stress is applied to the capacitive insulating film, causing weak spots and the like, which poses a problem in ensuring the reliability of the capacitive insulating film.
本発明は、上記従来の課題を解決するもので、電極表面
は連続点で構成され、かつ、電極側面の断面形状が円弧
状であるストレージノード電極を形成し、電極上に形成
される容量絶縁膜の信頼性を向上させることのできる優
れた半導体装置およびその製造方法を提供するものであ
る。The present invention solves the above-mentioned conventional problems by forming a storage node electrode whose electrode surface is composed of continuous points and whose side surface has an arcuate cross-section, and by forming a capacitive insulator formed on the electrode. An object of the present invention is to provide an excellent semiconductor device that can improve film reliability and a method for manufacturing the same.
課題を解決するための手段
この目的を達成するために、本発明の半導体装置は、ス
トレージノード電極に多結晶シリコンサイドウオールを
形成し、電極表面に屈曲点をなくし側面部を球面状にし
た構成を有している。Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention has a structure in which a polycrystalline silicon sidewall is formed on the storage node electrode, and the electrode surface has no bending point and the side surface is spherical. have.
作用
本発明によれば、ストレージノード電極表面は屈曲点の
ない面で構成され、かつ、側面部は球面状であるため、
電極上に形成する容量絶縁膜に応力が加わることなく、
信頼性の高い記憶素子を形成することができる。According to the present invention, the storage node electrode surface is composed of a surface without bending points, and the side surface portion is spherical.
without applying stress to the capacitive insulating film formed on the electrode.
A highly reliable memory element can be formed.
実施例
以下に、本発明の一実施例半導体について、図面を参照
しながら説明する。第１図は、本発明による半導体装置
の概略断面図である。２１が半導体基板、２２がＬＯＧ
Ｏ８酸化膜、２３がゲート酸化膜、２４がゲート電極、
２５がサイドウオール、２６がｎ十拡散層、２７が酸化
珪素膜、２８が多結晶シリコン、２９が多結晶シリコン
サイドウオール、３０が容量絶縁膜、３１が上部多結晶
シリコン電極である。EXAMPLE A semiconductor according to an example of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention. 21 is a semiconductor substrate, 22 is LOG
O8 oxide film, 23 is a gate oxide film, 24 is a gate electrode,
25 is a sidewall, 26 is an n+ diffusion layer, 27 is a silicon oxide film, 28 is polycrystalline silicon, 29 is a polycrystalline silicon sidewall, 30 is a capacitor insulating film, and 31 is an upper polycrystalline silicon electrode.
半導体基板２１上に形成されたストレージノード電極は
、多結晶シリコン２８と多結晶シリコンサイドウオール
２９で形成されているため、ストレージノード電極表面
は屈曲点のない面で構成され、かつ、電極側面部は球形
状となる。従って、ストレージノード電極上に形成され
た容量絶縁膜に対し応力が加わることによるウィークス
ポット等の発生がないため、信頼性の高い記憶素子を形
成することが可能となる。さらに、ストレージノード電
極に鋭角部分がないため、形成された記憶素子の上部多
結晶シリコン電極表面は平滑な面となり、素子の微細化
が進む上で問題になる平坦化にも寄与することになる。Since the storage node electrode formed on the semiconductor substrate 21 is formed of polycrystalline silicon 28 and polycrystalline silicon sidewalls 29, the storage node electrode surface has no bending points, and the side surface of the electrode has a spherical shape. Therefore, weak spots and the like due to stress applied to the capacitive insulating film formed on the storage node electrode do not occur, making it possible to form a highly reliable storage element. Furthermore, since there are no sharp edges in the storage node electrode, the surface of the upper polycrystalline silicon electrode of the formed memory element will be a smooth surface, contributing to flattening, which becomes a problem as elements become smaller. .
これにより、配線歩留も向上させることができる。Thereby, wiring yield can also be improved.
次に、本発明の半導体装置の製造方法の一実施例につい
て、図面を参照しながら詳しく説明する。Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings.
第２図は、本発明の半導体装置の製造方法を示す工程順
の概略断面図である。簡略化するためにあえて記憶素子
形成工程のみ示す。２１が半導体基板、２２がＬＯＧＯ
３酸化膜、２３がゲート酸化膜、２４がゲート電極、２
５がサイドウオール２６がｎ十拡散層、２７が酸化珪化
素膜、２８が多結晶シリコン、２９が多結晶シリコンサ
イドウオール、３０が容量絶縁膜、３１が上部多結晶シ
リコン電極である。FIG. 2 is a schematic cross-sectional view showing the process order of the method for manufacturing a semiconductor device of the present invention. For the sake of simplicity, only the memory element forming process is shown. 21 is the semiconductor substrate, 22 is LOGO
3 oxide film, 23 gate oxide film, 24 gate electrode, 2
Reference numeral 5 indicates a sidewall 26 which is an n+ diffusion layer, 27 a silicon oxide film, 28 a polycrystalline silicon sidewall, 29 a polycrystalline silicon sidewall, 30 a capacitive insulating film, and 31 an upper polycrystalline silicon electrode.
まず、半導体基板２１上に周知の方法によりＬＯＧＯ３
酸化膜２２、ゲート酸化膜２３、ゲート電極２４、サイ
ドウ万一ル２５、ｎ＋拡散層（ソース、ドレイン拡散層
）２６を形成した後、ＣＶＤ法により酸化珪素膜２７を
堆積する（第２図（ａ））。続いて、ホトレジストをマ
スクにして酸化珪素膜７をエツチングし、半導体基板２
１の表面のｎ＋拡散層６上にコンタクトホールを形成す
る（第２図（ｂ））。次にＣＶＤ法により多結晶シリコ
ン膜を堆積し、ホトレジストをマスクにして多結晶シリ
コン膜をエツチングし多結晶シリコン電極を形成する（
第２図（Ｃ））。次に、多結晶シリコン膜をＣＶＤ法に
より堆積した後、多結晶シリコンの異方性エツチングを
表面全体に施し、多結晶シリコンサイドウオール２９を
形成した後、リンを不純物拡散し導電性を高めてストレ
ージノード電極を形成する（第２図（ｄ））。そのスト
レージノード電極上に例えば窒化珪素膜と酸化珪素膜か
らなる容量絶縁膜３０を形成し、ＣＶＤ法により容量絶
縁膜上に多結晶シリコン膜を堆積し、リンの不純物拡散
により導電性を高め、ホトレジストをマスクにエツチン
グし上部多結晶シリコン電極３１を形成する（第２図（
ｆ））。以上のようにして、本発明の製造方法により、
容量素子が形成される。本発明の製造方法によれば、多
結晶シリコン膜を全面に堆積した後、全面に多結晶シリ
コンの異方性エツチングをし多結晶シリコンサイドウオ
ールを形成するため、ストレージノード電極表面の端面
において、端部での接線とストレージノード電極側面の
なす角度は９０°以上となり、かつ側面部は球面状とな
る。従って、この方法は、その上に形成する容量絶縁膜
に対し応力を加えることがなく、容量絶縁膜の信頼性を
高めることのできる優れた半導体装置の製造方法である
。First, LOGO3 is placed on the semiconductor substrate 21 by a well-known method.
After forming the oxide film 22, gate oxide film 23, gate electrode 24, sidewall 25, and n+ diffusion layer (source and drain diffusion layer) 26, a silicon oxide film 27 is deposited by the CVD method (see FIG. 2). a)). Next, the silicon oxide film 7 is etched using the photoresist as a mask, and the semiconductor substrate 2 is etched.
A contact hole is formed on the n+ diffusion layer 6 on the surface of the substrate 1 (FIG. 2(b)). Next, a polycrystalline silicon film is deposited by the CVD method, and the polycrystalline silicon film is etched using a photoresist as a mask to form a polycrystalline silicon electrode (
Figure 2 (C)). Next, after depositing a polycrystalline silicon film by the CVD method, anisotropic etching of the polycrystalline silicon is performed on the entire surface to form a polycrystalline silicon sidewall 29, and then phosphorus is diffused as an impurity to increase conductivity. A storage node electrode is formed (FIG. 2(d)). A capacitive insulating film 30 made of, for example, a silicon nitride film and a silicon oxide film is formed on the storage node electrode, a polycrystalline silicon film is deposited on the capacitive insulating film by the CVD method, and conductivity is increased by diffusion of phosphorous impurities. Using a photoresist as a mask, etching is performed to form an upper polycrystalline silicon electrode 31 (see FIG. 2).
f)). As described above, by the manufacturing method of the present invention,
A capacitive element is formed. According to the manufacturing method of the present invention, after a polycrystalline silicon film is deposited on the entire surface, polycrystalline silicon is anisotropically etched on the entire surface to form a polycrystalline silicon sidewall. The angle between the tangent at the end and the side surface of the storage node electrode is 90° or more, and the side surface has a spherical shape. Therefore, this method is an excellent method for manufacturing a semiconductor device that does not apply stress to the capacitive insulating film formed thereon and can improve the reliability of the capacitive insulating film.
発明の効果
以上のように、本発明によれば、多結晶シリコンと多結
晶シリコンサイドウオールを使用し、ストレージノード
電極表面の端面における端部での接線とストレージノー
ド電極の側面とのなす角度が９０°以上で、かつ側面部
を球面状にすることで、電極上に形成する容量絶縁膜の
信頼性を向上させ、さらに、平坦化にも寄与することか
ら後工程での配線保留を向上させることのできる優れた
半導体装置およびその製造方法である。Effects of the Invention As described above, according to the present invention, polycrystalline silicon and polycrystalline silicon sidewalls are used, and the angle between the tangent at the end of the end face of the storage node electrode surface and the side surface of the storage node electrode is By making the side surface spherical at an angle of 90 degrees or more, the reliability of the capacitive insulating film formed on the electrode is improved, and it also contributes to planarization, which improves wiring retention in subsequent processes. The present invention provides an excellent semiconductor device and a method for manufacturing the same.
第１図は本発明における半導体装置の断面図、第２図は
本発明における半導体装置の製造方法の工程順断面図、
第３図は従来の半導体装置の断面図、第４図は従来の半
導体装置の製造方法の工程順断面図である。
１・・・・・・半導体基板、２・・・・・・ＬＯＣＯ３
酸化膜、３・・・・・・ゲート酸化膜、４・・・・・・
ゲート電極、５・・・・・サイドウオール、６・・・・
・・ｎ十拡散層、７・・・・・・酸化珪素膜、８・・・
・・・多結晶シリコン、９・・・・・・多結晶シリコン
サイドウオール、１０，１３・・・・・・容量絶縁膜、
１１．１４・・・・・・上部多結晶シリコン電極、１２
・・・・・・ストレージノード電極、１５・・・・・・
多結晶シリコン膜。
代理人の氏名 弁理士 粟野重孝 はか１名塚FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of a method for manufacturing a semiconductor device according to the present invention,
FIG. 3 is a sectional view of a conventional semiconductor device, and FIG. 4 is a sectional view of a conventional semiconductor device manufacturing method in the order of steps. 1...Semiconductor substrate, 2...LOCO3
Oxide film, 3...Gate oxide film, 4...
Gate electrode, 5...Side wall, 6...
...n10 diffusion layer, 7... silicon oxide film, 8...
... Polycrystalline silicon, 9... Polycrystalline silicon side wall, 10, 13... Capacitive insulating film,
11.14... Upper polycrystalline silicon electrode, 12
...Storage node electrode, 15...
Polycrystalline silicon film. Name of agent: Patent attorney Shigetaka Awano Hakaichi Natsuka
Claims (2)
層と、前記半導体基板上に形成された絶縁膜と、前記拡
散層と接続するように前記絶縁膜に形成されたコンタク
トと、前記絶縁膜表面および前記コンタクト底面に形成
された第１の多結晶シリコンと、前記第１の多結晶シリ
コンの露出した表面に形成された容量絶縁膜と、前記容
量絶縁膜の側壁に形成された表面が円弧上の第２の多結
晶シリコンのサイドウォールと、前記容量絶縁膜と前記
サイドウォール表面に形成された第３の多結晶シリコン
を備えたことを特徴とする半導体装置。(1) A semiconductor substrate, a diffusion layer formed on the semiconductor substrate, an insulating film formed on the semiconductor substrate, a contact formed on the insulating film to be connected to the diffusion layer, and the insulating layer. a first polycrystalline silicon formed on the film surface and the bottom surface of the contact, a capacitive insulating film formed on the exposed surface of the first polycrystalline silicon, and a surface formed on the sidewall of the capacitive insulating film. A semiconductor device comprising: a second polycrystalline silicon sidewall on an arc; and a third polycrystalline silicon formed on the capacitor insulating film and the sidewall surface.
導体基板上に絶縁膜を形成する工程と、前記拡散層とコ
ンタクトする領域上の前記絶縁膜を除去する工程と、前
記絶縁膜表面および前記コンタクト底面に第１の多結晶
シリコンを形成する工程と、前記第１の多結晶シリコン
の露出した表面に容量絶縁膜を形成する工程と、前記半
導体基板の全面に第２の多結晶シリコンを形成する工程
と、前記第２の多結晶シリコンをドライエッチングして
、第２の多結晶シリコンからなるサイドウォールを形成
する工程と、少なくとも前記容量絶縁膜と前記サイドウ
ォール表面に第３の多結晶シリコンを形成する工程を備
えたことを特徴とする半導体装置の製造方法。(2) forming a diffusion layer in a semiconductor substrate; forming an insulating film on the semiconductor substrate; removing the insulating film on a region in contact with the diffusion layer; and a surface of the insulating film. and a step of forming a first polycrystalline silicon on the bottom surface of the contact, a step of forming a capacitive insulating film on the exposed surface of the first polycrystalline silicon, and a step of forming a second polycrystalline silicon on the entire surface of the semiconductor substrate. forming a sidewall made of second polycrystalline silicon by dry etching the second polycrystalline silicon; and forming a third polycrystalline silicon on at least the surface of the capacitive insulating film and the sidewall. A method for manufacturing a semiconductor device, comprising a step of forming crystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2195310A JPH0479366A (en) | 1990-07-23 | 1990-07-23 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2195310A JPH0479366A (en) | 1990-07-23 | 1990-07-23 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0479366A true JPH0479366A (en) | 1992-03-12 |
Family
ID=16339031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2195310A Pending JPH0479366A (en) | 1990-07-23 | 1990-07-23 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0479366A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483140B1 (en) * | 1999-07-26 | 2002-11-19 | Mitsubishi Denki Kabushiki Kaisha | DRAM storage node with insulating sidewalls |
-
1990
- 1990-07-23 JP JP2195310A patent/JPH0479366A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483140B1 (en) * | 1999-07-26 | 2002-11-19 | Mitsubishi Denki Kabushiki Kaisha | DRAM storage node with insulating sidewalls |
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