JPH0479137B2 - - Google Patents
Info
- Publication number
- JPH0479137B2 JPH0479137B2 JP17885882A JP17885882A JPH0479137B2 JP H0479137 B2 JPH0479137 B2 JP H0479137B2 JP 17885882 A JP17885882 A JP 17885882A JP 17885882 A JP17885882 A JP 17885882A JP H0479137 B2 JPH0479137 B2 JP H0479137B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- fuse
- region
- wiring
- fuse wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical group C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 2
- 239000010408 film Substances 0.000 description 23
- 238000000034 method Methods 0.000 description 10
- 239000005360 phosphosilicate glass Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置に係り、特に冗長回路を有
する半導体装置に於ける通電溶断型フユーズ配線
の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of an electrically blown fuse wiring in a semiconductor device having a redundant circuit.
(b) 技術の背景
LSIなど高集積度の半導体集積回路装置（IC）
に於ては、同一半導体基板上に予めメイン回路と
冗長回路を併設しておき、メイン回路部に不良が
発生した場合、冗長回路部を選択的に使用して集
積回路を構成することにより歩留まりの向上が図
られる。そしてこの際不必要な冗長回路若しくは
メイン回路の切り離しは、これら回路の基部に接
続されているフユーズ配線を切断することによつ
てなされる。(b) Technology background Highly integrated semiconductor integrated circuit devices (IC) such as LSI
In this case, a main circuit and a redundant circuit are installed on the same semiconductor substrate in advance, and if a defect occurs in the main circuit part, the redundant circuit part is selectively used to construct an integrated circuit, thereby reducing the yield. This will lead to improvements in At this time, unnecessary redundant circuits or main circuits are disconnected by cutting fuse wiring connected to the bases of these circuits.
フユーズ配線の切断方式には通電溶断方式とエ
ネルギー線焼去方式とがあり、本発明は通電溶断
方式に於けるフユーズ配線構造の改良に関するも
のである。 There are two methods for cutting fuse wiring: an energization fusing method and an energy beam burning method. The present invention relates to an improvement in the fuse wiring structure in the energization fusing method.
(c) 従来技術と問題点
通電溶断方式のフユーズ配線の材料には主とし
て多結晶シリコン（Si）が用いられ、フユーズ部
の構造は従来第１図に示す透視平面図イ及び断面
図ロのように、半導体基板１上に形成された１
〔μｍ〕程度の一様な厚さを有する二酸化シリコ
ン（SiO2）絶縁膜２上に、1.5〔μｍ〕程度の一定
の幅ｗ、0.4〔μｍ〕程度の一様な厚さｔを有し、
且つ10〔μｍ〕程度の長さｌを有する機能領域を
持つ多結晶Siフユーズ配線３が配設され、該多結
晶Siフユーズ配線３の機能領域を除く両端部が２
〜３〔μｍ〕程度の幅を有するアルミニウム
（Al）配線４及び４′に埋設接続されており、こ
れら領域の上部が２〔μｍ〕程度の厚さを有する
りん珪酸ガラス（PSG）表面保護（カバー）膜
５で覆われてなつていた。(c) Conventional technology and problems Polycrystalline silicon (Si) is mainly used as the material for fuse wiring in the current blowing method, and the structure of the fuse part is conventionally as shown in the perspective plan view A and cross-sectional view B shown in Figure 1. 1 formed on the semiconductor substrate 1
A silicon dioxide (SiO 2 ) insulating film 2 having a uniform thickness of about [μm] has a constant width w of about 1.5 [μm] and a uniform thickness t of about 0.4 [μm]. ,
In addition, a polycrystalline Si fuse wiring 3 having a functional area having a length l of about 10 [μm] is provided, and both ends of the polycrystalline Si fuse wiring 3 excluding the functional area are 2.
It is buried and connected to the aluminum (Al) wiring 4 and 4' having a width of about 3 [μm], and the upper part of these areas is covered with a phosphosilicate glass (PSG) surface protection (about 2 [μm] thick). cover) was covered with a membrane 5 and warped.
しかしながら、上記のような従来構造に於て
は、溶断に際して、フユーズ配線３の広い面積を
有する機能部全体をSiの溶融温度以上に昇温せし
めねばならないために、高い溶断電圧と大きな溶
断電流が必要になるという問題があつた。 However, in the conventional structure as described above, when blowing out, the temperature of the entire functional part of the fuse wiring 3, which has a large area, must be raised above the melting temperature of Si, resulting in a high blowout voltage and a large blowout current. The problem was that it was needed.
又溶断に際して、広い面積を有するフユーズ配
線３の機能部から放出される大きな熱エネルギー
によつて、該フユーズ機能部上のPSGカバー膜
５が爆発的に破砕し、フユーズ部上に大きな穴が
形成されるために、カバーPSG膜５の保護効果
が損なわれ、ICの信頼性が低下するという問題
もあつた。 Furthermore, when the fuse is blown, the PSG cover film 5 on the fuse wiring 3 is explosively ruptured due to the large thermal energy released from the functional part of the fuse wiring 3, which has a large area, and a large hole is formed on the fuse. Therefore, there was a problem that the protective effect of the cover PSG film 5 was impaired and the reliability of the IC was lowered.
(d) 発明の目的
本発明は、表面保護膜を破損させずに溶断する
ことが可能な通電溶断型のフユーズ配線構造を提
供するものであり、その主たる目的は冗長回路を
有する半導体ICの信頼性を向上せしめることに
ある。(d) Purpose of the Invention The present invention provides an electrically blown fuse wiring structure that can be blown without damaging the surface protective film, and its main purpose is to improve the reliability of semiconductor ICs having redundant circuits. The goal is to improve sexuality.
(e) 発明の構成
即ち本発明は半導体装置に於て、半導体基板上
の絶縁膜に選択的に周囲より絶縁膜厚の厚い台状
領域を設け、該絶縁膜上に、前記台状領域上を横
切つて該台状領域周囲の膜厚の薄い絶縁膜上まで
延在し、且つ該台状領域上の一部に選択的に、他
の領域より断面積を縮小して高抵抗にした被溶断
部を有する通電溶断型の多結晶シリコン・フユー
ズ配線が配設されてなることを特徴とする。(e) Structure of the Invention In other words, the present invention provides a semiconductor device in which an insulating film on a semiconductor substrate is selectively provided with a plateau-like region having a thicker insulating film than the surrounding area, and a plate-like region on the insulating film is formed on the insulating film. and extends over the thin insulating film around the plateau region, and selectively makes the cross-sectional area of a part of the plateau region higher than that of other regions. It is characterized by disposing a polycrystalline silicon fuse wiring of an energized fusion type having a portion to be fused.
(f) 発明の実施例
以下本発明を実施例について、図を用いて詳細
に説明する。(f) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.
第２図は本発明の半導体装置に於けるフユーズ
部の一実施例に於ける透視平面図イ及び断面図ロ
である。 FIG. 2 is a perspective plan view (A) and a cross-sectional view (B) of an embodiment of a fuse portion in a semiconductor device of the present invention.
本発明を適用して形成した冗長回路を有する半
導体ICに於けるフユーズ部は、半導体基板１１
上の絶縁膜例えばフイールド酸化膜１２にフオ
ト・エツチング技術を用いて選択的に台状領域１
３を形成し、該フイールド酸化膜１２上に前記台
状領域１３上を横切り且つ台状領域１３上に一
部、膜厚を薄くして他の領域より高抵抗に形成し
た部分１４を有する通電溶断型の多結晶シリコン
（Si）フユーズ配線１５が配設され、該フユーズ
配線１５が前記台状領域１３の周辺部に形成され
ているフイールド酸化膜１２の凹部１６上に於
て、メイン回路或るいは冗長回路の基部に当たる
アルミニウム（Al）配線１７，１７′間に挿入接
続され、これら領域上が他の領域と共に厚さ２
〔μｍ〕程度のカバーPSG膜１８によつて覆われ
てなつている。 In a semiconductor IC having a redundant circuit formed by applying the present invention, a fuse portion is formed on a semiconductor substrate 11.
The upper insulating film, for example, the field oxide film 12, is selectively etched using a photo-etching technique.
3, and has a portion 14 on the field oxide film 12 that crosses over the plateau region 13 and is partially formed on the plateau region 13 to have a thinner film thickness and higher resistance than other regions. A blowout type polycrystalline silicon (Si) fuse wiring 15 is disposed, and the main circuit or The wiring is inserted between the aluminum (Al) wiring 17, 17' which is the base of the redundant circuit, and the thickness of these areas along with other areas is 2.
It is covered with a cover PSG film 18 of about [μm].
なお上記フユーズ部に於けるフイールド酸化膜
１２上の台状領域１３は、フオト・エツチング技
術を用いてフイールド酸化膜に選択的に凹部１６
を形成することにより幅w6〔μｍ〕程度に作ら
れ、例えばフイールド酸化膜１３の厚さが１〔μ
ｍ〕程度の場合、凹部１６の底に厚さh′0.3〔μ
ｍ〕程度のフイールド酸化膜１２を残す必要があ
ることを考慮すると、その高さｈは0.7〔μｍ〕程
度となる。 Note that the plateau region 13 on the field oxide film 12 in the fuse section is formed by selectively forming a recess 16 in the field oxide film using photo-etching technology.
For example, the thickness of the field oxide film 13 is about 1 [μm].
m], the bottom of the recess 16 has a thickness of h'0.3 [μ
Considering that it is necessary to leave a field oxide film 12 of about 0.7 μm, the height h is about 0.7 μm.
又多結晶Siフユーズ配線１５は化学気相成長、
パターンニング、不純物イオン注入工程を経てゲ
ート電極等と同時に、例えば厚さt0.4〔μｍ〕、機
能部の幅wf1.5〔μｍ〕、機能部の長さl10〔μｍ〕、
比抵抗10-3〔Ω−cm〕程度に形成される。又該フ
ユーズ配線１５に於ける前記台状領域１３上の高
抵抗部１４は選択エツチング技術により、例えば
長さl′2〔μｍ〕程度の領域を0.2〔μｍ〕程度の厚
さt′に薄くすることによつて形成される。 In addition, the polycrystalline Si fuse wiring 15 is formed by chemical vapor deposition,
After the patterning and impurity ion implantation process, the gate electrode etc. are formed at the same time, for example, the thickness t0.4 [μm], the width of the functional part w f 1.5 [μm], the length of the functional part l10 [μm],
It is formed with a specific resistance of about 10 -3 [Ω-cm]. The high resistance portion 14 on the platform area 13 of the fuse wiring 15 is thinned, for example, from a region with a length of about l'2 [μm] to a thickness of about 0.2 [μm] by selective etching technology. It is formed by
なお上記高抵抗部１４は、本実施例のように多
結晶Siフユーズ配線１５の厚さを局部的に薄くす
る方法の外に、その幅を局部的に狭くする方法、
或るいはこれらの方法の組み合わせによつて形成
することもできる。 In addition to the method of locally reducing the thickness of the polycrystalline Si fuse wiring 15 as in this embodiment, the high-resistance portion 14 can be formed using a method of locally narrowing its width.
Alternatively, it can also be formed by a combination of these methods.
又該高抵抗部１４の抵抗値の上限は、回路機能
に悪影響を及ぼさない値に制限される。そして又
溶断の確実性を考慮した場合、その長さl′は上記
２〔μｍ〕程度が下限となる。 Further, the upper limit of the resistance value of the high resistance section 14 is limited to a value that does not adversely affect the circuit function. Furthermore, when considering the reliability of fusing, the lower limit of the length l' is about 2 [μm].
上記本発明のフユーズ構造に於ては、多結晶Si
フユーズ配線１５に溶断電流を流した際該フユー
ズ配線１５は、半導体基板１１に向かう熱抵抗の
大きいフイールド酸化膜１２の台状領域１４に位
置する部分が主として昇温し、更にこの部分に選
択的に形成されている高抵抗部１４の発熱量が特
に大きいため該高抵抗部１４が特に高温になり溶
断する。 In the above fuse structure of the present invention, polycrystalline Si
When a fusing current is applied to the fuse wiring 15, the temperature of the fuse wiring 15 is mainly increased in the portion located in the platform region 14 of the field oxide film 12, which has a large thermal resistance toward the semiconductor substrate 11, and furthermore, the temperature is selectively increased in this portion. Since the amount of heat generated by the high-resistance portion 14 formed in the wafer is particularly large, the high-resistance portion 14 reaches a particularly high temperature and is fused.
このように本発明の構造に於ては昇温効率が極
めて良いので溶断電流も従来の1/5程度に低減す
ることができる。 As described above, in the structure of the present invention, the temperature increase efficiency is extremely high, so that the fusing current can be reduced to about 1/5 of the conventional one.
又上記のように溶断部分が極めて微小領域に制
限され、且つ溶断電流が小さいため溶断部の発熱
量も少ないので、溶断に際してフユーズ部上の
PSGカバー膜１８が損傷を受けることがない。 In addition, as mentioned above, the fused part is limited to an extremely small area, and the fusing current is small, so the amount of heat generated at the fused part is small, so when the fuse is blown, the amount of heat generated by the fused part is small.
The PSG cover membrane 18 is not damaged.
更に又溶断部分が高抵抗部１４に限定されるこ
とにより溶断が確実になる。 Furthermore, since the fusing portion is limited to the high resistance portion 14, fusing is ensured.
(g) 発明の効果
以上説明したように本発明の特徴を具備した通
電溶断型のフユーズ構造に於ては、低電流で溶断
が可能であり、且つ溶断の確実性が確保され、更
に溶断に際して表面保護膜の損傷を伴わない。(g) Effects of the Invention As explained above, in the current-flow fuse structure having the features of the present invention, it is possible to fuse with a low current, the reliability of the fuse is ensured, and the No damage to the surface protective film.
従つて本発明は冗長回路を有する半導体ICの
製造歩留まり、信頼性の向上に対して有効であ
る。 Therefore, the present invention is effective in improving the manufacturing yield and reliability of semiconductor ICs having redundant circuits.
第１図は従来の通電溶断型フユーズ部の透視平
面図イ及び断面図ロで、第２図は本発明の一実施
例に於ける透視平面図イ及び断面図ロである。
図に於て、１１は半導体基板、１２はフイール
ド酸化膜、１３はフイールド酸化膜の台状領域、
１４は高抵抗部、１５は多結晶シリコン・フユー
ズ配線、１６はフイールド酸化膜の凹部、１７，
１７′はアルミニウム配線、１８はりん珪酸ガラ
ス表面保護膜を示す。
FIG. 1 is a perspective plan view (a) and a sectional view (b) of a conventional energized fuse part, and FIG. 2 is a perspective plan view (a) and a sectional view (b) of an embodiment of the present invention. In the figure, 11 is a semiconductor substrate, 12 is a field oxide film, 13 is a plateau region of the field oxide film,
14 is a high resistance part, 15 is a polycrystalline silicon fuse wiring, 16 is a recess in a field oxide film, 17,
17' is an aluminum wiring, and 18 is a phosphosilicate glass surface protective film.
Claims (1)
縁膜厚の厚い台状領域を設け、 該絶縁膜上に、 前記台状領域上を横切つて該台状領域周囲の膜
厚の薄い絶縁膜上まで延在し、 且つ該台状領域上の一部に選択的に、他の領域
より断面積を縮小して高抵抗にした被溶断部を有
する通電溶断型の多結晶シリコン・フユーズ配線
が配設されてなることを特徴とする半導体装置。[Scope of Claims] 1. An insulating film on a semiconductor substrate is selectively provided with a pedestal region having a thicker insulating film thickness than the surrounding area, and on the insulating film, a region around the pedestal region is provided across the insulating film. An electric fusing type which extends over a thin insulating film, and has a fusing part selectively on a part of the plateau-shaped region, the cross-sectional area of which is made smaller than that of other regions to make the resistance higher. A semiconductor device characterized by being provided with polycrystalline silicon fuse wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17885882A JPS5968946A (en) | 1982-10-12 | 1982-10-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17885882A JPS5968946A (en) | 1982-10-12 | 1982-10-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5968946A JPS5968946A (en) | 1984-04-19 |
| JPH0479137B2 true JPH0479137B2 (en) | 1992-12-15 |
Family
ID=16055911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17885882A Granted JPS5968946A (en) | 1982-10-12 | 1982-10-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5968946A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59146969U (en) * | 1983-03-23 | 1984-10-01 | 日本電気株式会社 | semiconductor equipment |
| JPS6334952A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Fuse for selection of circuit within semiconductor device |
-
1982
- 1982-10-12 JP JP17885882A patent/JPS5968946A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5968946A (en) | 1984-04-19 |
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