JPH0478247A - Packet synchronization recovery circuit - Google Patents

Abstract

PURPOSE:To operate the circuit so as to be synchronously with a transmission clock at a sender side at all times and to prevent it in advance that picture packet communication has a difficulty by generating a packet time series signal from a received picture packet signal, calculating a moving mean from the signal and generating a clock generating signal from the moving mean. CONSTITUTION:A packet decomposing means 2 uses a decomposition command signal S2 from a synchronization pattern detection section 1 to decompose a picture packet signal S1 into a header signal S3 and a packet information signal S4. A packet abort detection means 3 receives the signal S3 to output a packet abort detection signal S5. A logic channel detection means 4 receives the signal S3 to output a logic channel detection signal S6. A significant packet detection means 5 receives the signal S3 to output a significant packet detection signal S7. A timing control means 6 receives the signals S5-S7 to output a clock generating signal S8. A reception clock generating means 7 receives the signal S8 to output a reception clock signal S9. A buffer memory 8 receives the signal S4 to output a picture information signal S1O synchronously with the signal S9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an image packet communication device system connected to a high-speed packet switching network. The present invention relates to a packet synchronization regeneration circuit that performs clock timing regeneration.

BACKGROUND OF THE INVENTION Traditional packet switching is designed to efficiently transmit data information. Furthermore, loss of data information due to transmission errors is dealt with by retransmitting data with flow control as error control.

However, the upper limit of the packet transmission speed of a packet switching network for data transmission is 64 kbit/s, which is not suitable for transmitting audio and image information in communications that require real-time performance.

On the other hand, the packet transmission speed of information targeted for high-speed packet switching is 1.5 Mbit, which is the primary speed of digital networks.
/s or more. In high-speed packet switching networks, it is possible to uniformly transmit various types of information such as voice, image, and data, which have different transmission speeds, as voice packets, image packets, and data packets using high-speed packets. can also be handled flexibly. In addition, efficient operation of the transmission path can be expected due to the statistical multiplexing effect that takes advantage of the burst nature of the information source. Burst nature refers to the property that the amount of information generated from an information source fluctuates over time. The statistical multiple effect is an effect in which information that does not change over time is obtained by overlapping information from multiple disparate information sources whose information amount fluctuates. Here, a high-speed packet is a short packet with a fixed length (for example, 32 bytes = 256
shall be handled in bits). Increases and decreases in transmitted information due to burst fluctuations in the amount of generated information correspond to increases and decreases in the number of high-speed packets generated. In a high-speed packet switching network, the transmission route within the network is fixed in order to guarantee the order of transmission of high-speed packets. Furthermore, in order to guarantee the real-time nature of audio and image information, error control such as retransmission is not performed within the network exclusively for the transmission of high-speed packets.

In the image packet transmitting device, after encoding input image information, an image packet signal consisting of a header signal and a packet information signal is generated in a packet assembling unit and sent out to a transmission path. The image packet signal is transmitted within a high-speed packet switching network and arrives at the target image packet receiving device.

In the image packet receiving device, the received image packet signal is separated into a header signal and a packet information signal by a packet decomposition unit, and then decoded to reproduce image information.

(Problems to be Solved by the Invention) However, the above-described conventional technology has the following problems.

In other words, in a high-speed packet switching network, the transmission path between switches uses link piping, unlike in a conventional packet switching network.
Does not perform link flow control or error control. Therefore,
When there is a temporary overload of communication traffic in a high-speed packet switching network, packet overflow occurs due to packet multiplexing at nodes. This overflow causes packet drop and packet discard. When an image packet signal output from an image packet transmitting device of an image packet communication device system connected to a high-speed packet switching network is discarded within the packet switching network, the image packet receiving device at the arrival point ,
There has been a problem in that image information is missing, resulting in significant deterioration of image quality.

Furthermore, since the high-speed packet network is an asynchronous network that assumes packet synchronization, the transmission clock on the transmitting side and the receiving clock on the receiving side are asynchronous with each other. Therefore, due to temporary fluctuations in the load status of communication traffic in the high-speed packet switching network, the arriving packets at the receiving side will fluctuate, so the reception clock regenerated from the 58M packet will have slight fluctuations (referred to here as jitter). Occur. This jitter makes the reception clock unstable at the image packet receiving device at the arrival point, resulting in a problem of significant deterioration of image quality when reproducing image information.

The present invention has been made in view of the above points, and eliminates the drawbacks of the conventional image packet communication device system. It is an object of the present invention to provide a packet synchronization reproducing circuit for an image packet receiving device, which causes less deterioration of image quality on the side and avoids difficulties in image communication.

(Means for Solving the Problems) The packet synchronization reproducing circuit of the present invention includes a synchronization pattern detection means that inputs an image packet signal, identifies a pattern specific to the packet, and outputs a decomposition instruction signal, and a packet disassembly means for disassembling an image packet signal into a header signal and a packet information signal in response to a disassembly instruction signal from the unit; a packet discard detection means for inputting the header signal and outputting a packet discard detection signal; Logical channel detection means that inputs the header signal and outputs a logical channel detection signal; Priority packet detection means that inputs the header signal and outputs a significant packet detection signal; Packet discard detection signal, logical channel detection signal, and significant packet detection timing control means that inputs signals, generates a packet time series signal from these signals, calculates a moving average from the packet time series signal, and generates and outputs a clock generation signal from the moving average calculation signal; It is characterized by comprising a reception clock generation means which inputs the clock generation signal and outputs a reception clock signal, and a buffer memory which inputs the packet information signal and outputs an image information signal in synchronization with the reception clock signal. That is.

(Operation) In the packet synchronization reproduction circuit of the present invention, when an image packet signal is input to the synchronization pattern detection means, a pattern unique to the packet is identified. Based on this identification, the packet disassembly means separates the image packet signal into a header signal and a packet information signal. Thereafter, the header signal is input to the packet discard detection means, the logical channel detection means, and the significant packet detection means. Then, each detection means outputs a packet discard detection signal, a logical channel detection signal, and a significant packet detection signal to the timing control means. The timing control means generates a packet time series signal, calculates a moving average from this packet time series signal, and generates a clock generation signal from this moving average calculation signal. Therefore, the generated clock generation signal is less affected by jitter. The receiving clock generating means inputting this clock generating signal outputs a receiving clock signal. This received clock signal allows high quality image information to be reproduced.

(Embodiment) FIG. 3 is a diagram showing the connection relationship of a high-speed packet switching network according to the present invention.

The image packet transmitting device 31 receives an image input signal and outputs an image packet signal, and the clock circuit 32 generates a transmitting side clock signal. The image packet signal is transmitted within the high-speed packet switching network 33 and input to the image packet receiving device 34 at the arrival point. The image packet receiving device 34 inputs the image packet signal and outputs an image output signal, and the packet synchronization reproducing circuit 35 generates a receiving side clock signal based on the received image packet signal.

FIG. 1 is a block diagram showing an embodiment of a packet synchronous reproducing circuit of the present invention.

The illustrated circuit includes a synchronization pattern detection means 1, a packet disassembly means 2, a packet discard detection means 3, a logical channel detection means 4, a priority packet detection means 5, a timing control means 6, and a reception clock generation means. 7 and a buffer memory 8.

The synchronization pattern detection means 1 inputs the image packet signal S1, identifies a pattern unique to the packet, and outputs a decomposition instruction signal S2. Here, the pattern unique to a packet refers to a unique pattern in the header signal of a packet signal that can be distinguished from other information signals.

FIG. 4 is a diagram showing an example of a data arrangement of a packet signal.

The illustrated packet signal consists of a header signal and a packet information signal.

The header signal includes a flag pattern F, a logical channel number LCN, a sequence number SQN, and a packet type PT.
It consists of

Flag pattern F is a pattern unique to a packet, and is composed of, for example, an 8-bit string r0IIIIIIOJ. By using such a flag pattern F, on the receiving side, it is possible to identify the break in the packet signal by detecting that six "l"s are received in succession.

The logical channel number LCN indicates the number of the logical channel through which the packet signal is transmitted.

The sequence number SQN is a number assigned on the transmitting side in the order in which packet signals are generated. For example, if 8 bits are assigned to the sequence number SQN, 28 (=25
6) Assign sequential numbers "0 to 255". This allows the receiving side to check the continuity of sequence numbers and identify discarded packets. For example, if discontinuous sequence numbers such as "0.1.2.3.5.6.7.8,..." are received, it is recognized that the packet signal with sequence number 4 has been discarded. can do.

The packet type PT indicates the type of the packet, and indicates, for example, that the packet is an image packet.

The packet information signal INF is for sending information such as image information sent by a packet signal.

Regarding the packet signal configured in this way, synchronization is achieved on the receiving side based on the position of the flag pattern F.

FIG. 5 is a diagram showing an example of flag strings on the transmitting side and receiving side of a packet signal.

On the receiving side, the flag pattern F of the packet signal is detected to identify the break in the packet signal. In this case, a packet signal is transmitted from the transmitting side in synchronization with a predetermined clock signal.

That is, as shown in FIG. 5(a), the flag string Fs of the transmitting side packet signal is equally spaced.

Therefore, if the physical transmission route within the high-speed packet network is completely fixed, there would be no need to synchronize other packet signals by synchronizing with the flag pattern of one packet signal.

However, in reality, within a high-speed packet switching network, the transmission route may change slightly due to subtle changes in the switches of the exchange.

Therefore, as shown in FIG. 5(b), the flag string F of the receiving side packet signal is not spaced at equal intervals and has minute delay fluctuations. This variation is called jitter variation. Due to such jitter fluctuations, when synchronization is achieved using the flag pattern of one packet signal, synchronization will occur with other packet signals.

Therefore, in the present invention, synchronization is achieved at a position determined by averaging the positions of the flag patterns of a plurality of packet signals. This operation is performed by timing control means 6, which will be described later.

Here, we return to the explanation of FIG. 1 again.

The packet decomposition means 2 decomposes the image packet signal S1 into a header signal S3 and a packet information signal S4 in response to a decomposition instruction signal S2 from the synchronization pattern detection section 1.

The packet discard detection means 3 receives the header signal S3 and outputs a packet discard detection signal S5.

The packet discard detection procedure is explained in the fourth section mentioned above.
As stated in the explanation of the figure.

The logical channel detection means 4 receives the header signal S3 and outputs a logical channel detection signal S6.

That is, the logical channel detection means 4 detects the logical channel number LCN of the header signal shown in FIG. If this logical channel number changes, it means that the transmission route within the high-speed packet switching network has changed, so it is necessary to resynchronize.

The significant packet detection means 5 receives the header signal s3 and outputs a significant packet detection signal S7.

The timing control means 6 inputs the packet discard detection signal S5, the logical channel detection signal S6, and the significant packet detection signal S7, and outputs the clock generation signal S8.

The reception clock generation means 7 inputs the clock generation signal S8 and outputs the reception clock signal S9.

The buffer memory 8 inputs the packet information signal S4,
The image information signal is output in synchronization with the reception clock signal S9.

FIG. 2 is a block diagram showing the detailed configuration of the timing control means.

As shown, the timing control means includes a pseudo packet generation means 21, a composite packet generation means 22, a moving average calculation means 23, and a phase locked loop means 24.

The pseudo packet generating means 21 generates a packet discard detection signal S.
5 to generate a pseudo packet generation signal. That is, the pseudo packet generating means 21 generates a pseudo packet to be used in place of the discarded packet.

The composite packet generation means 22 generates a pseudo packet generation signal S.
21 and a significant packet detection signal S5 are input, and a packet time series signal S22 is output.

The moving average calculation means 23 inputs the packet time series signal S22 and outputs a moving average calculation signal S23.

The phase locked loop (PLL) means 24 receives the moving average calculation signal S23 and outputs the clock generation signal S8.

This phase locked loop means 24 includes a phase comparator (PC) 4
1, a low-pass filter (LPF) 42, a voltage-controlled optical oscillator (VC○) 43, and a clock frequency divider (DV) 44.

The phase-locked loop means 24 has a circuit configuration that performs feedback control so that the oscillation frequency and phase of the voltage-controlled optical oscillator 43 are always constant with the input signal. That is, a clock frequency division signal S24, which will be described later, is input to the phase comparator 41 together with the moving average calculation signal, and a phase error signal S41 between the two is output. This phase error signal S41 is passed through a low-pass filter 42.
and drives the voltage-controlled optical oscillator 43 in the next stage.

The voltage-controlled optical oscillator 43 generates a clock generation signal S8, and this clock generation signal S8 is sent to the reception clock generation means 7 shown in FIG. Further, the output of the voltage-controlled optical oscillator 43 is input to a clock frequency divider 44, which outputs a clock frequency divided signal S24 close to the frequency of the moving average calculation signal S23. .

This clock frequency divided signal S24 is then sent to the phase comparator 41 mentioned above.

As a numerical example, when the bit rate of the moving average calculation signal 323 is 1.5 Mbit/s, the clock generation signal S which is the output of the voltage controlled optical oscillator 43 of the phase locked loop means 24
8 is 27 MHz, and the frequency of the clock frequency divided signal S24 obtained by dividing this 27 MHz by 18 is 1.5 MHz. In particular, in the field of moving image signals, 13.5 MHz, which is 27 MHz divided by two, is used as the clock frequency for component encoding.

For the definition of moving average, see, for example, the title of the document: Mitsuaki Fujii, "Time Series Analysis J," first published December 15, 1974,
Corona Publishing, p. 204 states as follows:

The observed next series X (t) is the sum of the mean value function m (t) and the variation value function g (t), and is expressed as
It is expressed as (t)+ε(1).

The values at the times before and after a certain time t are respectively weighted, and the weighted average value is set as the value at the time t. Expressing this mathematically, time t+j (-L≦j≦L
) is the weight to be applied to the value of q.

Then, the moving average Y(t) is Y(t) = ΣJll−LLQJ X (t + J
). Therefore, the moving averaged mean value function m
(t) and the fluctuation value function ε(1) are respectively the moving average average value function m(t): A, =ΣJ=−LLQJ X (t + j) the moving average fluctuation value function ε(t); Av"ΣJ=-LLqJ X (t+j).

In this embodiment, the data of the packet time series signal S22 generated as described above is input from the image packet signal S1, and the data is The moving average of the packet generation rate is calculated according to the above formula, and the average value A of the moving average of the packet generation rate is calculated. and find the fluctuation value Av. And this average value A,
Let be the moving average calculated value.

Next, the operation of the circuit described above will be explained.

The synchronization pattern detection means 1 that receives the image packet signal identifies a pattern unique to the packet and outputs a decomposition instruction signal S2. Then, in response to this disassembly instruction signal S2, the packet disassembling means 2 separates the image packet signal S1 into a header signal S3 and a packet information signal S4.

First, the header signal S3 is sent to the packet discard detection means 3,
The signal is input to the logical channel detection means 4 and the significant packet detection means 5. Then, each detection means outputs a packet discard detection signal S5, a logical channel detection signal S6, and a significant packet detection signal S7 to the timing control means 6. In the timing control means 6, the clock generation signal S
8 is generated. The reception clock generation means 7 which manually generates the clock generation signal S8 outputs the reception clock signal S9.

On the other hand, the packet information signal S4 is input to the buffer memory 8, and is first-in first-out (FIFO).
) operation, information is accumulated by the operation, and the received clock signal S
At read timing 9, the speed-converted buffer output image information signal SIO is output.

Here, it is assumed that timing control is performed on a channel-by-channel basis with respect to a specific channel detected in advance by the logical channel detection means 4.

(Effects of the Invention) As explained above, according to the present invention, in the image packet receiving device, a packet time series signal of packets synthesized from packet discard detection and significant packet detection of the received image packet signal is generated. Since the moving average is calculated from this packet time series signal and the clock generation signal is generated from this moving average calculation signal, the following effects can be obtained.

In other words, even if packet discards or jitter fluctuations occur in the image packet signal temporarily in a high-speed packet switching network, the receiving clock on the receiving side can be stabilized and always synchronized with the transmitting clock on the transmitting side. Since it can be operated, it has the effect of preventing image packet communication from becoming difficult.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the packet synchronization regeneration circuit of the present invention, FIG. 2 is a block diagram showing the detailed configuration of the timing control means, and FIG. 3 is the connection relationship of the high-speed packet switching network according to the present invention. FIG. 4 is a diagram showing an example of a data arrangement of a packet signal, and FIG. 5 is a diagram showing an example of flag strings on the transmitting side and receiving side of the packet signal. DESCRIPTION OF SYMBOLS 1... Synchronization pattern detection means, 2... Packet disassembly means, 3... Packet discard detection means, 4... Logical channel detection means, 5... Significant packet detection means, 6... Timing control Means, 7... Reception clock generating means, 8... Buffer memory, 21... Pseudo packet generating means, 22... Composite packet generating means, 23... Moving average calculating means, 24... Phase Synchronous loop means, 41... Phase comparator, 420.8 Low pass filter, 43... Voltage controlled optical oscillator, 44... Clock frequency divider.

Claims (1)

[Claims] 1. Synchronous pattern detection means that inputs an image packet signal, identifies a pattern unique to the packet, and outputs a decomposition instruction signal; packet disassembly means for disassembling the signal into a header signal and a packet information signal; packet discard detection means for inputting the header signal and outputting a packet discard detection signal; and inputting the header signal and outputting a logical channel detection signal. a logical channel detection means; a preferential packet detection means that inputs the header signal and outputs a significant packet detection signal; inputs a packet discard detection signal, a logical channel detection signal, and a significant packet detection signal; a timing control means for generating a packet time series signal, calculating a moving average from the packet time series signal, and generating and outputting a clock generation signal from the moving average calculation signal; 1. A packet synchronization reproducing circuit comprising a reception clock generating means for outputting a signal, and a buffer memory for inputting the packet information signal and outputting an image information signal in synchronization with the reception clock signal. 2. The timing generation means includes pseudo packet generation means that generates a pseudo packet generation signal from the packet discard detection signal, and receives the pseudo packet generation signal and the significant packet detection signal and outputs a packet time series signal. Comprised of a composite packet generation means, a moving average calculation means for inputting the packet time series signal and outputting a moving average calculation signal, and a phase locked loop means for inputting the moving average calculation signal and outputting a clock generation signal. A packet synchronization reproducing circuit characterized by: