JPH0477855A - Microcomputer circuit - Google Patents

Abstract

PURPOSE:To attain the special processing to recover the runaway of a microcomputer by providing a means to decide the 1st or 2nd reset signal that reset the microcomputer. CONSTITUTION:When a master microcomputer 1 is reset, the deciding means 1 and 9 decide whether the microcomputer 1 is reset by a 1st reset signal (computer reset signal) produced by a watchdog timer 4 owing to the runaway of the microcomputer 1 or by a 2nd reset signal, e.g., a power-on reset signal produced at application of the power supply of the microcomputer 1. Thus the runaway of the microcomputer 1 is decided. Then the special processing is attained so that the runaway is recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer circuit comprising a microcomputer, and particularly to detection of runaway of the microcomputer in the circuit.

[Conventional technology]

A conventional example of this type of circuit is shown in FIG. In this circuit, a dual port RAM 3 is connected to a mask microcomputer 1 and a slave microcomputer 2. Hereinafter, the microcomputer will be referred to as a CPU.

The CPUI transfers data or signals to the CPU2 to the RAM3.
1, and the CPU 2 reads this data or signal from the RAM 3, thereby transferring data or signals from the CPU 2 to the CPU 1, and vice versa.
The CPU 2 writes data or signals to be given to the CPU in the RAM 3, and the CPU 1 reads the data or signals from the RAM 3, thereby transferring data or signals from the CPU 2 to the CPU 1.

That is, CPU 1. / CPU 2 communication is performed via RAM 3.

A watchdog timer 4 is provided to detect runaway of the CPUI and 2. A reset signal from the CPU I2 for resetting (restarting/retriggering) the watchdog timer 4 is applied to the determination circuit 5.

available. The determination circuit 5 provides the watchdog timer 4 with 9 set signals at intervals shorter than the time limit T while the set signals from CP tJ ] and CP 2 arrive within predetermined time intervals. The dog timer 4 does not time out (completion of timing T). When CPUI or 2 no longer generates a reset signal,
Or, the reset signal period is longer than a predetermined time interval (if this happens, the determination circuit 5 does not give a reset signal to the watchdog timer 4, or is delayed in giving it to the watchdog timer 4, causing the watchdog timer 4 to time out and generate a computer reset signal. Then reset the CPUUI and 2 people on the end of the R3T
give to When CPUs 1 and 2 receive this set signal, they return to the same state as the initial state immediately after power-on.
From there, start running the program again.

Another conventional circuit is shown in FIG. In this,
CPU 1 has a watchdog timer of 4°, and C
Watchdog timer 4° is connected to PU2, and CP tJ 1 and CPU 2 each have timer 4. and 42 are provided with a reset signal at time intervals shorter than their time limits T1 and T2. When the CPUI no longer issues a reset signal, or when the interval between reset signals becomes longer than timer period T, timer 4. When the timeout occurs, a computer reset signal is generated through the NOR gate 6 and applied to the input terminal R3T of CP IJ 1 and 2. When the CPU 2 no longer issues a reset signal, or when the interval between reseller signals becomes longer than the timer time limit T2, the timer 42 times out and generates a computer reset signal via the NOR gate 6, which is sent to the CPU 2 and It is applied to the reset input terminal R3T. .

In either of the two conventional examples, if CPU U1 or 2 stops generating the timer reset signal I due to runaway, or if the generation of the reset signal is delayed, both CPU U1 and CPU2 are reset.

[Problem to be solved by the invention]

In the conventional example shown in FIGS. 5 and 6, the CPU 1
．． If CPU2 goes out of control, naturally the CPU
1. , it is not possible to save the fact that the CPU2 itself is running out of control in memory, and if the watchdog timer is reset, after the reset is released, it is difficult to determine whether this is the start of operation due to power-on, or the operation after the runaway is released. It is not possible to distinguish whether it is a start or not. When a runaway occurs, it is true that it is prevented from continuing, but from the perspective of employees and employers, the system suddenly initializes, and it is unclear what happened.

An object of the present invention is to detect the fact that a microcomputer has run out of control.

[Means to solve the problem]

When the microcomputer circuit of the present invention receives a restart signal (timer recent signal) within a predetermined time period T from the start of the timer, it starts a new timer operation, and if it does not receive a restart signal (timer reset signal), the predetermined timer expires. A watchdog timer (4) that gives a first reset signal (computer reset signal) that resets the microcomputer (+) described later when the time expires at T.
; Normal operation January: Give the restart signal (timer reset signal) to the watchdog timer (4), and respond to the first reset signal (computer reset signal) and the second reset signal (power-on reset signal) described below. A microcomputer that resets itself (1)
; Means (10) for generating a second reset signal (power-on reset signal) that resets the microcomputer (1) when the power is turned on; and means (10) for generating a second reset signal (power-on reset signal); The microcomputer (+) is reset by a determining means (1, 9) for determining which of the on-reset signals) has caused the microcomputer (+) to be reset.

Note that symbols in parentheses indicate corresponding elements in the embodiments shown in the drawings and described later.

[Effect]

When the microcomputer (1) has been reset, the determining means (1, 9) determines whether the reset signal (1, 9) is the first reset signal (computer It is determined whether the microcomputer (1) is newly reset by a second reset signal (reset signal) or by a second reset signal (power-on reset signal) when the microcomputer (1) is powered on.

Therefore, since it is known that the microcomputer (1) has gone out of control, it is possible to perform special processing such as recovery from the runaway, and the user can also check what happens when the microcomputer (1) is initialized. I am not confused as to whether it has occurred or not.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention. This embodiment is a control circuit for a copying machine, in which a master CPU, slave CPU2
The present invention is applied to the mask CPU 1. The master CPU performs system control of the copier, such as man/machine interface management, copy mode management, and copy sequence settings through the operation panel.Slave CPU2 executes the sequence instructed by the master CPU and makes copies. It performs so-called mechanism control, such as process control.

The master CPUI and slave CPU2 are connected via a dual port RAM3 as a communication means. When the master CPUI gives data or a signal to the slave CPU2, it writes it to RA, M3, and sends it to the slave CPU2.
U2 reads it from RAM3. Slave CPU2
When giving data or a signal to the master CPU, it writes it to the RAM 3, and the master CPU reads it.

A watchdog timer 4 is connected to the master CPUI, and the master CPUI outputs a timer reset signal to the watchdog timer 4 via an output port.

A computer reset signal is output from the watchdog timer 4, one of which is sent to the master C via the NOR gate 7.
It is connected to the reset input terminal R3T of PU1, and the other one is
Furthermore, it is connected to the reset input terminal R3T of the slave CPU 2 via the NOR gate 8. Also, Noah games 1-8
A slave input signal output from the output port I of the parallel I 10 of the master CPU 1 is input to the input signal. Therefore, when the watchdog timer 4 times out, a computer reset signal is applied to the master CPUI and the slave CPU 2 to perform a reset, and the master CPU can also reset the slave CPU 2 by software. When only the slave CPU 2 runs out of control, the master CPU is operating normally, so it can perform recovery processing after the runaway, and can notify users and external devices that a runaway has occurred.
PUI or master CPUI and slave CPU2
When a runaway occurs, it is impossible to monitor the runaway, so it is not possible to notify that the runaway has occurred.

Therefore, in this embodiment, a power-on reset generation circuit 10 using a voltage monitoring IC or the like is connected to the NOR gate 7, and an RS flip-flop 9 is connected to the master CPUI.

The power-on reset generation circuit 10 generates a signal (power-on reset signal) that resets the master CPUI and slave CPU 2 when the power is turned on. Also, since the terminal R of the RS flip-flop 9 is connected to the power-on reseller I/generation circuit 10, the RS flip-flop 9 is always reset by the power-on reset signal when the power is turned on, and the output at point a becomes L level. . Furthermore, since the master CPUI is connected to the terminal -11 to an output port that can be operated by software, the RS flip-flop 9 is set by the program of the mask CPUI.

With this configuration, the RS flip-flop 9 is set by software, and reset is possible only by the power-on reset signal, and is not affected by the reset signal output by the watchdog timer 4. In other words, when the program starts after the power is turned on, the RS flip-flop 9 is reset, and then the master CPU
Once the RS flip-flop 9 is set in the program, a reset signal is generated by the watchdog timer 4 to the master CPU I and the slave CPU 2, and even if the program starts after that, the state of the RS flip-flop 9 remains set. There is even. Therefore, master CPU 1 or master CPU I and slave C
Since the states of the R and S flip-flops 9 cannot be reset even if the PU2 goes out of control, the watchdog timer 4 can correctly remember whether or not it has been reset.

This operation will be explained using the timing chart shown in FIG. Note that signals a to e in FIG. 2 indicate output signals corresponding to each point a to e shown in FIG. 1.

When the power is turned on and the voltage rises to a certain value, each element becomes operational. Signal a is power-on reseller I.
It is time t after the voltage reaches a predetermined value by the generating circuit 101. t After holding the L level, it becomes the H level. R.S.
Since the flip-flop 9 is given an L level signal to the R terminal by the signal a when the power supply voltage reaches an operable value, the output signal d of the RS flip-flop 9 becomes the L level (the first When the signal at one point in the figure is at L level, the terminal of parallel I10 is high impedance and the signal C is at I] level because it is pulled up.Therefore, when signal a is at L level, signal C is at H level. Therefore, both terminals R and S are not at L level and RS
(The state of flip-flop 9 is determined). On the other hand, signal a
When becomes H level, the master CPUI starts executing the program.

At this time, the RS flip-flop 9 has been reset, so when the signal d is read by the program, it is at L level.

The mask CPUI generates a pulse on the signal e according to a program, and resets the watchdog timer 4 at the edge of the pulse. When this pulse is interrupted after a time T, the watchdog timer 4 activates the master CPU and slave CPU.
Generates a reset signal to PU2. In other words, after the signal 1] is kept at the L level for a predetermined period of time, the signal 1 is set to the level (2). If the master CPU is programmed so that the pulse generation period of the signal e is shorter than T, the reset signal is generated by the watchdog timer 4 only by the master CPU.
I is not running the program, that is, it is running out of control (mask CPUI or master CPU
and runaway of slave CPU2).

When the watchdog timer 4 sets the signal to L level due to runaway, the master CPU I and slave CPU 2 are reset, but the power-on reseller I/generation circuit 10
Since there is no voltage drop, the signal a remains at the H level without generating a power-on reset signal. At this time, since the signal cIj' is at H level, the state of the RS flip-flop 9 maintains the state before the signal became L level.

After a predetermined time, the signal l) goes to H level, the reset I state is released, and the mask CP tJ 1 starts executing the program. At this time, the state of the RS flip-flop 9 before it is set can be found by reading the signal d.

Therefore, when programming starts, check the signal d, and then set the signal C to L level to set the T<S flip-flop 9.
After the power-on reseller is turned on, the L level is read out by checking the signal d, and after being reset by the watchdog timer 4, the I-level is read out. This judgment determines whether or not there is a runaway.

Figure 3 shows the master CPU related to the runaway detection mentioned above.
An overview of the control operation is shown below. The program is started from "start" both after power-on reset and after reset by watchdog timer 4. Next, set the signals to be output during standby in the output capo) and set the internal registers, timers, flags, etc. for standby.
, read the signal d (2). At this time, if the signal d is at the L level in step 3, it is determined that the power has been turned on, and if the signal d is at the 1-] level, it is determined that the state has been reset by the watchdog timer 4, that is, after the runaway. to decide. Then, after the runaway, necessary processing is performed (4).

When the check of the signal d is completed, one pulse is outputted to the signal C (5 to 7), and the RS flip-flop 9 is set. Therefore, if a runaway occurs from now on and a reset by the watchdog timer 4 occurs, the occurrence of the runaway can be determined by steps 2 and 3 since the RS flip-flop 9 is set.

〔Effect of the invention〕

According to the present invention, a microcomputer (1
) has gone out of control, it becomes possible to perform special processing such as recovery from a runaway, and the user can also
I'm never confused about what happened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a time chart 1 showing the relationship between the output signals of each point a"e shown in FIG. 1. FIG.
3 is a flowchart showing a part of the control operation. FIG. 4 and FIG. 5 are block diagrams showing the outline of the configuration of a conventional microcomputer circuit. Dog timer (watchdog timer) 5
: Judgment circuit 6-8 Noah game)・9:
RS flip-flop IO power-on resetter 1 to generation circuit (1, 9 discrimination means)

Claims (1)

[Claims] If a restart signal is received within a predetermined time T from the start of the time limit, the timed operation will start anew, and if the restart signal is not received, the time will expire within the predetermined time T, and when the time is over, the microcomputer described below a watchdog timer that provides a first reset signal to reset the watchdog timer; a microcomputer that provides the restart signal to the watchdog timer during normal operation and resets itself in response to the first reset signal and the second reset signal described below; a means for generating a second reset signal for resetting the microcomputer when the power is turned on; and a determining means for determining which of the first reset signal and the second reset signal has reset the microcomputer; computer circuit.