JPH0477248U - - Google Patents
Info
- Publication number
- JPH0477248U JPH0477248U JP12053290U JP12053290U JPH0477248U JP H0477248 U JPH0477248 U JP H0477248U JP 12053290 U JP12053290 U JP 12053290U JP 12053290 U JP12053290 U JP 12053290U JP H0477248 U JPH0477248 U JP H0477248U
- Authority
- JP
- Japan
- Prior art keywords
- check terminal
- lead
- leads
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂ，ｃは、それぞれ本考案の一実施
例の平面図、側面図および断面図、第２図は第１
図のリードの拡大図である。 １……ＩＣ、２……リード、３……実装ピン部
、４……チエツク端子部。
例の平面図、側面図および断面図、第２図は第１
図のリードの拡大図である。 １……ＩＣ、２……リード、３……実装ピン部
、４……チエツク端子部。
Claims (1)
- 複数のリードを有するＩＣにおいて、リードに
チエツク用の端子を設けたことを特徴とするチエ
ツク端子付きＩＣ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12053290U JPH0477248U (ja) | 1990-11-16 | 1990-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12053290U JPH0477248U (ja) | 1990-11-16 | 1990-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0477248U true JPH0477248U (ja) | 1992-07-06 |
Family
ID=31868434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12053290U Pending JPH0477248U (ja) | 1990-11-16 | 1990-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0477248U (ja) |
-
1990
- 1990-11-16 JP JP12053290U patent/JPH0477248U/ja active Pending