JPH0477153A - Demodulation system - Google Patents

Abstract

PURPOSE:To prevent the leakage of a phase counter signal to a carrier wave signal by utilizing plural counters (Chinese number counter) equipped with dividing frequency to be prime each other. CONSTITUTION:In plural counters 4, the frequency is selected so as to turn the dividing number of each counter to be prime each other, and the product of the frequency number of each counter is selected to turn to be N. The output of each counter is stored in a latch 6 at the rising of the output signal. The contents stored in the latch 6 is inputted to an encoding circuit 5, and converted to a single output. The output signal of the encoding circuit 5 and a delay 7 are inputted to a comparison operation circuit 8, and a data is detected by the change of the phase of one baud section. When the frequency of an oscillator 3 is taken high enough compared with the center frequency of a phase modulation signal, the resolution of necessary phase measurement can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a demodulation method that inputs a signal phase-modulated by a digital signal and directly performs digital delay detection of the phase-modulated signal.

(Prior art) Conventionally, as a demodulation method in which a signal phase modulated by a digital data signal is input and demodulation is performed directly from an intermediate frequency signal by digital delay detection, a method as shown in Fig. 2 has been used. I've been exposed to it. The conventional demodulation method shown in FIG. 2 includes a limiter 101, a synchronization circuit 102, an oscillator 103,
It is composed of a counter 104, a latch 105, a delay 106, and a comparison calculation circuit 107. In this demodulation method, a limiter 101 converts a phase modulation signal into a logic level signal, and then a synchronization circuit 102 samples the baud timing signal with the logic level signal to perform baud timing synchronization. The output clock signal of the oscillator 103 is counted by a counter 104, and the output signal of the counter 104 is latched into a latch 105 by a baud timing signal synchronized by the synchronous north circuit R102. Furthermore, the output signal of the latch 105 is delayed by 106.
and delays the output signal by one baud period C+. The output signal of the latch 105 and the output signal of the delay 106 are input to a comparison calculation circuit 107, and a delayed detection output is obtained from the difference.

The output signal of this comparison calculation circuit 107 is a demodulated signal.

(Problems to be Solved by the Invention) The conventional demodulation method shown in FIG. 2 has a relatively simple circuit configuration and is suitable for integration. However, the counter 104
The final stage output of the carrier amplifier contains a frequency component that is the same as the center frequency of the phase modulation signal, and there is a high possibility that this output component will leak to the input stage of the carrier amplifier and cause interference. In order to prevent this, strict electromagnetic shielding is required, which has the drawback of increasing the weight and size of the receiver that uses the four demodulation power type.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a compact mobile and portable radio receiver that demodulates a signal phase-modulated by a digital signal.
The object of the present invention is to provide a demodulation method for reducing weight.

(Means for Solving the Problems) The demodulation method of the present invention includes a means for inputting a signal phase-modulated by a digital signal and converting the amplitude of the phase-modulated signal into a logic level signal, and an input signal. means for sampling and synchronizing a baud timing signal with the logic level signal; means for generating a clock signal having an integer multiple of the center frequency of the phase modulation signal; and means for dividing the clock signal into a plurality of disjoint frequency divisions. means for latching each output signal of said counter with said unsynchronized baud timing signal; and converting said plurality of latched signals into one coded signal. means for delaying the encoded signal by the time of one baud interval; and means for performing a comparison operation between the encoded signal and the delayed encoded signal, and the comparison operation means performs a comparison operation based on the comparison operation. The present invention is characterized in that the phase modulated signal is demodulated by differential detection.

<Function> In the present invention, by using a plurality of counters (Chinese number counters) having mutually prime frequency division periods, a counter whose frequency division number is equivalently the product of the periods of each counter is configured. . The minimum period of this counter is higher than the frequency of the phase modulation signal, so even if a leakage wave is generated from the counter, it will not cause any interference to others. Therefore, strict electromagnetic shielding is unnecessary, and the receiver can be made smaller and lighter.

(Example) Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
This embodiment includes a limiter 1, a synchronization circuit 2, and an oscillator 3.
, a plurality of counters 4 whose frequency division numbers are relatively prime, an encoding circuit 5, a latch 6, a delay 7, and a comparison calculation circuit 8.

π/4 shift as a phase modulated signal which is a received signal) QPS
Assume a K signal. The input phase modulation signal is limiter 1
The amplitude is made constant. On the other hand, the input baud timing signal is sampled in the synchronization circuit 2 at the rise of the phase modulation signal whose amplitude is limited by the limiter 1 and becomes a logic level. As a result, the sampled baud
The rising edge of the timing signal coincides with the zero tarosing of the phase modulation signal. The oscillation frequency of the oscillator 3 is set to an integral multiple (N) of the center frequency of the phase modulation signal.

Further, the periods of the plurality of counters 4 are selected so that the frequency division numbers of each counter are mutually prime, and the periods are selected such that the product of the frequency division numbers of each counter is N. The output of each counter is stored in the latch 6 at the rising edge of the output signal of the synchronization circuit 2. The contents stored in the latch 6 are input to the encoding circuit 5 and converted into one output. The output signal of the encoding circuit 5 is input to the delay 7, and is stored in the delay 7 at the rising edge of the output signal of the synchronization circuit 2.

The output signals of the encoding circuit 5 and the delay 7 are inputted to a comparator circuit 8, and data is detected by a change in phase in one baud interval. If the frequency of the oscillator 3 is set sufficiently higher than the center frequency of the phase modulation signal, the required phase measurement resolution can be obtained.

(Effects of the Invention) As described above, according to the present invention, in a demodulation method that directly digitally demodulates a phase modulation signal, leakage of the phase counter signal into the carrier signal can be prevented. There is no need for strict electromagnetic shielding, which is effective in making the receiver smaller and lighter.

06...Day-5

Claims (1)

[Claims] Means for inputting a signal phase-modulated by a digital signal and converting the amplitude of the phase-modulated signal to a logic level to obtain a logic level signal, and sampling and synchronizing the input baud timing signal with the logic level signal. means for generating a clock signal having an integer multiple of the center frequency of the phase modulation signal; means for frequency-dividing the clock signal by a counter having a plurality of disjoint frequency division numbers; means for latching an output signal with the synchronized baud timing signal; means for converting the latched signals into a coded signal; and delaying the coded signal by the time of one baud interval. and means for performing a comparison operation between the encoded signal and the delayed encoded signal, and the comparison operation means demodulates the phase modulation signal by delayed detection using the comparison operation. method.