JPH0476246B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit, and in particular to a differential amplifier circuit suitable for implementation in a monolithic integrated circuit.

[Conventional technology]

Many differential amplifier circuits suitable for implementation in bipolar or MOS integrated circuits have been known for some time.

Figures 5A and 5B are circuit diagrams of conventional examples of this type of differential amplifier circuit, respectively.
It shows a P-channel FET input type.

The N-channel FET input type differential amplifier circuit (A in the same figure) has power supply terminals 41, 42 and input terminals 51, 5.
2. Output terminal 55, N-channel FETs 61 and 62 forming a differential pair, P-channel FETs 63 and 64 forming a differential amplification stage (active load)
, an N-channel constant current source transistor 65, and a P-channel drive transistor 66 constituting a drive stage.
, an N-channel current transistor 67, a frequency compensation capacitor 70, and a current source 4 constituting a bias circuit.
5 and N channel transistor 68. The P-channel FET input type differential amplifier (FIG. 1B) has the same function as the N-channel FET input type differential amplifier circuit described above, except that the transistors have the opposite polarities.

Input terminals 51 and 52 for N-channel input type A
When the common mode input voltage from the negative side power supply terminal 41 approaches the power supply voltage, the differential pair (N-channel FET transistors 61 and 62) and the current source transistor 65 cannot operate normally at a constant current value.
Therefore, the common mode input voltage is V _D of the current source transistor 65 with respect to the power supply voltage of the negative side power supply terminal 41.
sat (drain-source saturation voltage) and differential pair (N
channel FET transistors 61 and 62)
A potential difference greater than or equal to the sum of V _GS (gate-source voltage) (approximately 1.5 to 2.0 (V)) is required. Even in the case of the P-channel input type, similarly, the common-mode input voltage requires a potential difference of about 1.5 to 2.0 (V) or more as described above with respect to the power supply voltage of the positive power supply terminal 42.

As described above, conventional differential amplifier circuits have limitations on the common-mode input voltage range, which has limited the range of applications.

Figure 6 shows an A/D using the above-mentioned differential amplifier circuit.
An example of a converter (invented by Mr. Gerald B. Boerma of National Semiconductor, USA,
FIG. 2 is a circuit diagram of the circuit disclosed in US Patent No. 4,323,887 filed on April 6, 1982. This A/D converter converts an analog input signal in a voltage range equal to the power supply voltage into a digital value, and its input circuit uses the aforementioned N-channel input type and P-channel input type differential amplifier circuits. .

The reference voltage V _REF at the reference voltage terminal 12 is D/A converted by a D/A converter 14 whose other end is grounded. The output of this D/A converter 14 is input to a P channel input type differential amplifier circuit 23 via a switch 16 which is turned on by a control clock 29 from a clock terminal 22, and is differentially amplified. The analog signal input from the analog input terminal 10 is sent to the inverter 18.
The output of the D/A converter 14 is alternately connected to the N-channel input type differential amplifier circuit 24 via the switch 17 which is turned on by the control clock 29 inverted by
and is differentially amplified. The switch 19, the inverting amplifier 20, and the capacitor 21 constitute a sample data comparator. The output of the P-channel input type differential amplifier circuit 23 or the N-channel input type differential amplifier circuit to the sample data comparator controls the switch 26, the inverter 28, and the switch 27, respectively.
Selected by MSB signal. Note that during MSB comparison, since both differential amplifier circuits 23 and 24 are in the operating range, either output can be used. If the voltage input of the analog input signal is greater than 1/2V _REF , from the second MSB after MSB judgment
During the comparison operation period of A/D conversion up to LSB, N
The output of the channel input type differential amplifier circuit 24 is supplied to the sample data comparator via the switch 28, and if it is smaller than 1/2V _REF , the P channel input type differential amplifier circuit is used when comparing the lower bits after MSB determination. The output of 23 is provided via switch 26 to a sample data comparator. The output of the sample data comparator is led to a successive approximation register 13.
The reference voltage V _REF is successively determined by supplying a voltage corresponding to the weight of each digit to the successive approximation register 13 and comparing the output of the D/A conversion circuit 14 and the analog voltage to be converted from the analog input terminal 10 with a comparator. The switches in the register 13 are sequentially repeated from MSB to LSB, and a converted digital number is obtained by the on/off arrangement of the switches.

In this way, in the conventional D/A converter,
Due to constraints on the input voltage range of the differential amplifier circuit, two types of amplifier circuits are used, one being a P-channel input type and the other being an N-channel input type, which requires extra circuits including control switches, etc. Ta.
Furthermore, for input voltages that require switching of the amplifier circuit after the MSB comparison, the capacitor 21 of the sample data comparator described above does not initially sample accurate analog input information, and the comparison below the second MSB It is also necessary to go through a sampling operation every time it operates. There is a problem in that accurate fluctuating operation cannot be performed when the input value changes with respect to the analog input at one point in time at the beginning of A/D conversion.

[Problem that the invention seeks to solve]

As explained above, in the conventional differential amplifier circuit, there is a restriction that the range of the common mode input voltage in which a desired differential gain can be obtained is narrower than the power supply voltage. Furthermore, the conventional D/
A converters etc. require circuit means for determining the input signal level and means for switching between the first and second differential amplifier circuits, and are capable of continuous amplification of continuously applied input signals and arbitrary This has the disadvantage that it interferes with the amplification of instantaneous input signals at certain times.

SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit that has a desired gain for a common-mode input range up to a power supply voltage range and has a function of continuously amplifying continuous signals.

Another object of the invention is to provide a wide common mode input range.
The object of the present invention is to provide a differential amplifier circuit suitable for implementation with FET or bipolar monolithic integrated circuits.

Another object of the present invention is to provide a differential amplifier circuit suitable for use in an input circuit of an A/D converter that converts an analog input signal in a voltage range equal to the power supply voltage into a digital value.

Still another object of the present invention is to provide a differential amplifier circuit which has a desired gain for a common mode input voltage range exceeding a power supply voltage range and has a continuous increase/decrease function for continuous signals.

[Means for solving problems]

The differential amplifier circuit of the present invention has first and second power supply terminals, first and second input terminals, first and second output terminals, and one end is connected to the first and second power supply terminals. first and second constant current sources connected to each other; a first load circuit connected to the second power supply terminal and the first and second output terminals; and the first and second inputs. a first differential pair connected to the first and second output terminals connected to the terminal and the first load circuit, and biased by the first constant current source; a second differential pair connected to a second input terminal, having two output terminals, and biased by the second constant current source; One output terminal of the dynamic pair is connected to the first power supply terminal, so that one output current of the second differential pair is added to one output current of the first differential pair. a first current mirror circuit connected to the first output terminal, the other output terminal of the second differential pair, and the first power supply terminal, the other output terminal of the second differential pair; a second current mirror circuit configured to add a current to the other output current of the first differential pair; and a gate gate of the first or second output terminal connected to the first differential pair. or a transistor connected to the base, the source or emitter connected to the second power supply, and the drain or collector connected to the second load circuit, and configured to obtain an output from the drain or collector of the transistor. has been done.

The first differential pair operates as a gain stage for input voltages from a level near 1/2 between the first power supply voltage and the second power supply voltage to a level equal to the second power supply voltage. 2 differential pairs have a first power supply voltage and a second
It operates as a gain stage for the input transformer from a level near 1/2 between the power supply voltages to a level equal to the first power supply voltage. Sum of stage gains (approx. 46dB)
is the gain of this differential amplifier circuit, and for other voltage ranges, the gain of one gain stage (approximately 40 dB)
is the gain of this differential amplifier circuit, and as a result, in this differential amplifier circuit, a desired gain can be obtained over the entire range from the first power supply voltage to the second power supply voltage.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a differential amplifier circuit according to the present invention. Differential amplifier circuit 1 of this embodiment
00 is the first power terminal 41, the second power terminal 42, the first input terminal 51, the second input terminal 52, the first output terminal 53, and the second output terminal 54. The first constant current source 105 has one end connected to the first power terminal 41, the second constant current source 106 has one end connected to the second power terminal 42, the second power terminal 42, and the first output. A load circuit 107 connected to the terminal 53 and the second output terminal and the first input terminal 51
conductivity type 3, which is connected to the second input terminal 52, the first output terminal 53, and the second output terminal 54, respectively, and biased by the first constant current source 105.
A first differential pair 1 constituted by a terminal amplification element pair
01, the first input terminal 51 and the second input terminal 52
A second differential amplifier pair 102 is configured of a conductivity type 3-terminal amplifier pair connected to and biased by a second constant current source 106 and has two output terminals.
, the first power supply terminal 41 , the second output terminal 54 , the first power supply mirror circuit 103 connected to one output terminal of the second differential pair 102 , and the first power supply terminal 4 .
1, a first output terminal 53, and a second current mirror circuit 104 connected to the other output terminal of the second differential pair 102.

FIG. 2 shows a differential amplifier circuit 100 of the embodiment shown in FIG.
is constructed from a CMOS monolithic integrated circuit, and a bias/output circuit 90 is connected to this to form an operational amplifier 150.

The first constant current source 105 is composed of an N-channel FET 65 whose source is connected to the first power supply terminal 41 and whose gate is connected to the first bias terminal 56. The second constant current source 106 consists of a P-channel FET 87 whose source is connected to the second power supply terminal 42 and whose gate is connected to the second bias terminal 57. The load circuit 107 has a source connected to the second power supply terminal 42, a drain connected to the first output terminal 53, and a gate and drain connected to each other.
It consists of a channel FET 63 and a P channel FET 64 whose source is connected to the second power supply terminal 42 , whose drain is connected to the second output terminal 54 , and whose gate is connected to the gate of the P channel FET 63 . 1st
The differential pair 101 has a drain connected to the first output terminal 5
3, an N-channel FET 65 whose gate is connected to the first input terminal 51 and whose source is the first constant current source 105.
N channels each connected to the drain of
FET 61 and the drain connected to the second output terminal 54,
N-channel FET 6 whose gate is connected to the second input terminal 52 and whose source is connected to the drain of the N-channel FET 65 of the first constant current source 105.
Consists of 5. The second differential pair 102 has a P-channel FET 87 whose drain is the second constant current source 106.
A P-channel FET 81 whose drain is connected to the first input terminal 51, and a P-channel FET 81 whose drain is connected to the first input terminal 51, and a P-channel FET 81 whose drain is connected to the second constant current source 106.
P-channel FETs connected to the drain of FET 87 and the gate or second input terminal 52, respectively.
Consists of 82. The first current mirror circuit 103 is
The drain is connected to the second output terminal 54, and the source is connected to the first output terminal 54.
N-channel FETs 84 each connected to the power supply terminal 41 of the drain or the second differential pair 102
It consists of an N-channel FET 83 whose drain and gate are connected, with the gate connected to the source of the P-channel FET 81, the gate connected to the gate of the N-channel FET 84, and the source connected to the first power supply terminal 41. The second current mirror circuit 104 has a drain or a P channel FET 8 of the second differential pair 102.
an N-channel FET 85 whose drain is connected to the first output terminal 53 and whose gate is connected to the first output terminal 53;
It consists of an N-channel FET 86 whose gate and source are connected to the first power supply terminal 41, respectively.

The bias/output circuit 90 includes a constant current source 75,
N-channel FETs 92, 93, whose sources are connected to the output terminal 55 and to the first power supply terminal 41, and whose gates are connected to the first bias terminal 56, respectively.
94, whose source is connected to the second power supply terminal 42, whose gate is connected to the second bias terminal 57, and whose drain is connected to the drain of the N-channel FET 94,
A bias P-channel FET 95 whose gate and drain are connected, and whose source is connected to the second power supply terminal 4
2, a P channel whose gate is connected to the second output terminal 54, the drain is connected to the output terminal 55, and the drain of the N channel FET 93, respectively.
It consists of a frequency compensation capacitor 70 connected to the FET 91, the second output terminal 54, and the drain of the P-channel FET 91, and supplies bias voltage to the differential amplifier circuit 100 via the first and second bias terminals 56, 57. do.

Next, the operation of the operational amplifier 150 having the above configuration will be explained.

The first differential pair 101 moves from a level near 1/2 (intermediate) of the power supply voltage between the first and second power supply terminals 41 and 42 to a second power supply voltage (the voltage of the second power supply terminal 42). ), the second differential pair 102 operates as a gain stage for input voltages up to a level equal to
For input voltages ranging from a level near 1/2 (middle) of the voltage between the first and second power supply terminals 41 and 42 to a level equal to the first power supply voltage (voltage of the first power supply terminal 41) Operates as a gain stage. Therefore, for an input voltage at a level near 1/2, the sum of the gains of both gain stages (approximately 46 dB) is the gain of this differential amplifier circuit 100, and for other voltage ranges, the gain of one of the stages is The gain of the stage (approximately 40 dB) becomes the gain of this differential amplifier circuit 100, and as a result, this differential amplifier circuit 100 can obtain the desired gain over the range of the first and second power supply voltages. .

Furthermore, although the drive stage of the bias/output circuit 90 is capable of outputting within the power supply voltage range, when the output approaches the potential of either power supply terminal 41 or 42, the gain decreases.
Approaching 0dB. A gain of about 30dB is usually obtained at the intermediate level.

In the follower connection state where the input and output voltages are equal, the operational amplifier 150 operates in a voltage range equivalent to the first and second power supply voltages for both the input and output voltage ranges, although the gain fluctuates by about 40 to 70 dB.

FIG. 3 shows differential amplifier circuits 23, 24 switches 26, 27 and inverter 28 in the A/D converter shown in FIG.
An application example is shown in which the differential amplifier of the present invention is used instead of the differential amplifier of the present invention. In this circuit, in addition to eliminating the need for switches 26, 28 and gate 27, the use of operational amplifier 150 eliminates the need for switching the amplifier after the MSB comparison. Therefore, the analog input voltage can be held in the capacitor 21 at the beginning of A/D conversion, and while analog input was limited to direct current in the conventional example, the voltage at one point can be accurately determined even for alternating current signals. A great effect can be obtained in that A/D conversion can be performed.

FIG. 4 is a diagram showing another embodiment of the configuration of a differential pair, in which N-channel FETs 161 and 61, 162 and 62 are both Darlington connected, and Darlington transistors 161 and 162 are biased by current source transistors 163 and 164. There is. This configuration is effective when expanding the input range beyond the power supply.

In addition, in the above explanation, P channel FET
Although examples using N-channel FETs and N-channel FETs have been shown, these elements include PNP transistors,
NPN transistors, Jankson FETs, etc. can also be used.

〔Effect of the invention〕

As explained above, the present invention provides a wide range of functions that could not be obtained conventionally by appropriately connecting two types of input differential pairs using opposite conductivity type transistors, a load circuit, and a current mirror circuit. A differential amplifier circuit that operates within the input/output voltage range is obtained.

Furthermore, if the differential amplifier of the present invention is applied to the input circuit of an A/D converter, it becomes possible to sample analog input information at one point in time at the beginning of A/D conversion into the sampling capacity of the sample data comparator. , accurate A/D conversion is possible even for time-varying analog inputs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the differential amplifier circuit according to the present invention, FIG. 2 is a circuit diagram of a specific example of the differential amplifier circuit shown in FIG. Circuit diagram of an embodiment of an A/D converter using an amplifier circuit, No. 4
The figure is a circuit diagram of another embodiment of the differential pair portion of the present invention.
Figure 5A is a circuit diagram of a conventional N-channel FET input type differential amplifier circuit, and Figure 5B is a P-channel circuit diagram.
FIG. 6 is a circuit diagram of a conventional example of an FET input type differential amplifier circuit. FIG. 6 is a circuit diagram of an A/D converter that switches between a conventional N-channel input type and a P-channel input type differential amplifier circuit. 41: first power supply terminal, 42: second power supply terminal, 51: first input terminal, 52: second input terminal, 53: first output terminal, 54: second output terminal, 101: 1st differential pair, 102: 2nd differential pair, 103: 1st current mirror circuit, 104: 2nd current mirror circuit, 105: 1st constant current source,
106: Second constant current source.

Claims (1)

[Claims] 1 first and second power supply terminals, first and second input terminals, first and second output terminals, and a first terminal connected at one end to the first and second power supply terminals, respectively;
a second constant current source; a first load circuit connected to the second power supply terminal and the first and second output terminals; a first and second input terminal and the first load; a first differential pair connected to the first and second output terminals connected to the circuit and biased by the first constant current source; and connected to the first and second input terminals. a second differential pair, having two output terminals and biased by the second constant current source; the second output terminal and one output terminal of the second differential pair; and the first power terminal,
a first current mirror circuit configured to add one output current of the second differential pair to one output current of the first differential pair; The other output terminal of the differential pair is connected to the first power supply terminal, and the other output current of the second differential pair is added to the other output current of the first differential pair. and the first or second output terminal connected to the first differential pair is connected to the gate or base, the source or emitter is connected to a second power supply, and the drain is connected to the second current mirror circuit. Or, by having a transistor whose collector is connected to a second load circuit, and obtaining an output from the drain or collector of the transistor,
A differential amplifier circuit that allows for a wide common-mode input voltage and obtains even greater gain.