JPH0475161A - Signal processor - Google Patents

Abstract

PURPOSE:To give identification numbers to respective neural cell imitation elements fast by giving the identification numbers by receiving identification number giving signals to the cascaded neural cell imitation elements from signal lines by propagation. CONSTITUTION:The respective neural cell imitation elements which constitute a neural cell network have the coupling coefficients of the neural cell imitation elements, or the codes of the coupling coefficients, or identification numbers for inputting other control control information. When the identification are given, the identification number giving signals are propagated to the cascaded neural cell imitation elements and then the identification number signals of the respective neural cell imitation elements are inputted from the signal lines connected to the neural cell imitation elements. Consequently, the operability and speediness at the time of giving the identification numbers are improved greatly and the occupation area of one neural cell imitation element on a substrate, the number of pins, and the number of electric conductors are reduced.

Description

[Detailed Description of the Invention] 1. The present invention relates to a signal processing method and device, and more particularly, to a neural computer imitating a neural network, such as character and figure recognition, motor control of robots, and associative memory. It is suitable for many applications.

By imitating the functions of neurons (neurons), which are the basic unit of information processing in IL-transplanted organisms, and configuring these "neuron mimicking elements" (neuron units) into networks, information can be parallelized. What we aim to do is a so-called neural network. There are many things, such as character recognition, associative memory, and motor control, that are easily accomplished in living organisms, but are difficult to achieve with conventional Neumann-type computers. Attempts to solve these problems by imitating the nervous system of living organisms, especially functions unique to living organisms, such as parallel processing and self-learning, are being actively conducted mainly through computer simulations.

FIG. 10 is a diagram for explaining a conventional neural network model. In the figure, A represents one neuron unit, and FIG. 11 shows it configured into a network. A2 and A3 each represent a neuron unit. One neuron unit is connected to many other neuron units, and processes and outputs signals received from them. In the case of FIG. 11, the network is hierarchical, and neuron unit A2 receives a signal from neuron unit A□ in the previous layer, and neuron unit A3 in the next layer (on the right in the figure) Output to.

First, to explain the neuron unit A shown in Figure 10, the coupling coefficient (T) represents the degree of connection between other neuron units and its own neuron unit. Yes, the first neuron unit and j
In general, the coupling coefficient of the neuron unit Tij
Expressed as There are two types of connections: excitatory connections, in which the larger the signal from the other neuron (the neuron that sends signals to you), the greater your own output; and conversely, the larger the signal from the other neuron, the higher your own output. There is an inhibitory connection where T iJ > O is an excitatory connection, and Tip < O
is an inhibitory bond. Now, suppose that your unit is the j-th neuron unit, and the output of the first neuron unit is yL.

Ti and yl obtained by multiplying this by the coupling coefficient TLj become inputs to its own unit. As mentioned above, since each neuron unit is connected to a large number of neuron units, T1. The sum of yL,
That is, ΣT,,y, becomes the input to its own unit. This is called the internal potential and is represented by U.

uj=ΣTtjyt (1)
Next, this input is subjected to nonlinear processing and is used as the output of that neuron unit. The nonlinear function used here is called a neuron response function, and the following equation (2) and a sigmoid function f (x) as shown in FIG. 12 are used.

f (x)=1/ (1+e−X)
(2) FIG. 12 is a diagram showing this sigmoid function.

The above neuron units are configured into a network as shown in FIG. 11, and each coupling coefficient T4. Given, equation (1)
, (2) one after another enables parallel processing of information and obtains the final output.

FIG. 13 is a diagram showing an example of the above network realized by an electric circuit (Japanese Unexamined Patent Publication No. 62-295188), which basically includes a plurality of amplifiers 33 having an S-shaped transfer function, and each amplifier 33. A resistive feedback network 31 is provided which connects the output of the amplifier to the input of the amplifier in the other layer as shown by the dashed line. A CR time constant circuit 32 including a grounded capacitor C and a grounded resistor R is individually connected to the input side of each amplifier 33. and,
Input current 0. I2 to ■ are supplied to the inputs of each amplifier 33, and the output is obtained from the set of output voltages of these amplifiers 33.

Here, the strength of the input and output signals is expressed as a voltage, and the strength of the connection between neurons is expressed as the resistance value of the resistor 30 (lattice point in the resistive feedback network 31) that connects the input and output lines between each cell. The nerve cell response function is represented by the transfer function of each amplifier 33. Further, as mentioned above, the connections between neurons have excitatory and inhibitory properties, which are mathematically expressed by the positive and negative signs of the coupling coefficient. However, since it is difficult to realize positive and negative values using constants on the circuit, here, the amplifier 33
This is achieved by dividing the output into two and inverting one output to generate two positive and negative signals, and selecting these appropriately. Furthermore, an amplifier is used as an equivalent to the sigmoid function shown in FIG.

Next, the learning function of the network will be explained. As a learning law used in numerical calculations.

There is something called pack propagation.

First, the coupling coefficient between each neuron unit is initially set to a random value. If input is given to the network in this state, the output result will not necessarily be desirable. For example, in the case of single character recognition, if you give the handwritten character "1", the output result will be "This character is "1".
Although it is desirable to obtain a result in which the coupling coefficient is random, this is not necessarily a desirable result.

Therefore, the correct answer (teacher signal) is given to this network so that when the same input is received again, the output result will be the correct answer (desired output result will be obtained).

Vary each coupling coefficient. At this time, the algorithm for determining the amount by which the coupling coefficient is changed is called pack propagation. for example.

In the hierarchical network shown in Figure 11, let y be the output of the j-th neuron unit in the final layer (layer A3 on the right in the figure), and let d be the teacher signal for that neuron unit. , E=Σ(d,+yp)2
8T1. so that E expressed in (3) is minimized. =aElaTtj (4)
The coupling coefficient T4. change. Specific [ha,
First, the output layer and the layer before it.

δb= (d'a-y, +)Xf'(u,)
(5) (output layer A3), and the layer further before that (middle layer) is δ4=Σ
δtTtxXf'(u~) (Intermediate layer A2 in the layer before A3) (6) However, f'' is the first-order differential of f. Using this, calculate δ (error signal).

ΔT4. =η(δLyL)+αΔTLjTtp=Tt,
Find i' + T, b (7) and T'
Change tp. However, each of ΔTi3Tij' is a value at the time of previous learning. Further, η is called a learning constant, and α is called a stabilization constant, and since they cannot be determined theoretically, they are determined empirically. -For boat fishing, the smaller these numbers are, the slower the convergence is, and the larger these numbers are, the more likely they are to oscillate. In terms of order, it is about 1.

It learns in this way, then gives input again, calculates the output, and learns. By repeating this operation many times, a coupling coefficient TiJ is eventually determined that will yield a desired result for a given amount of human effort.

Now, if one were to try to implement such a learning method into hardware, it would be difficult to implement because the learning would require a large amount of four arithmetic operations. The learning method itself is also unsuitable for hardware implementation.

14 to 16 are diagrams showing examples of realizing such a neural network using digital circuits. FIG. 14 is a diagram showing an example of a circuit configuration of a single neuron, 40 is a synaptic circuit, 41 indicates a dendritic circuit, and 42 indicates a cell body circuit. FIG. 15 is a diagram showing an example of the configuration of the synapse circuit 40 shown in FIG. 14, in which the value obtained by multiplying the input pulse f by a multiplication factor a (a multiplication factor of 1 or 2 for the feedback signal) is obtained through the coefficient circuit 40a. Input rate multiplier 4
A synapse weight register 40c storing a weighting value W is connected to the rate multiplier 40b. FIG. 16 is a diagram showing an example of the configuration of the cell body circuit 42, in which a control circuit 43, an up/down counter 44, a rate multiplier 45, and a gate 46 are connected in order, and an up/down memory 47 is connected in this order. It is provided. This expresses the input/output signals of a neuron unit as a pulse train, and the amount of the signal is expressed as the pulse density. The coupling coefficient is handled as a binary number and stored in the memory 47. Signal calculation processing is performed as follows. first,
By inputting the input signal to the clock of rate multiplier 45 and inputting the coupling coefficient to the rate value, the pulse density of the input signal is reduced in accordance with the rate value. This is Tt in the equation of the pack propagation model mentioned above.
This corresponds to the part p3't. Also ΣT,,'3/L's Σ
This part is realized by an OR circuit shown by the dendrite mouth W&41. Since the connections have excitatory and inhibitory properties, they are divided into groups in advance and OR'd for each group. In Figure 14, F is excitatory;
F2 indicates inhibitory output. An output is obtained by inputting these two outputs to the up side and down side of the counter 44 shown in FIG. 16, respectively, and counting them. Since this output is a binary number, the rate multiplier 45 is used again to convert it into a pulse density. By constructing a network using multiple neuron units,
Neural networks can be realized.

The learning function inputs the final output of the network to an external computer and performs numerical calculations inside the computer.
This is achieved by writing the results into the coupling coefficient memory.

Furthermore, a signal processing device using a neuron network composed of neuron mimicking elements has been previously proposed, but the coupling coefficient of each neuronal mimicking element, the sign of the coupling coefficient,
Nor is there any mention of other means and methods for providing control information.

Purpose The present invention was made in view of the above-mentioned circumstances.
In assigning an identification number to each neuron mimicking element, which is necessary when assigning a coupling coefficient, a sign of the coupling coefficient, or other control information to each neuronal mimicking element constituting a neuronal network, its operability, Significantly improve speed,
We solved the problems of operability and high speed by manually setting switches and assigning identification numbers to each neuron mimicking element as in the past. When fabricating a chip in order to reduce size, cost, and create a large network, the area occupied by a single neuron-mimetic element on a substrate can be reduced by incorporating a switch function for providing an identification number into the chip. The purpose of this invention is to provide a signal processing device that reduces the number of pins and the number of wires.

In order to achieve the above-mentioned object, the present invention provides (1) a signal processing device using a neuron network composed of neuron mimicking elements, in which each neuron mimicking element constituting the neuronal network; has an identification number for capturing the coupling coefficient of the neuron mimicking element, the sign of the coupling coefficient, or other control information, and the identification number is assigned to each neuron mimicking element connected in a cascade. (2) By propagating the identification number assignment signal to the neuron mimicking element, the identification number signal of each neuron mimicking element is sequentially taken in from the signal line connected to the neuron mimicking element; In a signal processing device using a cell network, each neuron mimicking element constituting the neuron network has control information as the neuron mimicking element, and the control information is applied to each neuron mimicking element connected in a cascade. The present invention is characterized in that the control information of each neuron mimicking element is sequentially taken in from the signal line connected to the neuron mimicking element by propagating a control information imparting signal to the neuron mimicking element.

Hereinafter, the present invention will be explained based on examples.

Each neuron imitation element constituting the neuron network is realized by an analog circuit or a digital circuit. The present invention is effective when a neuron mimicking element is held as a digital signal. Therefore, even if the neuron mimicking element is processed using an analog signal as well as a digital circuit, the identification number may be held as a digital signal. Digital
It can also be applied when analog is mixed.

Here, as an example of the neural network targeted by the present invention,
Signal processing by a neuron unit using a digital logic circuit and a network circuit configured using the neuron unit will be explained.

First, the basic idea of the present invention is as follows: (1) The input/output signals, intermediate signals, coupling coefficients, teacher signals, etc. related to the neuron unit are all expressed as a pulse train expressed by a binary value of 0.1.

■The value of a signal inside the network is expressed by pulse density (the number of "1"s within a certain period of time).

■Calculations within the neuron unit are performed by logical operations between pulse trains.

■The pulse train of the coupling coefficient is stored in the memory within the neuron unit.

■Learning is achieved by rewriting this pulse train.

- Regarding learning, calculate the error based on the given teacher signal pulse train, and change the coupling coefficient based on the equation. At this time, calculation of errors and calculation of changes in coupling coefficients are all performed by logical operations on the Oll pulse train.

This will be described in detail below based on examples.

FIG. 1 is a diagram showing a signal calculation part, that is, a part corresponding to one neuron imitation circuit (unit), and the network configuration uses the same hierarchical structure as the conventional one as shown in FIG. 11. All inputs and outputs of the neuron unit are “0”.
”, rlJ4: Binarized and further synchronized data is used. The value (=intensity) of the signal of input j is expressed by the pulse density, and is expressed by the number of "1" states within a certain fixed time, for example, as in the pulse train shown below.

Input signal = 4.76 (8) Synchronization signal 11-11-1" - This shows a signal representing 4/6, and the human input signal has 4 "1"s out of 6 synchronization pulses, rQJ or 2 It means that it is an individual. At this time, it is desirable that the arrangement of "1" and "0" is random, as will be described later.

On the other hand, the coupling coefficient Tl is similarly expressed in terms of pulse density, and is expressed as "
0" and "1" pulse trains are prepared in the summary memory.

Coupling coefficient = 3/6 (9) Synchronization signal t"-upper"-upper"-This represents that the value of the coupling coefficient is rlo1010]=3/6, and in this case, as above, rQJ and rl
It is preferable that the J's are arranged randomly. Then, the bit string of this coupling coefficient is sequentially read out from the memory according to the synchronized clock, and as shown in FIG.
nTtJ).

This is input to neuron unit j. To explain using the above example, when the signal rlo1101J is input, the bit string of the coupling coefficient is read from the memory in synchronization with this, and AND is performed sequentially.

Input signal = 4/6 Coupling coefficient = 3/6yznTtJ
==2/6 A pulse train (bit train) rlo10σ0 as shown in (10) is obtained, which means that the input signal pulse train yi is the pulse train T of the coupling coefficient,
As a result, the input pulse density to the neuron unit becomes 2/6. This AN
The output pulse density of the D circuit is approximately the product of the "input signal pulse density" and the "coupling coefficient pulse density",
It has the same function as the coupling coefficient in the analog system. The longer the signal train (pulse train) is, and the more randomly the 1's and 0's are arranged, the closer the function will be to the product of numerical values.

Non-random means that 1's (or 0's) are clustered (close together).

Note that if the length of the pulse train of the coupling coefficient is shorter than the input pulse train and there is no more data to be read, this can be handled by returning to the beginning of the data and repeating the read.

Since one neuron unit has many inputs, there are many "ANDs of input signals and coupling coefficients" as described above. Next, these OR circuits calculate the logical sum of these. Since the inputs are synchronized, the first data is rl
olooOJ, and if the second data is rolooooj, the OR of both becomes rlllooOJ. If this is calculated simultaneously with multiple inputs and the output is output, the result will be as follows.

t n T t, L''-11- y in T t, -ri1111-u ()' t
n TLJ) (11) This part corresponds to the calculation for calculating the sum of signals and the nonlinear function (sigmoid function) part in analog calculation. - In a simple pulse calculation, if the pulse density is low, the ORed pulse density approximately matches the sum of the respective pulse densities. As the pulse density increases, the output of the OR circuit gradually becomes saturated, so the result does not match the sum of the pulse densities and nonlinearity occurs. In the case of OR, the pulse density is neither greater than 1 nor less than 0, and is a monotonically increasing function, so it is approximately the same as a sigmoid function.

Now, coupling has excitatory and inhibitory properties, and in the case of numerical calculations, it is expressed by the sign of the coupling coefficient, and in the case of analog circuits, as mentioned above, when the coupling coefficient TLJ is negative (inhibitory For coupling), an amplifier is used to invert the output, and TL4
It is connected to other neuron units with a resistance value corresponding to . In this regard, in the case of the digital method, first
Depending on the positive/negative LJ, each connection is divided into excitatory and inhibitory connections.
Then, the OR of the ANDJ of the input signal and the pulse train of the coupling coefficient is calculated for each group. As a result, the output of the excitatory group is "1" and the output of the inhibitory group is " Outputs 1 only when the value is 0. In order to realize this function, it is sufficient to AND the output of the inhibitory group and the output of the excitatory group. That is, the output of the excitatory group 'F'-□
- □Top" - Output of inhibitory group - L - Kazuichi Kita" - Output of neuron unit (12) Expressed as a logical formula, a=U(ytnTta) (T=excitatory) (1
3) b:U(ytnT'ca) (T=inhibitory)
(14) y, = anb
It is expressed as (15).

The configuration of a network using this neuron unit is
A hierarchical type similar to pack propagation as shown in FIG. 11 is used. If the entire network is synchronized, each layer can perform calculations in parallel using the functions described above.

Next, processing during learning will be explained.

By determining the error signal using the following ■ or ■, and then changing the value of the coupling coefficient using the method described in ■,
Learn.

(2) Error signal in the final layer First, the error signal in each neuron is calculated in the final layer (layer A3 on the right side of FIG. 11), and the coupling coefficient related to that neuron is changed based on it. A method of calculating an error signal for this purpose will be explained. In the present invention, the error signal is defined as follows. In other words, when an error is expressed numerically, it can generally take both positive and negative values, but since such an expression is not possible with pulse density, it can be expressed as a signal representing the ten commandments.
- Express the error signal using two signals representing the components.

Output signal y (16) Teacher signal d (17) Error signal pulse L-[-1 (δ+= (y AND d)
(18) Error signal - one - L--- (δ-E (y AND d)
(19) That is, the ten commandments of the error signal are '1' when the output result is "0" and the teacher signal is it I 11, and otherwise J(O17).

On the other hand, one component of the error signal has an output result of (# l 97
When the teacher signal is 0'', it becomes '1'', and otherwise it is '1''.
0''.Based on such an error signal pulse, the coupling coefficient is changed as described later.

(2) Error signal in intermediate layer Furthermore, the error signal is back-propagated, changing not only the coupling coefficient between the final layer and the layer immediately before it, but also the coupling coefficient of the layer before it. Therefore, the middle layer (center layer A in Figure 11)
It is necessary to calculate the error signal at each neuron in 2). In the same way as propagating a signal from a neuron in the middle layer to each neuron in the next layer, we collect the error signals in each neuron in the next layer and calculate the own error. Signal. This can be done in the same manner as calculation equations (7) to (10) within the neuron unit. That is, first, the connections are divided into two groups depending on whether they are excitatory or inhibitory, and the multiplication part is expressed by AND, and the Σ part is expressed by OR.

However, the difference from equations (7) to (fl) within a neuron unit is that y is one signal, whereas δ has two signals representing positive and negative, and both signals need to be considered.

Therefore, it is necessary to differentiate into four cases: positive and negative of T (coupling coefficient) and positive and negative of δ (error signal).

First, the case of excitatory connections will be explained. For a neuron unit with an intermediate layer, the difference between the error signal in the neuron unit in the next layer (the final layer in Figure 11) and that neuron unit and itself (the neuron with an intermediate layer in Figure 11) (δ+1nTia) is calculated for each neuron unit in the next layer, and then the OR of these is calculated (=U
(δ+inr+,)). The result is defined as the error signal + for this layer. That is, it is expressed as follows.

δ+t n T t. l−-[δ+t n T
L r -LL-knee δ+, "earth" - [-Yul (20) Similarly, AND the error signal - in the neuron unit of the next layer with the coupling coefficient,
Furthermore, by ORing these values, it is possible to similarly obtain the error signal - of this layer.

δ−t n T. , -ri1 δ-J n T t s 1-1-''-s-, (21
) Next, the case of inhibitory binding will be explained. The error signal from the neuron unit in the next layer ahead is ANDed with the coupling coefficient between that neuron unit and itself, and the result of ORing these together is set as the error signal for this layer. . Namely.

δ-+nTtp ■-"-1 δ-t n T L'J"-1-δ+,
(22) Similarly, by ANDing the error signal in the neuron unit of the next layer with the coupling coefficient, and then ORing these, the error signal of this layer is similarly determined. I can do it.

δ+LnT, 4--"Nee- δ+ 4 nT I J L-1-1-The connections from one neuron unit to another neuron unit are excitatory and inhibitory. 2
Therefore, the error signal δ+ obtained by equation (20) and the equation (
22) is ORed with the error signal δ+ obtained in step 22), and set it as the error signal δ+ of Nealon in the own neuron unit. Similarly, the error signal δ− obtained by equation (21) and equation (23
) is ORed with the error signal δ- obtained in ), and this is set as the error signal δ- of Neelon) in the own neuron unit.

To summarize the above.

δ+, = (U(δ+, nTt*)) u(u(δ−, n”
r, )) iE excitatory iE inhibitory δ, =, (u(δ-tnTtj)) u(u(δ+, nT
t+)) iC excitatory iE inhibitory In addition, a function corresponding to the learning rate may be provided.

When the rate is less than 1 in numerical calculations, the learning ability further increases. This can be achieved by thinning out the pulse train in the pulse train calculation. This is a counter-like way of thinking,
The following examples 1) and 2) were used. For example, η=
At 0.5, every other pulse train of the original signal is thinned out. Even if the pulses of the original signal are not equally spaced, a method is used in which every other pulse is thinned out for a single pulse train (the method of <(Example 2)>).

(Example 1) (Example 2) ■Change each coupling coefficient from the error signal Next, using the error signal obtained by the above ■ or ■,
A method of changing each coupling coefficient will be explained.

The line to which the coupling coefficient you want to change belongs (see Figure 11)
A'ND of the signal propagating (=input signal to the neuron unit) and the error signal is taken (δny). However, here, since there are two error signals, 0 and 10, each is calculated and determined.

δ+ny →ΔT+
By thinning out such error signals, a learning rate function is provided.

δ−ny →ΔT
- Let the two signals obtained in this way be ΔT.

A new coupling coefficient T is determined based on these, but since the value of T is an absolute value component, cases are differentiated depending on whether the original T is excitatory or inhibitory.

First, in the case of excitability, the ΔT+ component is increased and the ΔT− component is decreased relative to the original T. In other words, T (28) after learning. Next, in the case of suppression, the Δτ+ component is decreased and the ΔT− component is increased with respect to the original T.

That is, T after learning becomes.

The entire network is calculated based on the above learning side.

Next, an actual circuit configuration based on the above algorithm will be explained with reference to FIGS. 2 to 4. The configuration of the neural network is the same as that shown in FIG. Figure 2 shows the line (
FIG. 3 is a diagram showing a circuit of a portion corresponding to the circle (neuron unit A) in FIG. 11. FIG. Further, FIG. 4 is a diagram showing a circuit for calculating an error signal in the final layer from the output of the final layer and the teacher signal. By forming these three circuits into a network as shown in FIG. 11, a digital neural network circuit capable of self-learning can be realized.

First, FIG. 2 will be explained. 1 is an input signal to the neuron unit and corresponds to equation (8). The coupling coefficient of equation (9) is stored in the shift register 8. Terminal 8A is a data output port, and terminal 8B is a data input port. If this has the same function as a shift register,
Others 1 For example, a RAM+address controller or the like may be used. Circuit 9 is a circuit corresponding to equation (10), and performs an AND operation between the input signal and the coupling coefficient.

These outputs must be divided into groups depending on whether the connections are excitatory or inhibitory, but it is more versatile if you prepare outputs 4 and 5 for each group in advance and switch which group they are sent to. expensive. For this reason, a bit indicating whether the connection is excitatory or inhibitory is stored in the memory 14, and this information is used to switch the gate circuit 1.
3 switches the signal. Further, as shown in FIG. 3, a gate circuit 15 having a plurality of OR gate configurations corresponding to equation (11) for processing each input is provided. Furthermore, as shown in the figure, the excitability group expressed by equation (12) is "1".
” and the inhibitory group is rQJ, the gate circuit 16 includes an AND gate and an inverter that outputs an output only when the inhibitory group is rQJ.
is provided.

Next, the error signal will be explained. FIG. 4 is a diagram showing a circuit that generates an error signal in the final layer, and is a logic circuit that is a combination of AND and an inverter, and is expressed by equations (16) to
This corresponds to (19). That is, the output 19 from the final layer
and error signals 21 and 22 are generated from the teacher signal 20.

Also, equations (20) to (20) for calculating the error signal in the intermediate layer are
23) is performed by the gate circuit 10 having an AND gate configuration shown in FIG. 2, and outputs 2 and 3 corresponding to 10 and - are obtained. In this way, the error signal used differs depending on whether the connection is excitatory or inhibitory, so it is necessary to differentiate between each case. In this case, the information stored in the memory 14 as to whether the connection is excitatory or inhibitory is used. + of the error signal.

- It is performed by the gate circuit 12 having an AND and OR gate configuration in accordance with the signals 6 and 7. Further, the arithmetic expression (24) for collecting error signals is performed by a gate circuit 17 having an OR gate configuration shown in FIG. Also, the formula corresponding to the learning rate (
25) is performed by the frequency dividing circuit 18 shown in FIG.

Finally, the part for calculating new coupling coefficients from the error signal will be explained. This is expressed by equations (26) to (29), and is performed by the gate circuit 11 having the AND, inverter, and OR gate configurations shown in FIG. This gate circuit 11
Since the cases must be classified according to the excitatory/inhibitory nature of the connections, this is done by the gate 12 shown in FIG.

Next, an embodiment of the signal processing device according to the present invention will be described.

In order to execute the processing using the neuron network as described above, each neuron mimicking element must be equipped with a neuron (neuron).
It is necessary to store the coupling coefficient Ti4 and the sign of the coupling coefficient.

An identification number unique to each neuron is given to each neuron constituting the network as shown in FIG. The operation of giving the coupling coefficient and the sign of the coupling coefficient is performed.

FIG. 5 shows a method of assigning an identification number to one neuron (A2 in FIG. 11), a coupling coefficient, and a code of the coupling coefficient. In the figure, 23 is a neuron imitation circuit corresponding to FIG. 2, 24a is a switch, 24b is a comparator, and 25° and 26 are regions. Therefore, 23
corresponds to a portion of the circuit (Fig. 2) corresponding to the line (connection) in Fig. 11. The coupling coefficient is stored, for example, in the shift register 8 in FIG. 2, and the code of the coupling coefficient is stored in the register 14 in FIG. 24a in FIG. 5 is a switch for giving the identification number of the neuron, and it can be manually turned on and off.
By turning N and OFF, "1" and "O" are given.

The bit width of this switch needs to be increased as the number of neurons increases. For example, if the bit width of the switch is 8 bits, up to 256 (=2") neurons can be identified.

We will actually describe the coupling coefficient and the method of assigning the sign to the coupling coefficient.

The neuron identification number is set using the switch 24a in FIG. This must be a unique value for each neuron in the network of FIG. Next, a controller (not shown) that controls the entire network outputs the identification number of each neuron to the address bus of each neuron. Then, in order to determine whether the address currently being output is for the own neuron, the comparator 24b compares the identification number roughly given by the switch 24a with the address bus value, and determines whether the values are the same. In other words, when its own neuron is selected, a selection signal is output to the circuit 23. In this state, when a pulse is sent to the clock signal, only the selected neuron stores each coupling coefficient and the sign of the coupling coefficient from the data bus in a register in the circuit 23 that stores the coupling coefficient and the sign of the coupling coefficient.

By performing the above operations on all the neurons in the network shown in FIG. 11, the assignment of coupling coefficients and the signs of the coupling coefficients is completed.

However, in the above conventional method, the identification number must be manually given using a switch added to each neuron, and the more neurons there are, the more time it takes, and the more difficult it is to change the identification number. There were problems with operability and high speed.

Furthermore, when converting the circuit shown in FIG. 5 into a chip, if 25 areas are incorporated into the chip, the number of terminals on the chip will be relatively reduced, but it is necessary to place the switch 24a and the comparator 24b for each neuron outside the chip. This increases the number of parts and makes it difficult to achieve miniaturization, which is the goal of chipping, in other words, to reduce the area occupied by one neuron on the boat. Furthermore, when the area 26 in FIG. 5 is taken into the chip, the comparator 24b is inside the chip, so
Although the number of parts is reduced, there is still a switch 2 outside the chip.
4a, and furthermore, the number of terminals for receiving and receiving the identification number from the switch increases. Therefore, the number of wires on the board increases, and the area occupied on the board does not become very small.

The present invention takes the above problems into consideration, and improves operability and speed in assigning identification numbers to each neuron, and further reduces the area occupied by a single neuron on a board when it is made into a chip. , which is designed to be smaller.

FIG. 6 shows a method of assigning an identification number to each neuron, a coupling coefficient, and a code of the coupling coefficient in the present invention. In the figure, 27 is a register, 28a is a flip-flop, and 28 is a control circuit. The difference from the example shown in FIG. 5 is that the identification number of each neuron is taken into the register 27. The addition of a circuit 28 allows the identification number to be easily assigned from the controller that controls the entire network.

Therefore, in FIG. 6, a method of assigning identification numbers to neurons will be described.

In FIG. 6, a neuron identification number is stored in a register 27, and a circuit 28 controls the storage in this register. 28a is a flip-flop that takes in an input signal at the rising edge of CK and outputs it from Q. A timing chart at this time is shown in FIG.

To store the neuron identification number in the register 27,
First, the load signal LDI is set to rQJ at the rising edge Ll of the load pulse LDP. As a result, LDCK, which is a signal taken into the register 27 from tl, becomes "0" and becomes "1" at the rising edge t2 of the next load pulse LDP. Since the register 27 captures the input data DI at the rising edge of the capture signal LDCK, when the identification number to be stored is output to the address bus at the rising edge t2 of LDCK, this identification number is captured into the register. This means that the desired identification number is stored in this neuron.

The output LDO of the circuit 28 is now connected to the load signal LDI of the next neuron. The situation at this time is shown in FIG. As shown in the figure, it can be seen that the load signal to the register is cascaded to each neuron in the network. In the figure, numeral 29 is a circuit for processing the connection input to one neuron A2 in FIG. 11, and corresponds to that in FIG. In FIG. 8, the timing chart when each neuron 29 is given an identification number is shown in FIG.
As shown in the figure. The timing of assigning an identification number to one neuron is as shown in FIG.

FIG. 9 shows how identification numbers are given to each neuron in the network, and here shows the timing at which identification numbers are given to three (1) neurons N1, N2, and N3. Masu Roto Pulse L
At the rising edge of DP (10), the load signal LDI is set to "0". As a result, as described in Fig. 7, the neuron N
1, the input signal LDCK to the register becomes "Oj" during the period from t○ to t1, and at the rising edge tl of this signal, the identification number on the address bus, that is, the neuron, reads (N
l) is taken up into neurons. Then, the load signal ratio LDO becomes "
0'', which is then input to the load signal LDI of the neuron N2 connected in cascade. As shown in FIG. 9, the load signal propagates through each neuron connected in a cascade, and at one time t2, the load signal is transmitted to neuron N2.

At time t3, neuron N3 takes in each identification number. Therefore, by simply connecting a single control line in cascade to each neuron in the network, the controller controlling the network or the host processor can easily assign an identification number to each neuron. This greatly improves operability and speed. In addition, when converting into a chip, the entire neuron shown in Figure 8 can be incorporated into the chip, which reduces the area occupied by each neuron on the board, resulting in a smaller size and larger network.

And cost reduction becomes possible.

Note that in the above example, a case has been described in which an identification number is given to each neuron, but instead of the identification number, control information for each neuron may be given. Further, both the identification number and the control information may be given in the same way.

Wheat - one rice As is clear from the above explanation, the present invention has the following effects.

(1) Effect corresponding to claim 1: Since a method for assigning an identification number to a neuron mimicking element is presented by a relatively simple means, an identification number to a neuron mimicking element can be assigned easily and at high speed. .

In addition, when converting to LSI, not only are there fewer external components, but the area occupied on the board and the number of wires can be reduced, making it possible to implement high-density packaging, resulting in larger networks, smaller size, and lower costs. can be converted into

(2) Effect corresponding to claim 2: Since a method for storing control information in a neuron imitation element using relatively simple means is presented, control information of a neuron imitation element can be stored easily and at high speed. can.

In addition, since the neuron-mimetic element can relatively easily have control information, the number of control lines directly applied to the neuron-mimetic element from the outside can be reduced, which reduces the area occupied on the board and the wiring. The number is reduced, high-density packaging is possible, and larger networks, smaller size, and lower costs are possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one of the neural circuit units. Figures 2 to 4 are diagrams showing examples of circuit configurations of each part;
6 and 6 are diagrams for explaining a method of assigning an identification number to one neuron, a coupling coefficient, and a method of assigning a code to the coupling coefficient, and FIG. 7 is a diagram showing a timing chart in FIG. 6, FIG. 8 is a diagram for explaining the method of assigning identification numbers to each neuron, FIG. 9 is a diagram showing a timing chart in FIG. 8, and FIGS. 10 to 12 are diagrams showing the operation of the neural circuit unit. A diagram to explain the principle,
FIG. 13 to FIG. 16 are diagrams showing examples of conventional circuit configurations. 1...Input signal, 2, 3, 6.7...Error signal, 4
... Excitatory signal, ... Inhibitory signal, 8... Shift register, 9, 10, 11, 12.13... Gate circuit, 1441. Memory, 23...neuronal mimicry circuit, 2
4a...Switch, 24b...Comparator. Patent Applicant Rico Co., Ltd.

Claims (1)

[Scope of Claims] 1. In a signal processing device using a neuron network composed of neuron mimicking elements, each neuron mimicking element constituting the neuron mimicking element has a coupling coefficient of the neuron mimicking element, Alternatively, it has an identification number for capturing the code of the coupling coefficient or other control information, and the identification number is sequentially assigned by propagating an identification number assignment signal to each neuron mimicking element connected in a cascade. , A signal processing device characterized in that an identification number signal of each neuron imitation element is taken in from a signal line connected to the neuron imitation element. 2. In a signal processing device using a neuron network composed of neuron mimicking elements, each neuron mimicking element constituting the neuron mimicking element has control information as the neuron mimicking element, and the neuron mimicking element has control information as the neuron mimicking element. The provision of information is carried out by propagating a control information provision signal to each neuron mimicking element connected in a cascade, and sequentially taking in the control information of each neuron mimicking element from a signal line connected to the neuron mimicking element. A signal processing device characterized by: