JPH0474431A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the deterioration, near a gate oxide film, which is caused by an electric charge at an interconnection formation process by a method wherein a second metal conductor film is connected at an opening part in a first insulating film having a desired pattern and in a third insulating film. CONSTITUTION:A first metal interconnection 2 is formed on a substrate 1 in which a semiconductor element has been formed. A thermal-reaction oxide film 3 is deposited and formed. p-SiN 4 is grown. The p-SiN 4 is filled into a region, in which the first metal interconnection 2 does not exist, so as to be flattened by an etching-back operation by using an RIE apparatus. A lower interconnection and an upper interconnection which are used to form a multilayer interconnection are insulated; an interlayer insulating film 6 used to reduce a capacity is formed. The insulating film 6 is etched down to a halfway part by using an RIE apparatus by making use of a mask 7; in succession, the residual film is etched by making use of the mask by using an etching apparatus using radicals, e.g. a CVD apparatus or a downstream etcher. A second metal interconnection 8 is grown and patterned. The same process is repeated to form a second interlayer film and a third metal interconnection.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device, particularly a structure of a semiconductor integrated circuit device having a highly integrated, multilayer metal wiring structure, and a method for manufacturing the same.

Prior Art Semiconductor devices, particularly complementary metal oxide semiconductor (CMO)
8) Since devices are easy to integrate, element dimensions are becoming increasingly finer and the degree of integration is increasing. For example, currently, the minimum wiring width is 0.8 μm.
Megabit Dynamic Random Access Memory (DR)
AM) has more than + million transistors integrated. In logic circuit elements, the minimum wiring width is 1.0ν
A microprocessing unit (MPU) in which 600,000 to 1,000,000 transistors are integrated has been developed.

With such high integration, the total wiring length connecting each element becomes longer and the area required for wiring increases, so it is necessary to narrow the wiring width or make the wiring multilayered. This is becoming more and more common. The wiring width is approximately 1.
2 to 1.5 uI11, and 4-layer wiring has already been put into practical use (for example, Nikkei Microdevice June 1989 issue, pages 42 to 49).

The wiring material is mainly aluminum (A1) to which silicon (Si), copper (Cu), titanium (Ti), etc. are added. Since the melting point of AI is relatively low at about 550°C, wiring using AI is performed at a temperature of 450°C or lower. For example, AI film is formed by sputtering method,
The insulating film is formed using plasma chemical vapor deposition (plasma CVD) or atmospheric pressure CVD at approximately 400 to 450°C.
Formed at temperatures within the range of

FIG. 6 is a diagram showing a conventional wiring process.

In FIG. 6, in order from the one closest to the substrate, the first metal wiring,
They are called second metal wiring and third metal wiring. In Figure 6(a),
A state in which a pattern of first metal wiring 2 is formed on a substrate on which semiconductor elements have already been formed is shown. Figure 6(b)
Now, plasma silicon nitride (p-SiN) 4
is grown to 2um from 500rv. Figure 6 (C)
Then, p-8i was etched back using RIE equipment.
A state in which N4 is buried in a region where there is no first metal wiring 2 and flattened is shown. In some cases, the remaining grooves are filled with spin-on glass (SOG) after such etch-back. A silicon oxide film may be used instead of a silicon nitride film. 5 is embedded p-8
It is iN. FIG. 6 (+1) shows a state in which various insulating films 6 have been subsequently grown.

What is shown in FIG. 6(e) is the step of forming a via hole, in which reactive ion etching (R) is performed using a mask 7.
This is a state in which the insulating film 6 has been etched using an IE) device.

FIG. 6(f) shows a state in which the second metal wiring 8 has been grown and patterned.

A conventional wiring method will be described with reference to FIG.

The first metal wiring taken out from the gate 9 is connected to the next transistor, and the length of the wiring becomes 1001 or more.

Problems to be Solved by the Invention The following problems arise because the wiring process is different from the semiconductor element forming process and must be processed at a low temperature of about 450°C.

The first is sputtering, plasma CVD, etc.
This problem arises from the frequent use of processes in which the semiconductor substrate is exposed to plasma.

For example, most of the processes such as thin film growth, planarization, and wiring metal growth use plasma, and although there are some processes that use plasma before the wiring process (for example, gate electrode processing using RIE), there are many thermal reaction, thermal diffusion,
The ratio of using plasma is low. When exposed to plasma, charges are generated in each region of the substrate, leading to deterioration of device characteristics.

Second, the damage caused in this way cannot be fully recovered.

High temperature treatment is necessary for sufficient recovery, but A
The limit is about 500°C, which is close to the melting point of I, and heat treatment at higher temperatures cannot be carried out because AI will melt.

Thirdly, since the formation of the element has already been completed at the time of the wiring process, current is likely to be generated due to the voltage difference due to the PN junction in each part of the element.

For example, when a substrate is placed in an aqueous solution containing electrolytes (ions), the PN junction absorbs light (infrared rays, etc.) and generates an electric current. This current is A connected to each diffusion layer.
An electrical reaction occurs between the I electrodes and the AI main electrode is electrolyzed. This phenomenon occurs even in gases such as plasma, and the current generated by photovoltaic force tends to cause corrosion of the AI main electrode and deterioration of device characteristics.

As explained above, in the wiring process, plasma is often used because it is necessary to process at low temperatures, which tends to cause corrosion of the wiring and deterioration of device characteristics. Furthermore, the deterioration of device characteristics that has occurred is difficult to recover from in low-temperature processes.

Among the deterioration of device characteristics, it is known that the wiring connected to the gate of a MOS transistor acts as an antenna and collects charge, causing deterioration of the breakdown voltage of the gate oxide film and fluctuation of the threshold value (e.g. May 1989 VLS Ichikunoroshii Symposium Preliminary Lecture Collection 9-2 “Gate Oxide Charge and Its Elimination Foremetal Antenna Capacitor and Transistorine VLSI CMOS
Double layer metal technology (GATE 0X
IDECHARGEAND ITS ELI Former NATI
ON FORMETAL ANTENACAPAC+T
ORAND TRANSISTORIN VLSI C
MOS DOUBLE LAYER METAL TECHN
OLOGY) J). The phenomenon is that the larger the area of connected wiring, the more severe the degree of deterioration.In highly integrated devices, wiring tends to be long, and as the wiring area increases, it is more likely to deteriorate. (Reference: Solid state technology (S solid S)
tate Technology) Japanese version (198
9-02) 29th to 34th pages.

Y, N15hi).

Means for Solving the Problems In order to solve the above problems, the present invention provides a first metal conductor film formed in a desired pattern on a semiconductor substrate, and a first metal conductor film formed on the metal conductor film and on the first metal conductor film. A first insulating film with a thickness of 0.1 to 0.3 uta formed only by thermal reaction is formed on the area where there is no metal conductor film, and a second insulating film is formed on the first insulating film on the area where there is no first metal conductor film. An insulating film is embedded, a third insulating film is formed on the first insulating film and the second insulating film, and the second metal conductor film has a desired pattern. The first insulating film and the third insulating film are connected through the openings.

Also, the process of forming semiconductor elements on various semiconductor substrates,
The step of forming at least two or more layers of metal wiring, the step of ion-implanting hydrogen from the front or back surface of the semiconductor substrate, and subsequent heat treatment at a temperature within the range of 400 to 500° C. in an atmosphere containing hydrogen.

Also, the process of forming semiconductor elements on various semiconductor substrates,
A step of forming a first metal wiring pattern, a step of forming a first insulating film formed only by thermal reaction on the first metal wiring, and a step of forming a second insulating film formed by various methods on the first insulating film. a step of etching the second insulating film leaving at least a portion of the first insulating film and embedding it between the first metal wirings; a third insulating film formed by various methods;
a step of growing an insulating film on the first insulating film and the buried second insulating film; a step of etching the third insulating film and the first insulating film using a mask with a predetermined pattern; A second metal wiring is formed to form a predetermined pattern.

Effect: In the structure and method according to the present invention, deterioration near the gate oxide film caused by charges during the wiring formation process is less likely to occur (or even if it occurs, the deterioration is effectively suppressed. As a result, multilayer The manufacturing yield of highly integrated circuit elements with wiring structures is improved.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a step-by-step sectional view of a first embodiment for explaining the present invention.

First, as shown in FIG. 1(a), a first metal wiring 2 is formed on a substrate 1 on which a semiconductor element has already been formed.

This was made of AI containing 0.5% Cu, and the film thickness was 1.0 μm.

Although AI containing about 0.5% Cu was used here, any material that can be used as wiring, such as AI or an alloy of AI and Si, may be used. Needless to say, there are no particular restrictions on the concentration of additives such as Cu and Si at this time. In addition, although the film thickness of the wiring was set to 1.0 μm in the first embodiment, it is actually necessary to change the film thickness depending on the formation of the base substrate, and the usage range is 0.3 to 1.0 μm. Especially suitable is about 0.6 pm.

Next, as shown in FIG. 1(b), a thermally reactive oxide film 3 is deposited to a thickness of 100 nIIl by a thermal reaction of an ozone-TE01 system, that is, an insulating film that can be grown without using plasma. The thickness of the thermally reactive oxide film 3 may be any value that can prevent ions, electrons, etc. that enter from the plasma from reaching the wiring, and in reality, the film thickness is 50 to 300 nm.
It is sufficient as long as it is of a certain extent. Here, an ozone TEO3-based thermal reaction was used to form the thermally reactive oxide film 3, but atmospheric pressure CV
The D oxide film growth method can also be used.

Also, although we have talked about using an oxide film here,
An insulating film such as a nitride film, an oxynitride film, or an alumina film can be used.

Next, as shown in FIG. 1(C), about 2 pm of p-8iN4 is further grown. Plasma was used to form the insulating film (pSiN) at this time, but in the previous step the first metal arrangement s2
Since it is already covered with the thermally reactive oxide film 3, damage caused by plasma is less likely to occur.

Here, p-3iN4 was grown to a thickness of 2 μm,
It is necessary to adjust the film thickness according to the level difference and shape of the underlying substrate.

Next, as shown in FIG. 1(d), using an RIE apparatus, p-3iN4 is buried and planarized in the region where the first metal wiring 2 is not formed by etching back. As for the etch-back method, the pSiN may be directly etched back after the p-8iN is grown, or the p-3iN and the resist may be simultaneously etched using a resist. It is also possible to fill in the remaining grooves with spin-on glass (SOG) after such etch-back. S using RIE method
In the etching of the i-nitride film, since the etch rate of the oxide film is slow, the previously formed thermally reactive oxide film 3 is not etched much. Therefore, the first metal wiring is not exposed to plasma even in an etch-back process using an RIE apparatus. The first step is also the etchback process of the embedded pSiN5.
Plasma is used because the metal wiring is not exposed to plasma, but damage caused by plasma is unlikely to occur.

Next, as shown in FIG. 1<e>, an interlayer insulating film 6 is formed to a thickness of about 200 rv to insulate the lower wiring and the upper wiring to form a multilayer wiring and to reduce the capacitance. do. A film thickness of 100 to 200 na+ is sufficient for insulation, but a thicker film is advantageous in order to reduce capacitance.

If the film thickness exceeds 500 nm, the formation conditions for later forming via holes become difficult;
A film thickness within the range of nm is practically suitable.

The insulating film 6 contains plasma SiO2, ozone-TEO3
Any oxide film produced by thermal reaction of the system, atmospheric pressure CVD oxide film, plasma nitride film, oxynitride film, etc. may be used, but since the insulating film capacitance changes depending on the dielectric constant difference of each film, oxynitride film A film or a plasma nitride film needs to be thicker than a Si oxide film.

FIGS. 1(f) and 1(g) are cross-sectional views showing the step of forming a pie hole. Figure (f) shows a state in which the insulating film 6 has been etched halfway using an RIE device using the mask 7, and Figure (g) shows a state in which the insulating film 6 has been etched halfway using an RIE device using the mask 7.
The remaining film is etched using a downstream etcher (CDE) device. Here, the via holes are formed by etching in two stages using RIE.
This is to prevent damage caused by. If the entire wafer is etched (until the first metal wiring 1 is exposed) using the RIE equipment, the via holes of the first metal wiring will be exposed to the plasma, causing damage. Therefore, the etching should be stopped midway and the wafer exposed to the plasma. (Even if plasma is used to generate radicals, if there is no wafer in the plasma, only radicals and neutral reaction products will reach the wafer, so no damage will be caused by the plasma.) Additional etching is being done.

Then, as shown in FIG. 1(h), the second metal wiring 8
grow and pattern.

Thereafter, the second interlayer film and the third metal wiring can be formed by repeating the same process.

According to the method explained above, the metal wiring is not exposed to plasma (therefore, there is little deterioration of the characteristics of the element.In the conventional general method, when growing the interlayer insulating film, a flattening process by etchback is performed). Both devices were exposed to plasma during the formation of via holes, resulting in thicker (deteriorated) device characteristics.

Although the case of two-layer wiring has been described here, the same process can be performed for three-layer wiring or four-layer wiring.

FIG. 2 shows an element in which a thermal CVD oxide film is formed on the first wiring after forming the first wiring in the first embodiment to make the first wiring unaffected by plasma, and a conventional method. The relationship between the area of the first wiring and the amount of change in threshold voltage of an element in which a flattening process is performed using plasma after forming the first wiring is shown. The area of the wiring was standardized with 104 μI2 as 1, and the formed element was an n-type channel transistor with a gate width of 1.4 μm and a gate length of 1.0 μm.

This result shows that in the conventional method, the amount of change in threshold voltage varies depending on the area of the wiring, which must be taken into account when designing the element, making it complicated.

On the other hand, in the present invention, even if the wiring area changes, the threshold voltage remains constant (no change), and device design is easy, and it is clear that device design will become easier even when higher integration is achieved in the future.

Figure 3 shows a transistor with the configuration used in Figure 2.
The amount of change in threshold voltage when the first wiring is formed and then flattened using plasma, the amount of change in threshold voltage when the second wiring is formed and then flattened using plasma, and the second wiring is flattened using plasma. 3 shows the relationship between the amount of change in the threshold voltage of the wiring when the wiring No. 3 is formed and then flattened with plasma.

In conventional technology, even if the wiring area is the same, the threshold voltage of the transistor connected to the wiring in the lower layer varies greatly. Threshold voltage fluctuates widely.

On the other hand, in the present invention, even if a multi-layer wiring structure such as a two-layer wiring or a three-layer wiring is adopted, the fluctuation in the threshold voltage is small.

From this, it can be seen that according to the present invention, there is no need to consider changes in threshold voltage even when forming a multilayer wiring structure, and element design is easy.

The deterioration of device characteristics that occurs here is due to the charge from the plasma causing a locally high electric field, or the device absorbing light generated by the plasma, and the current flowing inside the device causes deterioration of the device characteristics. It is thought that he was invited.

FIG. 4 is a diagram for explaining a second embodiment of the present invention, which is a method of forming a first metal interconnect without drawing it long. Figure 4(a) is a plan view, Figure 4(b)
is a sectional view taken along the line A-A' in Fig. 4(a), and Fig. 4(
C) is a sectional view taken along line BB' in FIG. 4(a).

This method, independent of the method described in FIG. 1, is to prevent deterioration of device characteristics by devising the arranged pattern.

In the conventional wiring method, the first metal wiring to the gate electrode is long (wired, but this leads to deterioration of the device characteristics), so a long first metal wiring as shown in Figure 4 (a) is required. In such a case, if you cut the first metal wiring and connect it to the second metal wiring, the gate electrode will not be connected to the long first metal wiring in the first metal wiring manual process, so the element Characteristics do not deteriorate.

In the figure, 9 is a gate, 10 is a first metal wiring, 11 is a drain, and 12 is a second metal wiring.

Here, the allowable length of the first metal wiring is 0.5~
It is about 1+a+n. Of course, plasma damage will occur even if the second metal wiring is connected, but the third
As explained in the figure, when the wiring area is the same, the plasma effect due to the first metal wiring and the plasma effect due to the second metal wiring are the same. This is about 1/4 to 1/2 compared to when doing this, and the occurrence of damage can be suppressed.

Here, transistor size radius (W)/length (L) 1.4
If it is ua+/1.0ulI (n channel) and the goal is for the threshold voltage fluctuation to be 0.1V or less in the final process, the allowable area of the wiring connected to the gate electrode is Approximately 1000um" for wiring, approximately 3000Ij112 for second metal wiring, and approximately 5000μm2 for third metal wiring
It will be about. 1100 each for wiring part 1-0μ
Corresponds to 0p, 3000μ+n, and 5000μm. Even if the transistor size is W/L=20 μII/1.0 μ, the appropriate wiring length is 10 m for the first metal wiring and 30 rm for the second metal wiring.

The third metal wiring is about 50a+m. Judging from the normal wiring length, this length cannot be said to be long enough (Sonorad State Technology (SOLID 5TATETEC)
HNOLOGY) Japanese version February 1989 No. 29-34
Page ``Challenges of rcMO8 Technology'' Figure 8).

A third embodiment of the present invention is a manufacturing method that recovers deterioration of device characteristics that has occurred at a low temperature.

As explained above, the deterioration in device characteristics is somewhat recovered by heat treatment in an atmosphere containing hydrogen at a temperature in the range of 400 to 450°C, but not completely. The degree of recovery is better at higher temperatures and for longer periods of time.

FIG. 5 shows a cross-sectional view of an element for explaining the third embodiment.

In the figure, 20 is a (100) P-type Si substrate, and 21 is an n-channel MO8l-run transistor formed in the substrate. 22 is a gate oxide film, 23 is a gate electrode, 24 is a first metal wiring, 25.27 is an interlayer insulation film, 26.29 is a buried insulation film, 28 is a second metal wiring, 30 is a third metal wiring, 31 is a This is the final protective film.

An n-channel transistor 21 is formed on a P-type Si substrate 20 using a commonly used planar process. At this time, a gate electrode 23 made of polysilicon is formed on the gate oxide film 22, and a first metal wiring 24 made of AI with a film thickness of 1.0 μm, for example, is formed from the gate electrode, drain, and source, and further a first metal wiring 24 is formed from the gate electrode, drain, and source. For example, a film thickness of 1
．． A plasma Si nitride film of 0 μm is formed as the buried insulating film 26. This plasma Si nitride film is etched back using an RIE apparatus to fill in the unevenness around the first metal wiring 24 and flatten it. Furthermore, an interlayer insulating film with a thickness of 1
．． A 0 μm 81 oxide film is formed. After that, a desired resist pattern is formed by photolithography, and RIE
Using the resist pattern as a mask, the Si oxide film is etched using an apparatus to expose the opening A1 of the first metal wiring 24. Thereafter, AI is deposited, and the AI film is patterned by photolithography and dry etching to form second metal wiring 28. Thereafter, similarly to the formation of the first metal wiring 24, a buried insulating film 29 and an interlayer insulation film 27 are sequentially laminated, and the interlayer insulation film 27 is selectively etched to expose a part of the second metal wiring 28. From above,
After forming the third metal wiring 30 in a desired pattern, a Si oxide film is formed as the final protective film 31.

Next, hydrogen ions are implanted from the upper surface of the Si substrate 20 at an acceleration voltage of 20 keV, an implantation amount of 1, and Ox 10f5/cj.

After that, heat treatment is performed at a temperature of 450° C. for 90 minutes.

The amount of change in threshold voltage of the device formed in this example was about 1/2 to 1/3 of that of the device formed by the process shown in FIG. 5 and heat-treated in a hydrogen atmosphere. .

This is presumed to be because, in the present invention, hydrogen diffuses inside the substrate and reduces the interface states formed directly under the gate oxide film, thereby restoring the device characteristics.

In particular, when a low-pressure CVD5 i nitride film is formed under the first wiring, hydrogen is prevented from diffusing by the low-pressure CVD5 i nitride film, so heat treatment in a hydrogen atmosphere will not work effectively. In the method of the present invention, in which hydrogen is pre-implanted and heat treated, the amount of change in threshold voltage is stably recovered.

Here, the implantation energy is 50 to 500 keV when implanting from the back surface, and 10 to 50 keV when implanting from the front surface, and the implantation amount is I x 1015 to 5×
10160I11-2 is suitable. As for the heat treatment conditions after implantation, heat treatment in a hydrogen atmosphere at a higher temperature and for a longer time is effective, but since it is necessary to avoid melting the AI, it is necessary to heat treatment at a temperature in the range of about 450 to 500 °C for 10 to 500 °C.
A time in the range of 90 minutes is suitable. It is conventionally known to perform heat treatment by implanting hydrogen ions during the process, for example, before forming an interlayer insulating film under the first metal wiring or before forming the first wiring, in order to stabilize the oxide film interface. However, even if hydrogen ions are implanted in the middle of the process, hydrogen will be diffused in the subsequent process and will not be effective against plasma damage in the wiring process, which the present invention aims to solve. In the present invention, hydrogen ion implantation and heat treatment are performed at the end of all steps, which is more effective.

Furthermore, whether hydrogen ions are implanted into the front surface or the back surface of the substrate, the thermal diffusion of hydrogen is rapid and the same effect can be achieved.

However, the film thicknesses of the wiring and the insulating film described above are merely exemplary values, and may be appropriately selected experimentally. Further, in this embodiment, a three-layer AI' structure is used, but the same effect can be obtained even if the present invention is applied to a single-layer, two-layer, or three or more layer structure.

In addition, although AI was used for the wiring, A1 containing Cu and Si
Alloys may be used, and Si oxide films, Si nitride films, Si oxide films containing boron (B) or phosphorus (P), and oxynitride films may be used as buried insulating films, interlayer insulating films, and protective films. Can be used.

As described in detail, according to the present invention, it is possible to reduce the occurrence of deterioration near the gate oxide film caused by charges during the wiring formation process, or to effectively eliminate the deterioration that has occurred. As a result, highly integrated circuit elements having a multilayer wiring structure can be stably manufactured at a high yield.

[Brief explanation of drawings]

FIGS. 1(a) to (h) are process-order cross-sectional views for explaining the first embodiment of the present invention, and FIG. 2 is a characteristic showing the amount of change between the first wiring area ratio and the threshold voltage. A curve diagram, FIG. 3 is a characteristic curve diagram showing the relationship between the number of stacked metal wiring layers and the amount of change in threshold voltage, FIG. 4(a) is a plan view of the main part of the second embodiment of the present invention, Figures 4(b) and (c) are the fourth
A sectional view taken along the line AA' in Figure (a). 5 is a sectional view taken along line B-B', FIG. 5 is a sectional view for explaining the third embodiment of the present invention, and FIGS. 6(a) to 6) are steps for explaining the conventional example. The sectional view and FIG. 7 are plan views of essential parts showing a conventional wiring method. 1...Substrate, 2...First metal wiring, 3
...Thermal reaction oxide film, 4...p-3iN
(plasma nitride), 5... embedded pSiN% 6... interlayer insulating film, 7
...Mask, 8...Second metal wiring, 9
...Gate electrode, 10...First metal wiring, 11...Drain, 12...Second
Metal wiring, 20...P-type Si substrate, 21...
...n-channel MOS transistor, 22...
・Gate oxide film, 23... Gate electrode, 24.
...First metal wiring, 25... Interlayer insulating film, 26... Buried insulating film, 27...
Interlayer insulating film, 28... Second metal wiring, 29...
...Embedded insulating film, 30...Third metal wiring, 31...Protective film. Name of agent: Patent attorney Shigetaka Awano and one other person 7dnL (
10', ttm' = 1) Magic JhM number of track layers/1 /l Figure eaves v1

Claims (7)

[Claims] (1) A first layer formed in a desired pattern on a semiconductor substrate.
and a first insulating film with a thickness of 0.1 to 0.3 μm formed by thermal reaction on the metal conductor film and on the region where the first metal conductor film is not provided, Said first
A second insulating film is buried on a region of the insulating film where the first metal conductor film is not provided, and the first insulating film and the second insulating film are connected to each other.
has a third insulating film on the insulating film, and has a desired pattern, and a second metal conductor film is connected to the first insulating film and the third insulating film having the desired pattern. A semiconductor device characterized by being connected through an opening. (2) having a third metal conductor film and a fourth metal conductor film on the second metal conductor film, and an insulating film structure between the first metal conductor film and the second metal conductor film; Similarly, an insulating film is formed between the second metal conductor film and the third metal conductor film and between the third metal conductor film and the fourth metal conductor film. The semiconductor device according to claim 1, characterized in that: (3) A semiconductor device characterized in that semiconductor elements formed on various semiconductor substrates are interconnected by at least two layers of metal wiring, and the length of one first metal wiring does not exceed 10 mm. (4) the process of forming semiconductor elements on various semiconductor substrates;
A step of forming at least two or more layers of metal wiring, a step of ion-implanting hydrogen from the front or back surface of the semiconductor substrate, and a step of subsequently performing heat treatment at a temperature within the range of 400 to 500° C. in an atmosphere containing hydrogen. A method for manufacturing a semiconductor device, characterized by: (5) forming semiconductor elements on various semiconductor substrates;
a step of forming a first metal wiring pattern, a step of forming a first insulating film formed only by thermal reaction on the first metal wiring, and a step of forming a second insulating film formed by various methods on the first metal wiring. a step of etching the second insulating film leaving at least a portion of the first insulating film and embedding it between the first metal wirings; a third insulating film formed by various methods; a step of growing a film on the first insulating film and a buried second insulating film, and a step of etching the third insulating film and the first insulating film using a mask with a predetermined pattern. . A method of manufacturing a semiconductor device, comprising the steps of forming a second metal wiring and forming a predetermined pattern. (6) In the step of etching the third insulating film and the first insulating film using a mask with a predetermined pattern, the third insulating film and the first insulating film are etched without exposing the first metal wiring.
and a part of the first insulating film, and then etching the remaining part of the first insulating film using only radicals without placing the semiconductor substrate in plasma, and etching the remaining part of the first insulating film using only radicals, 6. The method of manufacturing a semiconductor device according to claim 5, further comprising exposing a surface of the first metal wiring. (7) Claim 6 characterized in that the step is repeated multiple times.
A method of manufacturing the semiconductor device described above.